CN107359142A - Substrate-less interposer and semiconductor device using the same - Google Patents
Substrate-less interposer and semiconductor device using the same Download PDFInfo
- Publication number
- CN107359142A CN107359142A CN201710293806.8A CN201710293806A CN107359142A CN 107359142 A CN107359142 A CN 107359142A CN 201710293806 A CN201710293806 A CN 201710293806A CN 107359142 A CN107359142 A CN 107359142A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- intermediary layer
- semiconductor device
- electrically
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000002955 isolation Methods 0.000 claims abstract description 40
- 239000011521 glass Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 109
- 239000000463 material Substances 0.000 claims description 20
- 238000005538 encapsulation Methods 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 claims description 8
- 238000007639 printing Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 4
- 239000011368 organic material Substances 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 143
- 238000000034 method Methods 0.000 abstract description 20
- 230000008569 process Effects 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000012797 qualification Methods 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract description 5
- 238000000576 coating method Methods 0.000 abstract description 5
- 239000012044 organic layer Substances 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000012858 packaging process Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 39
- 238000005553 drilling Methods 0.000 description 9
- 239000004744 fabric Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 239000010703 silicon Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010494 dissociation reaction Methods 0.000 description 4
- 230000005593 dissociations Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920000297 Rayon Polymers 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000037361 pathway Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 241001562042 Physa Species 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 239000012788 optical film Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000016 photochemical curing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Geometry (AREA)
Abstract
The invention provides a substrate-free interposer and a semiconductor device using the same, in particular to a substrate-free interposer without using pre-formed wafer, glass or organic layer, etc., which is formed with a plurality of conductive paths communicating the upper and lower surfaces in an insulation isolation layer solidified by deposition or coating, etc., and one side surface of the insulation isolation layer is provided with at least one circuit redistribution layer, each circuit redistribution layer is respectively provided with a dielectric layer and a plurality of conducting wire patterns, and a plurality of electrode paths electrically connected with part of the conducting wire patterns are formed on the outermost circuit redistribution layer different from the insulation isolation layer, thus, the thickness of the insulation isolation layer can be effectively controlled, the conductive paths are more precise and finer, the number and density of pins are greatly improved, and the interposer can be reduced to be more suitable for subsequent heating and pressurizing processes, thus not only effectively improving the production speed and qualification rate of the interposer, meanwhile, the interposer can meet the requirements of the subsequent packaging process.
Description
Technical field
The present invention relates to a kind of intermediary layer technical field of semiconductor device, specifically refers to one kind without using advance
The substrate of the wafer of shaping, glass or organic layer without substrate intermediary Rotating fields, so that the thinning of intermediary layer and more letters can be met
The demand of number pin, reduces unnecessary time course, while has the qualification rate for improving semiconductor device and reduce cost
Effect.
Background technology
Press, with flourishing for electronic industry, electronic product tends to be compact in kenel, therefore its application
Semiconductor device functionally also gradually marches toward high-performance, high function, the R＆D direction of high speedization, and also therefore semiconductor fills
The semiconductor wafer put is by continuous miniaturization.Usual semiconductor wafer microminiaturization most straightforward approach relies on lithographic skill
Art progresses greatly, but lithographic techniques are gradually close to its physics limit now, therefore solution must go to longitudinal direction from breadth wise dimension
Yardstick；In addition, multifunction electronic product such as mobile phone etc., is made up of all kinds of key modules, therefore in terms of product design, not only
Progressing greatly for single first component must be directed to, must more consider a heterogeneous integration for element and the presentation of overall efficiency, thus just has three-dimensional
The development of semiconductor device (3D IC).
Simultaneously as the line pattern of semiconductor wafer is contracted to the size of tens of nms, made crystal grain incorporates
More calculation functions and the more transistor elements of number so that the also rapid multiplication of the quantity of its signal pin (I/O),
It is related also to cause traditional die package technology to meet with extremely harsh challenge.
And preferably 3D IC, each module will be to stack pattern encapsulation, longitudinal link can also reduce conductive channel length
It is a lot of, and then increase efficiency, this process then tests the heterogeneous integration to progress greatly with interelement of process technique.In the 3D that marches toward
On IC road, also there is the development of transitional 2.5D IC now, regardless of whether be 3D IC or 2.5D IC development, it is main equal
System connects the electricity between printed circuit board (PCB) or package substrate and semiconductor wafer by a kind of intermediary's Rotating fields (Interposer)
Signal, this intermediary layer improves the packaging density of product just as link nm and the passage in the millimeter world, in common
Interlayer is just like silicon intermediary layer (Si Interposer), glass intermediary layer (Glass Interposer) and organic intermediary layer
(Organic Interposer) etc..
The structure of these described intermediary layers is formed on the substrate (silicon, glass, organic layer ...) of an advance comprising
Perforation, such as silicon perforation (Through-Silicon Via, TSV), glass are perforated (Through-Glass Via, TGV) or had
Machine layer is perforated (Through Organic Via, TOV), and the circuit redistribution layer on the perforation substrate
(Redistribution layer, RDL), the bottom of the substrate is made electrically to combine the larger encapsulation base of spacing by conductive pad
The wafer-covered solder pad of plate, and the superiors' circuit of the circuit redistribution layer has electronic pads, electrically to combine spacing by solder bump
The signal pin (I/O pins) of less semiconductor wafer, re-forms packing colloid, and the package substrate is combined has height
The semiconductor die device of wiring density electric connection pad, and reach the purpose for the semiconductor wafer for integrating high wiring density.It is this
Structure is widely used in industry, as TaiWan, China patent of invention No. 093132237, No. 099143617 and in
In the patent cases such as state's patent of invention No. 200910130333.5 and No. 201210592167.2.
And the composition of existing intermediary's Rotating fields is as shown in figure 1, by taking the structure of the intermediary layer 100 of silicon perforation as an example, its
It is that perforation 102 is formed with drilling techniques such as etching or lasers on the wafer substrate 101 of an advance comprising, for inserting conduction material
Material forms conductive channel 103, and the wafer substrate 101 is pasted on into a support plate 200, is provided with chemical mechanical milling method and carries out crystalline substance
The thinning of physa plate 101, after circuit redistribution layer 105 and electrode path 106 is formed, by the wafer substrate 101 and support plate
200 dissociation, and form an intermediary layer 100.
Because the circuit miniaturization by semiconductor wafer is with contacting increased number of influence, industry centering interlayer is not
Carrying out demand, comprising thickness to get over Bao Yuehao, the density of pin the higher the better (Pitch is the smaller the better) and wire more thin better
(Line/Space is the smaller the better).Due to that in existing intermediary's Rotating fields, need to be bored on the wafer substrate of advance comprising
Hole, therefore its difficulty is also with regard to more and more higher, and the integrality in the aperture of drilling, the precision of pitch-row and hole position and hole shape is with regard to face
Face great challenge.Furthermore existing Drilling operation can cause the structure of wafer substrate to destroy, slight crack, make wafer substrate rear
Ruptured in continuous processing procedure because heating or pressurizeing, cause the lifting of disqualification rate.Furthermore in order to allow script thickness about 600~
700 microns of wafer substrate, the thickness requirement of semiconductor device agency Rotating fields can be met, can be ground using chemical machinery
Mill method is ground to the back side of wafer substrate, its thickness is thinned to 25~200 microns, due to needing to remove suitable thickness
Wafer substrate, therefore can expend for quite a long time；And, it is also possible to the wafer substrate after grinding is caused, is produced local
Or the defects of integral thickness inequality, or the problems such as cause crystal round fringes to damage, and cause the reduction of product qualification rate rate.In addition,
After thinning is ground, the phenomenon for having warpage (War page) produces the wafer substrate of advance comprising, therefore subsequently will be to thinning
Wafer substrate be processed also relative difficulty, the probability that wafer substrate fragmentation occurs increases.
Although existing intermediary layer before thinning grinding, can use the skill of temporary fitting (Temporary Bonding)
Art, pass through viscose glue (such as UV Tape, UV photocuring solutions glued membrane, UV constrictive types liquid adhesive) or the side of Electrostatic Absorption
Formula, wafer substrate are attached on support plate and are processed again, can so rely on carrying to provide wafer substrate enough branch for support plate
Support.But nonetheless, still easily occur if the wafer substrate thickness after grinding is excessively thin in follow-up dissociation or processing procedure
Rupture.Also, because used viscose glue can only be resistant to 200 degree Celsius or so of temperature, therefore it can not add in high temperature furnace pipe
Work, it can not also carry out the processing procedure of high tempering.Along with the wafer substrate pasted each other is not integrally formed with carrier, in temperature
Also easily burst in the higher environment of degree, also easily cause the difficulty that follow-up chip bonding technique becomes.
As can be seen here, manufactured no matter the above-mentioned existing intermediary layer using advance comprising substrate ties up in upper, structure with making
Use, it is clear that there are many inconvenience and defect, therefore need further to be improved in structure.In view of this, the present inventor
Be to be directed to existing intermediary layer problem encountered further investigated in structure, and by be engaged in for many years the research and development of related industry with
Manufacturing experience, the improvement through being continually striving to studying, successfully develop finally it is a kind of do not use advance comprising substrate without substrate
Intermediary layer and apply that semiconductor device, with can effectively solve the problem that those existing because need to use perforation substrate derived from inconvenience
With puzzlement.
The content of the invention
Therefore, the main object of the present invention is to provide one kind without substrate intermediary layer, can be without the use of advance comprising
Substrate, the manufacture without such as existing intermediary layer need to use the processing procedure to substrate drilling and substrate thinning, in so can not only making
The more miniaturization of the conductive channel of interlayer, and the quantity and density of its pin can be greatly improved.
Also, another main purpose of the present invention is to provide one kind without substrate intermediary layer, it can directly control intermediary layer
Thickness, meet requirement of the manufacturer for intermediary's thickness, avoid occurring as practised formula intermediary layer because of drilling and splitting during thinning
Trace trace or stress concentration, and cause intermediary layer to rupture loss because pressurizeing or heating in following process, entirety can be effectively improved
Qualification rate.
In addition, another main purpose of the present invention is to provide a kind of semiconductor device of the application without substrate intermediary layer, its energy
The quantity and density of its pin are improved, further promotes the high-performance, high function and high speedization of semiconductor device.
Based on this, the present invention is mainly by following technological means, to implement foregoing purpose and efficacy：
One kind is without substrate intermediary layer, it is characterised in that：It is to be dielectrically separated from one by what the technology for depositing or being coated with was formed
Conductive path is connected formed with plural number in layer, respectively the conductive path both ends and is exposed by the upper and lower surface of dielectric isolation layer
Come, and respectively the conductive path in the side surface of dielectric isolation layer one formed with a conductive pad；
The side surface of dielectric isolation layer one has the circuit redistribution layer that one or more layers are stacked with, respectively the circuit weight
Layer of cloth can be electrically connected with adjacent conductive path or circuit redistribution layer；
Different from the outermost layer circuit redistribution layer of dielectric isolation layer formed with plural electrode path, respectively the electrode path with
Adjacent circuit redistribution layer is electrically connected, and respectively the electrode path on adjacent lines redistribution layer surface formed with an electrode
Pad.
It is described without substrate intermediary layer, wherein：The dielectric isolation layer is selected from dielectric material, insulating materials or semiconductor
Material makes.
It is described without substrate intermediary layer, wherein：The dielectric isolation layer is formed by silicon materials deposition.
It is described without substrate intermediary layer, wherein：The dielectric isolation layer is formed by glass material coating.
It is described without substrate intermediary layer, wherein：The dielectric isolation layer is formed by organic material coating.
The present invention also provides a kind of semiconductor device using above-mentioned no substrate intermediary layer, it is characterised in that：This is without substrate
The electrode path of intermediary layer electrically combines at least semiconductor wafer, and being formed at simultaneously in an encapsulation structure body, makes the semiconductor
Device can utilize the conductive path without substrate intermediary layer to be selectively electrically incorporated on a printed circuit board (PCB).
The present invention also provides a kind of semiconductor device using above-mentioned no substrate intermediary layer, it is characterised in that：This is without substrate
The electrode path of intermediary layer electrically combines at least semiconductor wafer, and the conductive path without substrate intermediary layer electrically combines
In on a package substrate, and it is formed at simultaneously in an encapsulation structure body, the semiconductor device is selected using the package substrate
Property is electrically incorporated on a printed circuit board (PCB).
The present invention also provides a kind of semiconductor device using above-mentioned no substrate intermediary layer, it is characterised in that：This is without substrate
The electrode path of intermediary layer electrically combine at least semiconductor wafer and an at least upper strata without substrate intermediary layer, wherein on this
The electrode path without substrate intermediary layer of layer electrically combines another semiconductor wafer, and is formed at simultaneously in an encapsulation structure body, makes
The semiconductor device can utilize the conductive path without substrate intermediary layer of the lower floor to be selectively electrically incorporated into a printed circuit
On plate.
The present invention also provides a kind of semiconductor device using above-mentioned no substrate intermediary layer, it is characterised in that：This is without substrate
The electrode path of intermediary layer electrically combine at least semiconductor wafer and an at least upper strata without substrate intermediary layer, wherein on this
The electrode path without substrate intermediary layer of layer electrically combines another semiconductor wafer, and the leading without substrate intermediary layer of the lower floor
Electric pathway is electrically incorporated on a package substrate, and is formed at simultaneously in an encapsulation structure body, the semiconductor device is utilized
The package substrate is selectively electrically incorporated on a printed circuit board (PCB).
In this way, by the realization of above-mentioned particular technique means, no substrate intermediary layer provided by the present invention can make conduction
Passage is more accurate, more miniaturization, greatly improves the quantity and density of its pin, and the drilling as practised formula will not occur or thinning adds
Work and the phenomenon for increasing work, and the speed of production of intermediary layer can be improved, and it is avoided that intermediary layer is made because being processed drilling or thinning
Into structural damage and slight crack, qualification rate can be effectively improved, and successive process is suitable for pressurization and the environment heated,
The different product demand of manufacturer can be met.
It is to lift the present invention below to enable your juror to further appreciate that composition, feature and the other purposes of the present invention
Preferred embodiment, and coordinate schema to describe in detail as after, while allow and be familiar with this those skilled in the art and can be embodied.
Brief description of the drawings
Fig. 1 is cross-sectional structure schematic diagram of the existing intermediary's Rotating fields in forming process.
Fig. 2 is the cross-sectional structure schematic diagram of the invention without substrate intermediary layer, for illustrating that it forms aspect and its relative pass
System.
Fig. 3~Fig. 5 is cross-sectional structure schematic diagram of the present invention without substrate intermediary layer in manufacturing process.
Fig. 6 is the cross-sectional structure schematic diagram of the invention without another embodiment of substrate intermediary layer.
Fig. 7 is the cross-sectional structure schematic diagram using the semiconductor device of the invention without substrate intermediary layer.
Fig. 8 is the cross-sectional structure schematic diagram using the semiconductor device another embodiment of the invention without substrate intermediary layer.
Description of reference numerals：10 without substrate intermediary layer；30 conductive paths；31 conductive pads；32 inside conductors；40 are dielectrically separated from
Layer；50 circuit redistribution layers；51 wire patterns；52 dielectric layers；Breach in 53；60 electrode channels；61 electronic padses；80 printed circuits
Plate；81 wafer-covered solder pads；85 are electrically connected with body；90 semiconductor wafers；91 signal pins；95 are electrically connected with body；500 semiconductors fill
Put；501 encapsulation structure bodies；505 are electrically connected with body；A support plates；B cushions；100 intermediary layers；101 wafer substrates；102 perforation；103
Conductive channel；105 circuit redistribution layers；106 electrode paths；200 support plates.
Embodiment
The present invention is a kind of no substrate intermediary layer and applies that semiconductor device, below by specific specific implementation
Form illustrates the technology contents of the present invention, makes people skilled in the art can be by content disclosed in the present specification easily
Solve advantages of the present invention and effect.So the present invention also can be implemented or applied by other different specific implementation forms.Cause
In the specific embodiment and its component of the invention of this legend of enclosing, it is all about before with after, left and right, top and bottom, on
Portion and bottom and horizontal with vertical reference, are only used for conveniently being described, not the limitation present invention, nor by its component
It is limited to any position or direction in space.Specified size in schema and specification, when can be in the application without departing from the present invention
In the scope of the claims, design according to a particular embodiment of the invention is changed with demand.
For the structure of the present invention, its be such as Fig. 2, Fig. 6 those disclosed herein, should be without wafer, glass or organic layer etc.
Substrate without substrate intermediary layer 10,10A be in a dielectric isolation layer 40 formed by the technology that deposits or be coated with formed with
Plural number connects the conductive path 30 on upper and lower surface, and the side surface of dielectric isolation layer 40 1 has an at least circuit redistribution layer
50, respectively the circuit redistribution layer 50 there is an at least wire pattern 51, and wherein different from the outermost layer circuit weight of dielectric isolation layer 40
Formed with plural electrode path 60 on layer of cloth 50, respectively the electrode path 60 and by the wire pattern 51 of circuit redistribution layer 50 with
The corresponding conductive path 30 of dielectric isolation layer 40 is electrically connected, and this is relied on dielectric isolation layer without substrate intermediary layer 10
40 conductive path 30 electrically combines spacing larger package substrate or the wafer-covered solder pad of printed circuit board (PCB) 80 or package substrate
81, and by electrode path 60 electrically with reference to the signal pin 91 of the less semiconductor wafer 90 of spacing, then pass through packing colloid
Form semiconductor crystalline substance device 500 (as shown in Figure 7, Figure 8)；
As for the detailed composition of the invention without the wherein preferred embodiment of substrate intermediary layer is then such as the three~five figure institute
Show, first, be prepare one in advance can be with the printing opacity support plate A of the selective dissociation of dielectric isolation layer 40 of the present invention, printing opacity support plate A
Surface is available for forming a cushion B, the present invention a preferred embodiment in, this printing opacity support plate A and can be quartz glass,
Pyrex, sodium silica glass or sapphire glass are formed.And cushion B material in some embodiments of the invention
Can be formed by Ceramic optical film, metallic film or the nonmetal film that laser dissociates；
As shown in figure 3, the surface of the cushion B prior to printing opacity support plate A formed with plural number conductive path 30, respectively this lead
There is electric pathway 30 conductive pad 31 and one to be formed at the inside conductor 32 of the upper surface of conductive pad 31 respectively, and utilize deposition, coating
Technology solidified between printing opacity support plate A cushion B surface and each adjacent conductive vias 30 and form the dielectric isolation layer 40, and
Make the top and bottom ends face of conductive path 30 exposed by 40 upper and lower surface of dielectric isolation layer, make respectively the conductive path 30 can connect
Logical 40 upper and lower surface of dielectric isolation layer.In part embodiment, the material and related process of the dielectric isolation layer 40 can bases
The demand of producer is changed, such as dielectric material Dielectric, passivating material (Passivation may be selected
) or the semiconductor such as photonasty insulating polymer material (Photosensitive Isolation polymer) Material
Material makes dielectric isolation layer 40.In certain embodiments, the dielectric isolation layer 40 can be deposited by silicon materials and formed.
In another embodiment, the dielectric isolation layer 40 can be coated with by glass material and be formed.In another embodiment, the dielectric isolation layer
40 can be formed by organic material coating；
In addition, as shown in figure 4, the technology of cloth processing procedure (RDL, redistribution layer) is weighed using circuit, in insulation
The circuit redistribution layer 50 that one or more layers stack is formed on separation layer 40, respectively the circuit redistribution layer 50 includes one and is electrically connected with
The wire pattern 51 and one of conductive path 30 is covered in the dielectric layer 52 of wire pattern 51 and the surface of dielectric isolation layer 40, process
Dielectric layer 52 can have the interior breach 53 that plural number exposes part wire pattern 51, electron-donating to link adjacent circuit weight cloth
50 wire pattern 51 of layer or former electrodes passage 60 (as shown in fourth, fifth figure).Wherein closest to the circuit weight of electrode channel 60
The dielectric layer 52 of layer of cloth 50 can be a dielectric protective materials, such as dielectric material (Dielectric), passivating material
(Passivation Material) or photonasty insulating polymer material (Photosensitive Isolation
The semi-conducting material such as polymer).In certain embodiments, can be stacked on dielectric isolation layer 40 to be formed three layers circuit weight cloth
50 (as shown in Figure 2) of layer.It is another to stack to form one layer of circuit redistribution layer in certain embodiments, on dielectric isolation layer 40
50, and directly in formation electrode path 60 (as shown in Figure 6) in the circuit redistribution layer 50.To be illustrated, above-mentioned line
The quantity of road redistribution layer 50, visual demand are adjusted.With different encapsulation specifications, the more circuit weight cloth of number can be formed
Layer 50；
Also, such as Fig. 5, the electrode channel 60 for being formed at the surface of the superiors' circuit redistribution layer 50 passes through the circuit by plural number
The electronic pads 61 of its part wire pattern 51 of the electrical connection of breach 53 is formed in redistribution layer 50.Finally according to cushion B material
Material selection corresponding to dissociation technique, such as by laser light illumination vaporize in a manner of dissociate cushion B, enable support plate A with insulation every
The lower surface of conductive pad 31 of absciss layer 40 and conductive path 30 separates, and forms one without substrate intermediary layer 10,10A (Fig. 2, Fig. 6 institutes
Show).
Furthermore it is shown in Figure 7, being applied the present invention without substrate intermediary layer 10 in follow-up semiconductor device
In 500 encapsulation structure body 501, the electronic pads 61 of the electrode channel 60 of the substrate intermediary layer 10 without semiconductor device 500 can be with
The signal pin 91 of the less semiconductor wafer 90 of spacing is electrically incorporated into by plural number electric connection body 95 respectively, it is described
It can be the conduction materials such as tin ball, copper post, principal column that these, which are electrically connected with body 95,.In certain embodiments, the semiconductor device 500
It is electrical further the conductive pad 31 of the conductive path 30 without substrate intermediary layer 10 can be electrically connected with body 85 by plural number respectively
It is incorporated on the wafer-covered solder pad 81 of the larger printed circuit board (PCB) 80 of spacing or package substrate, these described are electrically connected with body 85
Can be the conduction materials such as tin ball, copper post, principal column.And reach the purpose for the semiconductor wafer for integrating high wiring density.
What is more, as shown in figure 8, in certain embodiments, in the encapsulation structure body 505 of the semiconductor device 500 further
Can in a substrate the electrode channel 60 of interlayer 10 electronic pads 61 can respectively by plural number be electrically connected with body 505 electrically tie
Be bonded to a few upper strata without substrate intermediary layer 10A, it can be tin ball, copper post, principal column etc. that described these, which are electrically connected with bodies 505,
Conduction material, different work(are electrically combined for this can be layered without substrate intermediary layer 10A from the respectively upper strata without substrate intermediary layer 10
Semiconductor wafer 90, the 90A of energy, it is available for further integrating the semiconductor wafer of high wiring density.What is more, then some implementations
In example, there is IC support plates (IC Carrier) in the semiconductor device 500, with electrical by the IC support plates (IC Carrier)
It is connected on printed circuit board (PCB).
In summary, no substrate intermediary layer provided by the present invention can make conductive channel more precisely, more miniaturization, greatly
Width improves the quantity and density of its pin, while reason does not practise the drilling of formula such as or thinning is processed and increases man-hour, and can improve
The speed of production of intermediary layer, and avoid because drilling or thinning processing and caused by structural damage, can effectively improve qualification rate,
The thickness requirements of manufacturer can be met simultaneously, therefore the surcharge of product can be effectively increased, effectively improve its economic benefit.
So it will be appreciated that the present invention is the splendid invention of an intention, except what effective solution habit formula person was faced asks
Topic, more significantly improves effect, and has no that identical or approximate product is published or openly used in identical technical field, together
When there is the enhancement of effect, therefore the present invention has met patent of invention about novelty and creative important document, is to propose Shen in accordance with the law
Please patent of invention.
Claims (9)
1. one kind is without substrate intermediary layer, it is characterised in that：It is in a dielectric isolation layer formed by the technology for depositing or being coated with
It is interior to connect conductive path formed with plural number, each conductive path both ends and exposed by the upper and lower surface of dielectric isolation layer, and
Respectively the conductive path in the side surface of dielectric isolation layer one formed with a conductive pad；
The side surface of dielectric isolation layer one has the circuit redistribution layer that one or more layers are stacked with, respectively the circuit redistribution layer energy
It is enough to be electrically connected with adjacent conductive path or circuit redistribution layer；
Different from the outermost layer circuit redistribution layer of dielectric isolation layer formed with plural electrode path, respectively the electrode path with it is adjacent
Circuit redistribution layer is electrically connected, and respectively the electrode path on adjacent lines redistribution layer surface formed with an electronic pads.
2. no substrate intermediary layer according to claim 1, it is characterised in that：The dielectric isolation layer be selected from dielectric material, absolutely
Edge material or semi-conducting material make.
3. no substrate intermediary layer according to claim 1, it is characterised in that：The dielectric isolation layer by silicon materials deposit and
Into.
4. no substrate intermediary layer according to claim 1, it is characterised in that：The dielectric isolation layer by glass material be coated with and
Into.
5. no substrate intermediary layer according to claim 1, it is characterised in that：The dielectric isolation layer by organic material be coated with and
Into.
A kind of 6. semiconductor device applied without substrate intermediary layer as any one of Claims 1 to 5, it is characterised in that：
The electrode path without substrate intermediary layer electrically combines at least semiconductor wafer, and being formed at simultaneously in an encapsulation structure body, makes
The semiconductor device can utilize the conductive path without substrate intermediary layer to be selectively electrically incorporated on a printed circuit board (PCB).
A kind of 7. semiconductor device applied without substrate intermediary layer as any one of Claims 1 to 5, it is characterised in that：
The electrode path without substrate intermediary layer electrically combines at least semiconductor wafer, and the conductive path electricity without substrate intermediary layer
Property is incorporated on a package substrate, and is formed at simultaneously in an encapsulation structure body, the semiconductor device is utilized the encapsulation base
Plate is selectively electrically incorporated on a printed circuit board (PCB).
A kind of 8. semiconductor device applied without substrate intermediary layer as any one of Claims 1 to 5, it is characterised in that：
The electrode path without substrate intermediary layer electrically combine at least semiconductor wafer and an at least upper strata without substrate intermediary layer, its
In the electrode path without substrate intermediary layer on the upper strata electrically combine another semiconductor wafer, and be formed at an encapsulation structure body simultaneously
In, the semiconductor device is selectively electrically incorporated into a printing using the conductive path without substrate intermediary layer of the lower floor
On circuit board.
A kind of 9. semiconductor device applied without substrate intermediary layer as any one of Claims 1 to 5, it is characterised in that：
The electrode path without substrate intermediary layer electrically combine at least semiconductor wafer and an at least upper strata without substrate intermediary layer, its
In the electrode path without substrate intermediary layer on the upper strata electrically combine another semiconductor wafer, and the lower floor without substrate intermediary layer
Conductive path be electrically incorporated on a package substrate, and be formed at simultaneously in an encapsulation structure body, enable the semiconductor device
Selectively electrically it is incorporated on a printed circuit board (PCB) using the package substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105113193A TW201739011A (en) | 2016-04-28 | 2016-04-28 | Substrate-free intermediate layer and semiconductor device using the same forming a plurality of conductive paths communicating with an upper surface and a lower surface in an insulated isolation layer |
| TW105113193 | 2016-04-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107359142A true CN107359142A (en) | 2017-11-17 |
Family
ID=60272080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710293806.8A Withdrawn CN107359142A (en) | 2016-04-28 | 2017-04-28 | Substrate-less interposer and semiconductor device using the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107359142A (en) |
| TW (1) | TW201739011A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113838766A (en) * | 2020-06-23 | 2021-12-24 | 祁昌股份有限公司 | Same-side electrical property measuring method for packaging substrate and packaging substrate |
| CN115274475A (en) * | 2022-09-27 | 2022-11-01 | 江苏芯德半导体科技有限公司 | Chip packaging method with high-density connecting layer and chip packaging structure thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006190885A (en) * | 2005-01-07 | 2006-07-20 | Nec Corp | Substrate for layer formation, wiring substrate and its manufacturing method, and semiconductor device and its manufacturing method |
| US20150348895A1 (en) * | 2013-01-21 | 2015-12-03 | Pbt Pte. Ltd. | Substrate for semiconductor packaging and method of forming same |
| CN105304584A (en) * | 2014-07-31 | 2016-02-03 | 恒劲科技股份有限公司 | Interposer substrate and method of manufacturing the same |
| CN105405827A (en) * | 2015-12-22 | 2016-03-16 | 华进半导体封装先导技术研发中心有限公司 | Multi-stacked fanout package structure with low cost and fabrication method thereof |
| CN105655309A (en) * | 2014-11-27 | 2016-06-08 | 鉝晶国际科技有限公司 | Method for manufacturing interposer without chip substrate |
-
2016
- 2016-04-28 TW TW105113193A patent/TW201739011A/en unknown
-
2017
- 2017-04-28 CN CN201710293806.8A patent/CN107359142A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006190885A (en) * | 2005-01-07 | 2006-07-20 | Nec Corp | Substrate for layer formation, wiring substrate and its manufacturing method, and semiconductor device and its manufacturing method |
| US20150348895A1 (en) * | 2013-01-21 | 2015-12-03 | Pbt Pte. Ltd. | Substrate for semiconductor packaging and method of forming same |
| CN105304584A (en) * | 2014-07-31 | 2016-02-03 | 恒劲科技股份有限公司 | Interposer substrate and method of manufacturing the same |
| CN105655309A (en) * | 2014-11-27 | 2016-06-08 | 鉝晶国际科技有限公司 | Method for manufacturing interposer without chip substrate |
| CN105405827A (en) * | 2015-12-22 | 2016-03-16 | 华进半导体封装先导技术研发中心有限公司 | Multi-stacked fanout package structure with low cost and fabrication method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113838766A (en) * | 2020-06-23 | 2021-12-24 | 祁昌股份有限公司 | Same-side electrical property measuring method for packaging substrate and packaging substrate |
| CN115274475A (en) * | 2022-09-27 | 2022-11-01 | 江苏芯德半导体科技有限公司 | Chip packaging method with high-density connecting layer and chip packaging structure thereof |
| CN115274475B (en) * | 2022-09-27 | 2022-12-16 | 江苏芯德半导体科技有限公司 | Chip packaging method with high-density connecting layer and chip packaging structure thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201739011A (en) | 2017-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11728273B2 (en) | Bonded structure with interconnect structure | |
| US10411433B2 (en) | Active silicon optical bench | |
| US11791256B2 (en) | Package substrate and method of fabricating the same | |
| US7087514B2 (en) | Substrate having built-in semiconductor apparatus and manufacturing method thereof | |
| JP4023076B2 (en) | Front and back conductive substrate and manufacturing method thereof | |
| US7884466B2 (en) | Semiconductor device with double-sided electrode structure and its manufacturing method | |
| JPH0220848Y2 (en) | ||
| CN111357102A (en) | Non-embedded silicon bridge chip for multi-chip module | |
| TWI544599B (en) | Fabrication method of package structure | |
| US20120146216A1 (en) | Semiconductor package and fabrication method thereof | |
| CN104051354A (en) | Semiconductor package and fabrication method thereof | |
| WO2021018014A1 (en) | Tsv-based multi-chip package structure and method for manufacturing same | |
| CN107424979A (en) | Method for manufacturing interposer of semiconductor device | |
| TW201742167A (en) | Electronic package and method for fabricating the same | |
| TWM531651U (en) | Substrate-free interposer and semiconductor device using same | |
| CN107359142A (en) | Substrate-less interposer and semiconductor device using the same | |
| JP4407702B2 (en) | Front and back conductive substrate manufacturing method and front and back conductive substrate | |
| TWI508157B (en) | Semiconductor structure and method of manufacture | |
| TW200939442A (en) | Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips | |
| KR20200071920A (en) | Semiconductor package and manufacturing method for the same | |
| CN104733407B (en) | Method for fabricating semiconductor device | |
| US20240186233A1 (en) | Packaging structure and packaging method | |
| TWI810948B (en) | Substrate structure and manufacturing method thereof | |
| TWI775280B (en) | Capacitor integrated structure, capacitor unit and manufacturing method thereof | |
| KR100872130B1 (en) | Method for forming through interconnection and manufacturing printed circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20171117 |
|
| WW01 | Invention patent application withdrawn after publication |