CN107359119B - Super junction power device and manufacturing method thereof - Google Patents
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- 238000002513 implantation Methods 0.000 claims description 12
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention provides a super junction power device and a manufacturing method thereof, and relates to the technical field of semiconductor chip manufacturing. The method comprises the following steps: implanting an N-type epitaxial layer generated by epitaxy on an N-type substrate to form a first P-type region and an N-type cut-off region; forming a P-type injection window of a groove structure on the N-type epitaxial layer between the first P-type region and the N-type cut-off region, wherein the depth of the groove structure is greater than that of the first P-type region; and injecting in the P-type injection window to form a second P-type region communicated with the first P-type region. According to the scheme of the invention, the P-type injection window with enough depth is formed through etching, so that the P-type injection area with enough depth is obtained after ion injection, long-time thermal annealing is avoided, and the charge balance degree of the super junction power device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor chip manufacturing, in particular to a super junction power device and a manufacturing method thereof.
Background
The most important performance of the power device is blocking high voltage, and the device can bear high voltage on depletion layers of PN junctions, metal-semiconductor contacts and MOS interfaces of field effect transistors after being designed. With the increase of the applied voltage, the electric field intensity of the depletion layer is also increased, and avalanche breakdown finally occurs beyond the material limit. The electric field curvature is increased in the depletion region at the edge of the device, the electric field intensity is larger than that in the tube core, avalanche breakdown occurs at the edge of the tube core earlier than that in the tube core in the voltage increasing process, in order to maximize the performance of the device, a voltage dividing structure needs to be designed at the edge of the device, the curvature of a PN junction at the edge of an active region (cellular region) is reduced, a depletion layer is extended transversely, the voltage endurance capability in the horizontal direction is enhanced, and the edge and the inside of the device are simultaneously broken down. The stop ring is arranged between the partial pressure structure and the scribing groove area, is distributed at the outermost periphery of the chip, and is indispensable in high reliability requirements and module packaged devices.
In addition, a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) structure is generally adopted in a conventional power MOSFET, so that in order to bear high voltage, the doping concentration of a drift region is reduced or the thickness of the drift region is increased, but the result that the on-resistance is increased sharply is brought. The on-resistance or breakdown voltage of a typical conventional power MOSFET is related to the power of 2.5, which is referred to as the "silicon limit". The super-junction VDMOS is based on a charge compensation principle, so that the on-resistance and the breakdown voltage of the device are in a 1.32 power relation, and the contradiction between the on-resistance and the breakdown voltage is well solved. Compared with the traditional power MOSFET structure, the super-junction MOSFET structure adopts the alternating P columns and N columns for charge compensation, so that the P area and the N area are mutually depleted, and ideal flat-top electric field distribution and uniform electric potential distribution are formed, thereby achieving the purposes of improving breakdown voltage and reducing on-resistance. However, the prerequisite for achieving the desired effect is charge balance.
However, although the voltage division structure-junction termination structure in the super-junction VDMOS can be formed by diffusion together with the active region, and the improvement of the breakdown resistance of the device is achieved without increasing the process, a long-time thermal annealing is required to be performed in order to reach a sufficient depth to improve the voltage resistance in the P-type implantation region formed directly by implantation around the main junction, and the long-time thermal annealing affects the charge balance in the super-junction VDMOS and further affects the performance of the device.
Disclosure of Invention
The invention aims to provide a super junction power device and a manufacturing method thereof.
To achieve the above object, an embodiment of the present invention provides a method of manufacturing a super junction power device, the method including:
implanting an N-type epitaxial layer generated by epitaxy on an N-type substrate to form a first P-type region and an N-type cut-off region;
forming a P-type injection window of a groove structure on the N-type epitaxial layer between the first P-type region and the N-type cut-off region, wherein the depth of the groove structure is greater than that of the first P-type region;
and injecting in the P-type injection window to form a second P-type region communicated with the first P-type region.
Wherein the manufacturing method further comprises:
thermally oxidizing the surfaces of the first P-type region, the N-type epitaxial layer, the second P-type region and the N-type cut-off region to form a first oxide layer;
photoetching and etching the first oxide layer to form a first opening and a second opening;
forming a conductive layer with high resistance in the first opening, the second opening and the rest of the first oxide layer, wherein the conductive layer is electrically connected with the first P-type region through the first opening, and the conductive layer is electrically connected with the N-type epitaxial layer or the N-type cut-off region through the second opening;
and thermally oxidizing the surface of the conductive layer to form a second oxide layer.
Wherein the first oxide layer includes a first portion and a second portion, the second opening being disposed between the first portion and the second portion.
The conducting layer is made of high-resistance polysilicon.
The doping concentration of the N-type cut-off region is greater than that of the N-type epitaxial layer; the doping concentration of the first P type area is greater than that of the second P type area.
To achieve the above object, an embodiment of the present invention further provides a super junction power device, including:
a first P type region and an N type cut-off region formed on an N type epitaxial layer of an N type substrate;
a downward sunken P-type injection window is formed on the N-type epitaxial layer between the first P-type region and the N-type cut-off region; and
a second P-type region formed by implantation in the P-type implantation window; wherein the content of the first and second substances,
the depth of the P-type injection window is greater than that of the first P-type area;
the first P type area is communicated with the second P type area.
Wherein the super junction power device further comprises:
the first oxide layer is arranged on the surfaces of the first P-type region, the N-type epitaxial layer, the second P-type region and the N-type cut-off region:
a first opening and a second opening disposed on the first oxide layer;
a high-resistance conductive layer disposed in the first opening, the second opening, and the remaining first oxide layer; and
a second oxide layer disposed on the conductive layer; wherein the content of the first and second substances,
the conducting layer is electrically connected with the first P-type region through the first opening, and the conducting layer is electrically connected with the N-type epitaxial layer or the N-type cut-off region through the second opening.
Wherein the first oxide layer includes a first portion and a second portion, the second opening being disposed between the first portion and the second portion.
The conducting layer is made of high-resistance polysilicon.
The doping concentration of the N-type cut-off region is greater than that of the N-type epitaxial layer; the doping concentration of the first P type area is greater than that of the second P type area.
The technical scheme of the invention has the following beneficial effects:
according to the manufacturing method of the super junction power device, the groove is etched to obtain the P-type injection window with the groove structure, and injection is directly carried out in the P-type injection window, so that the second P-type area communicated with the first P-type area can be formed. The depth requirement of the second P type area can be realized by increasing the depth of the groove structure, and the long-time thermal annealing process in the traditional method is reduced, so that the charge balance degree of the super junction device is improved, and the performance of the device is improved.
Drawings
Fig. 1 is a first flowchart of a method for manufacturing a super junction power device according to an embodiment of the present invention;
fig. 2 is a first schematic diagram of implementation of a manufacturing method of a super junction power device to which an embodiment of the invention is applied;
fig. 3 is a second schematic diagram of implementation of a manufacturing method of a super junction power device to which an embodiment of the invention is applied;
fig. 4 is a first schematic structural diagram of a super junction power device to which an embodiment of the invention is applied;
fig. 5 is a second flowchart illustrating a method for manufacturing a super junction power device according to an embodiment of the present invention;
fig. 6 is a third schematic diagram of implementation of a manufacturing method of a super junction power device to which an embodiment of the invention is applied;
fig. 7 is a fourth schematic diagram of implementation of a manufacturing method of a super junction power device to which an embodiment of the invention is applied;
fig. 8 is a fifth implementation schematic diagram of a manufacturing method of a super junction power device to which an embodiment of the invention is applied;
fig. 9 is a schematic structural diagram of a super junction power device to which an embodiment of the invention is applied.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
The invention provides a manufacturing method of a super-junction power device, aiming at the problems that long-time thermal annealing is needed for a voltage division structure-junction terminal structure in the existing super-junction VDMOS to reach the depth of a sufficient P-type injection region, and the long-time thermal annealing can influence the charge balance in the super-junction VDMOS so as to influence the performance of the device.
As shown in fig. 1, a method for manufacturing a super junction power device according to an embodiment of the present invention includes:
102, forming a P-type injection window with a groove structure on the N-type epitaxial layer between the first P-type region and the N-type cut-off region, wherein the depth of the groove structure is greater than that of the first P-type region;
and 103, injecting in the P-type injection window to form a second P-type region communicated with the first P-type region.
Through the steps, the super junction power device shown in fig. 4 is obtained. According to the manufacturing method of the super junction power device, the groove is etched to obtain the P-type injection window with the groove structure, and injection is directly carried out in the P-type injection window, so that the second P-type area communicated with the first P-type area can be formed. The depth requirement of the second P type area can be realized by increasing the depth of the groove structure, and the long-time thermal annealing process in the traditional method is reduced, so that the charge balance degree of the super junction device is improved, and the performance of the device is improved.
Specifically, first, an N-type epitaxial layer 2 epitaxially grown on an N-type substrate 1 is subjected to ion implantation to obtain a first P-type region 3 and an N-type cut-off region 4 as shown in fig. 2. Then, as shown in fig. 3, a P-type implantation window 10 of a groove structure is obtained by dry etching on the N-type epitaxial layer 2 between the first P-type region 3 and the N-type cut-off region 4 using the photoresist 5 as a mask. Thereafter, as shown in fig. 4, ion implantation is performed in the P-type implantation window 10 to form a second P-type region 6 communicating with the first P-type region 3. The photoresist 5 is then removed.
Specifically, the depth of the P-type implantation window 10 in the longitudinal section of the N-type epitaxial layer 2 is greater than the depth of the first P-type region 3 in the longitudinal section of the N-type epitaxial layer 2.
In addition, in order to further improve device performance, on the basis of the foregoing embodiment, as shown in fig. 5, the method for manufacturing a super junction power device according to the embodiment of the present invention further includes, in addition to the foregoing steps 101 and 103:
and 107, thermally oxidizing the surface of the conductive layer to form a second oxide layer.
On the device shown in fig. 4 obtained in the step 101-103, the device shown in fig. 9 is finally obtained by the step 104-107, wherein the first oxide layer 7 and the high-resistance conductive layer 8 are added in the groove structure. The first oxide layer 7 can reduce the influence of surface charges on the junction termination performance. The conductive layer 8 covers the surface of the first oxide layer 7, and contacts the first P-type region 3 through the first opening, and contacts the N-type epitaxial layer 2 or the N-type cut-off region 4 through the second opening. Thus, when the potential is linearly increased from the first P-type region 3 (main junction) to the N-type epitaxial layer 2 or the N-type cut-off region 4 during reverse bias, the potential at the interface between the conductive layer 8 and the first oxide layer 7 is lower than the potential at the interface between the second P-type region 6 and the first oxide layer 7 because the resistance of the conductive layer 8 is higher than the resistance of the second P-type region 6, and P-type induced charges are generated at the interface between the first oxide layer 7 and the second P-type region 6, thereby increasing the surface P-type concentration of the second P-type region 6, increasing the width of the depletion layer during reverse bias, reducing the electric field intensity at the end of the first oxide layer 7, increasing the device breakdown voltage, reducing the area of the voltage dividing region, and reducing the device manufacturing cost.
Step 104-107, after removing the photoresist 5 from the structure of fig. 4, as shown in fig. 6, performing thermal oxidation on the surface thereof to form a first oxide layer 7. Then, as shown in fig. 7, a first opening and a second opening are formed by etching on the first oxide layer 7 using a photoresist as a mask. Then, a conductive layer 8 is formed on the surface of the structure shown in fig. 7, as shown in fig. 8, so that the conductive layer 8 is electrically connected to the first P-type region 3 through the first opening, and the conductive layer 8 is electrically connected to the N-type epitaxial layer 2 through the second opening. Finally, a second oxide layer 9 is formed on the surface of the conductive layer 8 by thermal oxidation, so as to obtain the device structure shown in fig. 9.
However, the conductive layer 8 may be electrically connected to the N-type cut region 4 through the second opening in addition to the structure shown in fig. 8.
Wherein the first oxide layer 7 comprises a first portion and a second portion, the second opening being arranged between the first portion and the second portion.
As shown in fig. 7, after photolithography and etching, two openings are formed on the first oxide layer 7, and the remaining first oxide layer 7 is divided into two parts to ensure that one end of the conductive layer 8 contacts the first P-type region 3 and the other end contacts the N-type epitaxial layer 2 or the N-type cut-off region 4. Specifically, the first opening is located only on the first P-type region 3, and the second opening may be located on the N-type epitaxial layer 2 or the N-type cut-off region 4.
Preferably, in order to meet the requirement of high resistance and be suitable for the super junction power device, the conductive layer 8 is high-resistance polysilicon.
In addition, the doping concentration of the N-type cut-off region 4 is greater than that of the N-type epitaxial layer 2; the doping concentration of the first P-type region 3 is greater than the doping concentration of the second P-type region 6.
In summary, in the manufacturing method of the super junction power device according to the embodiment of the present invention, the groove structure is obtained by trench etching to form the second P-type region 6, the depth requirement of the second P-type region 6 can be realized by the depth of the groove structure, and the long-time thermal annealing process in the conventional method is reduced, so that the charge balance degree of the super junction device is improved, and the device performance is improved. In addition, the first oxide layer 7 and the conducting layer 8 are added in the groove structure, so that the influence of surface charges on the performance of a junction terminal can be reduced, the width of a depletion layer in reverse bias is increased, the electric field intensity at the tail end of the first oxide layer 7 is reduced, the breakdown voltage of the device is improved, the area of a partial pressure area is reduced, and the manufacturing cost of the device is reduced.
As shown in fig. 4, a super junction power device according to an embodiment of the present invention includes: a first P-type region 3 and an N-type cut-off region 4 formed on the N-type epitaxial layer 2 of the N-type substrate 1; a P-type injection window 10 which is concave downwards is formed on the N-type epitaxial layer 2 between the first P-type region 3 and the N-type cut-off region 4; and a second P-type region 6 formed by implantation in the P-type implantation window 10; wherein the depth of the P-type implantation window 10 is greater than the depth of the first P-type region 3; the first P-type region 3 is communicated with the second P-type region 6.
Further, as shown in fig. 9, the super junction power device further includes: a first oxide layer 7 disposed on the surfaces of the first P-type region 3, the N-type epitaxial layer 2, the second P-type region 6, and the N-type cut-off region 4: a first opening and a second opening provided on the first oxide layer 7; a high-resistance conductive layer 8 provided in the first opening, the second opening, and the remaining first oxide layer 7; and a second oxide layer 9 disposed on the conductive layer 8; the conductive layer 8 is electrically connected to the first P-type region 3 through the first opening, and the conductive layer 8 is electrically connected to the N-type epitaxial layer 2 or the N-type cut-off region 4 through the second opening.
Wherein the first oxide layer 7 comprises a first portion and a second portion, the second opening being arranged between the first portion and the second portion.
The conductive layer 8 is made of high-resistance polysilicon.
The doping concentration of the N-type cut-off region 4 is greater than that of the N-type epitaxial layer 2; the doping concentration of the first P-type region 3 is greater than the doping concentration of the second P-type region 6.
According to the super junction power device provided by the embodiment of the invention, the groove structure is obtained by groove etching to realize the formation of the second P type area 6, the depth requirement of the second P type area 6 can be realized by means of the depth of the groove structure, and the long-time thermal annealing process in the traditional method is reduced, so that the charge balance degree of the super junction device is improved, and the performance of the device is improved. In addition, the first oxide layer 7 and the conducting layer 8 are added in the groove structure, so that the influence of surface charges on the performance of a junction terminal can be reduced, the width of a depletion layer in reverse bias is increased, the electric field intensity at the tail end of the first oxide layer 7 is reduced, the breakdown voltage of the device is improved, the area of a partial pressure area is reduced, and the manufacturing cost of the device is reduced.
It should be noted that the super junction power device according to the embodiment of the present invention is manufactured by applying the manufacturing method of the super junction power device, and the implementation manner of the manufacturing method of the super junction power device is applicable to the super junction power device, and the same technical effect can be achieved.
The embodiments described above are described with reference to the accompanying drawings, and many different forms and embodiments are possible without departing from the spirit and scope of the invention, therefore, the invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of elements may be exaggerated for clarity. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, and/or components. Unless otherwise indicated, a range of values, when stated, includes the upper and lower limits of the range and any subranges therebetween.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method of manufacturing a super junction power device, the method comprising:
implanting an N-type epitaxial layer generated by epitaxy on an N-type substrate to form a first P-type region and an N-type cut-off region;
forming a P-type injection window of a groove structure on the N-type epitaxial layer between the first P-type region and the N-type cut-off region, wherein the depth of the groove structure is greater than that of the first P-type region;
injecting in the P-type injection window to form a second P-type region communicated with the first P-type region;
the P-type injection window is obtained by using photoresist as a mask and performing dry etching on the N-type epitaxial layer between the first P-type region and the N-type stop region.
2. The method of manufacturing a super junction power device of claim 1, further comprising:
thermally oxidizing the surfaces of the first P-type region, the N-type epitaxial layer, the second P-type region and the N-type cut-off region to form a first oxide layer;
photoetching and etching the first oxide layer to form a first opening and a second opening;
forming a conductive layer with high resistance in the first opening, the second opening and the rest of the first oxide layer, wherein the conductive layer is electrically connected with the first P-type region through the first opening, and the conductive layer is electrically connected with the N-type epitaxial layer or the N-type cut-off region through the second opening;
and thermally oxidizing the surface of the conductive layer to form a second oxide layer.
3. The method of manufacturing a super junction power device of claim 2, wherein the first oxide layer comprises a first portion and a second portion, the second opening being disposed between the first portion and the second portion.
4. The method for manufacturing a super junction power device according to claim 2, wherein the conductive layer is high-resistance polysilicon.
5. The method for manufacturing a super junction power device according to claim 1, wherein a doping concentration of the N-type cut-off region is greater than a doping concentration of the N-type epitaxial layer; the doping concentration of the first P type area is greater than that of the second P type area.
6. A super junction power device, comprising:
a first P type region and an N type cut-off region formed on an N type epitaxial layer of an N type substrate;
a downward sunken P-type injection window is formed on the N-type epitaxial layer between the first P-type region and the N-type cut-off region; and
a second P-type region formed by implantation in the P-type implantation window; wherein the content of the first and second substances,
the depth of the P-type injection window is greater than that of the first P-type area;
the first P-type area is communicated with the second P-type area;
the P-type injection window is obtained by using photoresist as a mask and performing dry etching on the N-type epitaxial layer between the first P-type region and the N-type stop region.
7. The super junction power device of claim 6, further comprising:
the first oxide layer is arranged on the surfaces of the first P-type region, the N-type epitaxial layer, the second P-type region and the N-type cut-off region:
a first opening and a second opening disposed on the first oxide layer;
a high-resistance conductive layer disposed in the first opening, the second opening, and the remaining first oxide layer; and
a second oxide layer disposed on the conductive layer; wherein the content of the first and second substances,
the conducting layer is electrically connected with the first P-type region through the first opening, and the conducting layer is electrically connected with the N-type epitaxial layer or the N-type cut-off region through the second opening.
8. The super junction power device of claim 7, wherein the first oxide layer comprises a first portion and a second portion, the second opening being disposed between the first portion and the second portion.
9. The superjunction power device of claim 7, wherein the conductive layer is high resistance polysilicon.
10. The super junction power device of claim 6, wherein a doping concentration of the N-type cut-off region is greater than a doping concentration of the N-type epitaxial layer; the doping concentration of the first P type area is greater than that of the second P type area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610302027.5A CN107359119B (en) | 2016-05-09 | 2016-05-09 | Super junction power device and manufacturing method thereof |
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| US5956582A (en) * | 1993-05-10 | 1999-09-21 | Sgs-Thomson Microelectronics S.A. | Current limiting circuit with continuous metallization |
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