CN107346731A - A kind of method for reducing copper film thickness - Google Patents
A kind of method for reducing copper film thickness Download PDFInfo
- Publication number
- CN107346731A CN107346731A CN201610292045.XA CN201610292045A CN107346731A CN 107346731 A CN107346731 A CN 107346731A CN 201610292045 A CN201610292045 A CN 201610292045A CN 107346731 A CN107346731 A CN 107346731A
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- Prior art keywords
- copper
- film thickness
- crystal column
- electrochemical
- copper film
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02096—Cleaning only mechanical cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
- H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Abstract
The invention discloses a kind of method for reducing copper film thickness, comprise the following steps：Layers of copper is plated in crystal column surface using electrochemical plating process for copper；Crystal column surface copper film thickness is thinned using electrochemical polishing process；Wafer surface oxidation layer is removed using citric acid.The present invention removes removing oxide layer using citric acid cleaning crystal column surface, solves the problems, such as that oxide layer has an impact to the clearance and uniformity of CMP process.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of method for reducing copper film thickness.
Background technology
The integrated antenna package technology (3D IC) that three-dimensional based on silicon chip through hole (TSV) technology stacks is
Encapsulation technology newest at present, there is minimum size and quality, effectively reduce ghost effect, improve chip speed
The advantages that degree and reduction power consumption.TSV technology is by making vertical conducting between chip and chip, realizing core
The state-of-the-art technology interconnected between piece, as a kind of substitute technology of wire bonding, form the through hole knot for penetrating silicon wafer
Structure can greatly shorten the distance of interconnection, so as to eliminate the limitation of chip-stack quantitatively so that the three of chip
Dimension lamination can be applied in wider array of field.
Existing silicon hole uses metallic copper mainly to be comprised the steps of as metal level, copper metal layer front technique：
Copper seed layer vacuum plating (PVD) technique, copper film electroplating technology, annealing process, chemically mechanical polishing (CMP)
Flatening process.Because the through hole in TSV technology has larger depth-to-width ratio, typically from 5：1 to 10：1, even
20：1.Big depth-to-width ratio can be caused in copper-plating technique, and copper can not fill up in hole.By the copper plating process of optimization
Deep hole can preferably be filled up, but crystal column surface metal copper layer can be caused blocked up, usually 3 to 5 microns.
Metal internal stress increases with thickness, and the metal surface stress of TSV silicon chips can be bigger than traditional chip metal ply stress,
Silicon chip can form warpage.In annealing process, because metal level is thicker, and metal grain is grown up, gold above deep hole
Category can form projection.Wafer crushes when 2 points of the above can cause to use conventional chemical-mechanical flatening process, Yi Jiwu
Method effectively planarizes the metal bump above deep hole, therefore, reduces copper film thickness and is necessary.
What the existing method for reducing copper film thickness was realized in：After copper-plating technique, thrown using electrochemistry
Crystal column surface copper film thickness is thinned light, then carries out annealing process, finally using CMP process.
In existing process method, after electrochemical polish, copper surface can form cupric oxide caused by one layer of electrochemical oxidation
Layer, oxide layer has an impact to the clearance and uniformity of subsequent chemical mechanical flatening process, than autoxidation copper
Layer clearance is low.
The content of the invention
CMP process is gone for caused oxide layer in the technique of existing reduction copper film thickness
The problem of being had an impact except rate and uniformity, the present invention propose a kind of method for reducing copper film thickness.
What the technical solution adopted in the present invention was specifically realized in：
The invention provides a kind of method for reducing copper film thickness, comprise the following steps：
(1) layers of copper is plated in crystal column surface using electrochemical plating process for copper；
(2) crystal column surface copper film thickness is thinned using electrochemical polishing process；
(3) wafer surface oxidation layer is removed using citric acid.
Further, citric acid is the dilution citric acid of 1%-2% concentration.
It is preferred that this method further comprises：
(4) wafer is delivered to annealing process chamber and carries out annealing process；
(5) crystal column surface residual impurity is removed using CMP process
Further, reducing gas is passed through in anneal chamber.
Further, reducing gas is the mixed gas of hydrogen and nitrogen.
Further, before electrochemical polishing process after carrying out electrochemical plating process for copper, cleaning wafer surface.
Further, before electrochemical polishing process post growth annealing is carried out, cleaning wafer surface.
Further, after CMP process is carried out, cleaning wafer surface.
The present invention removes removing oxide layer using citric acid cleaning crystal column surface, and it is flat to chemical machinery to solve oxide layer
The problem of clearance and uniformity of chemical industry skill have an impact；The present invention is passed through reducing gas in annealing process chamber,
The oxide layer that crystal column surface is formed by electrochemical oxidation is removed using restoring method, makes subsequent planarization effect more
It is good.
Brief description of the drawings
Fig. 1 is a kind of flow chart of embodiment provided by the invention；
Fig. 2 is the flow chart of another embodiment provided by the invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to this
The embodiment of invention is described in detail, and makes the above and other purpose of the present invention, feature and advantage will more
It is clear to add.Not deliberately accompanying drawing drawn to scale, it is preferred that emphasis is show the purport of the present invention.
Embodiment 1
A kind of method for reducing copper film thickness, comprises the following steps：
(1) layers of copper is plated in crystal column surface using electrochemical plating process for copper；
(2) cleaning wafer surface；
(3) crystal column surface copper film thickness is thinned using electrochemical polishing process；
(4) cleaning wafer surface, the dilution citric acid of 1%-2% concentration is added in cleaning agent, to remove wafer
Surface oxide layer.
It is preferred that following steps are can further include in the above method：
(5) wafer is delivered to annealing process chamber and carries out annealing process；
(6) crystal column surface residual impurity is removed using CMP process；
(7) cleaning wafer surface.
Embodiment 2
A kind of method for reducing copper film thickness, comprises the following steps：
(1) wafer is provided, layers of copper is plated in crystal column surface using electrochemical plating process for copper；
(2) cleaning wafer surface；
(3) crystal column surface copper film thickness is thinned using electrochemical polishing process；
(4) cleaning wafer surface, the dilution citric acid of 1%-2% concentration is added in cleaning agent；
(5) wafer is delivered to annealing process chamber and carries out annealing process；
(6) reducing gas is passed through in annealing process chamber, reducing gas is the mixed gas of hydrogen and nitrogen；
(7) crystal column surface residual impurity is removed using CMP process；
(8) cleaning wafer surface.
Those skilled in the art can be obvious, can to the present invention above-mentioned example embodiment carry out it is various modification and
Modification is without departing from the spirit and scope of the present invention.Will in appended right accordingly, it is intended to fall present invention covering
Ask the modifications of the present invention in the range of book and its equivalent arrangements and modification.
Claims (8)
- A kind of 1. method for reducing copper film thickness, it is characterised in that comprise the following steps：(1) layers of copper is plated in crystal column surface using electrochemical plating process for copper；(2) crystal column surface copper film thickness is thinned using electrochemical polishing process；(3) wafer surface oxidation layer is removed using citric acid.
- 2. according to the method for claim 1, it is characterised in that citric acid is the dilution lemon of 1%-2% concentration Lemon acid.
- 3. according to the method for claim 1, it is characterised in that further wrapped afterwards in the step (3) Include：(4) wafer is delivered to annealing process chamber and carries out annealing process；(5) crystal column surface residual impurity is removed using CMP process.
- 4. according to the method for claim 3, it is characterised in that after the completion of annealing process and in chemical machine Before tool flatening process, this method further comprises：Reducing gas is passed through in anneal chamber.
- 5. according to the method for claim 4, it is characterised in that reducing gas is the mixing of hydrogen and nitrogen Gas.
- 6. according to the method for claim 1, it is characterised in that electrochemical after electrochemical plating process for copper is carried out Before optical polishing technique, cleaning wafer surface.
- 7. according to the method for claim 1, it is characterised in that carrying out electrochemical polishing process after annealing Before technique, cleaning wafer surface.
- 8. according to the method for claim 1, it is characterised in that after CMP process is carried out, Cleaning wafer surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610292045.XA CN107346731B (en) | 2016-05-05 | 2016-05-05 | Method for reducing thickness of copper film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610292045.XA CN107346731B (en) | 2016-05-05 | 2016-05-05 | Method for reducing thickness of copper film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107346731A true CN107346731A (en) | 2017-11-14 |
| CN107346731B CN107346731B (en) | 2021-03-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610292045.XA Active CN107346731B (en) | 2016-05-05 | 2016-05-05 | Method for reducing thickness of copper film |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109999839A (en) * | 2019-05-06 | 2019-07-12 | 淮北师范大学 | A kind of preparation method of inorganic non-noble metal Ni doping Cu base bifunctional electrocatalyst |
| CN113059405A (en) * | 2019-12-30 | 2021-07-02 | 盛美半导体设备(上海)股份有限公司 | Processing method and cleaning device for semiconductor structure |
| CN114156099A (en) * | 2021-12-06 | 2022-03-08 | 北京七星飞行电子有限公司 | Method for processing capacitor lead |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100000877A1 (en) * | 2004-05-25 | 2010-01-07 | Ameen Joseph G | Method for electrochemical mechanical polishing |
| CN101882595B (en) * | 2009-05-08 | 2014-07-09 | 盛美半导体设备（上海）有限公司 | Method and device for removing barrier layer |
| CN104637862A (en) * | 2013-11-14 | 2015-05-20 | 盛美半导体设备（上海）有限公司 | Method for forming semiconductor structures |
-
2016
- 2016-05-05 CN CN201610292045.XA patent/CN107346731B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100000877A1 (en) * | 2004-05-25 | 2010-01-07 | Ameen Joseph G | Method for electrochemical mechanical polishing |
| CN101882595B (en) * | 2009-05-08 | 2014-07-09 | 盛美半导体设备（上海）有限公司 | Method and device for removing barrier layer |
| CN104637862A (en) * | 2013-11-14 | 2015-05-20 | 盛美半导体设备（上海）有限公司 | Method for forming semiconductor structures |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109999839A (en) * | 2019-05-06 | 2019-07-12 | 淮北师范大学 | A kind of preparation method of inorganic non-noble metal Ni doping Cu base bifunctional electrocatalyst |
| CN109999839B (en) * | 2019-05-06 | 2021-11-16 | 淮北师范大学 | Preparation method of inorganic non-noble metal Ni-doped Cu-based bifunctional electrocatalyst |
| CN113059405A (en) * | 2019-12-30 | 2021-07-02 | 盛美半导体设备(上海)股份有限公司 | Processing method and cleaning device for semiconductor structure |
| CN114156099A (en) * | 2021-12-06 | 2022-03-08 | 北京七星飞行电子有限公司 | Method for processing capacitor lead |
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| Publication number | Publication date |
|---|---|
| CN107346731B (en) | 2021-03-16 |
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Address after: 201203 building 4, No. 1690, Cailun Road, free trade zone, Pudong New Area, Shanghai Applicant after: Shengmei semiconductor equipment (Shanghai) Co., Ltd Address before: 201203 Shanghai Zhangjiang High Tech Park of Pudong New Area Cailun Road No. fourth 1690 Applicant before: ACM (SHANGHAI) Inc. |
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