CN107342273A - A kind of wafer silicon hole fill method - Google Patents
A kind of wafer silicon hole fill method Download PDFInfo
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- CN107342273A CN107342273A CN201710495773.5A CN201710495773A CN107342273A CN 107342273 A CN107342273 A CN 107342273A CN 201710495773 A CN201710495773 A CN 201710495773A CN 107342273 A CN107342273 A CN 107342273A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
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- Manufacturing & Machinery (AREA)
- Electroplating Methods And Accessories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of wafer silicon hole fill method, comprise the following steps：First time electroplating processes are carried out to wafer silicon hole according to the first parameter, to fill the wafer silicon hole, wherein the first parameter includes at least one first current value；First time electroplating processes are carried out to wafer silicon hole according to the second parameter, supplement filling is carried out to wafer silicon hole with supplement, wherein the second parameter includes at least one second current value, and the second current value of at least a portion is more than the first current value.The present invention is final to not yet complete filling of TSV realizations to be filled up completely with, and is reduced material loss, is reduced process costs.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, and in particular to a kind of wafer silicon hole fill method.
Background technology
With the continuous progress of microelectric technique, the characteristic size of integrated circuit constantly reduces, and interconnection density improves constantly；
Requirement of the user to high-performance low power consumption simultaneously improves constantly.Silicon hole (ThroughSilicon Via, abbreviation TSV) technique with
Three-dimensional stacks the advantages that density is big, appearance and size is small, low in energy consumption after encapsulation, be widely regarded as after bonding, carrier band weldering and
Forth generation encapsulation technology after flip-chip, the mainstream technology in high-density packages field will be increasingly becoming, and TSV electro-copperings are filled out
The technology of filling is the important ring in TSV techniques.
By debugging electroplating current process menu such as table 1 during its plating is filled up completely with early stage：
Electroplating current process menu when the plating of table 1 is filled up completely with
| Current value/A | Electroplating time/min |
| 0.245 | 6 |
| 0.309 | 6 |
| 0.376 | 6 |
| 0.504 | 6 |
| 0.636 | 6 |
| 0.768 | 6 |
| 0.896 | 6 |
| 1.027 | 6 |
| 1.158 | 6 |
| 1.287 | 6 |
| 1.419 | 6 |
| 1.549 | 6 |
X-Ray detects crystal circle center, wafer centre and crystal round fringes, testing result such as Fig. 2A, Fig. 2 B, Fig. 2 C institutes respectively
Show, the TSV at the center of wafer, centre and edge completes filling, the TSV wafer after being filled to above-mentioned electro-coppering without without hole.
It is raised to measure TSV top coppers through optical profilometer, obtains testing result as shown in Fig. 3 A, Fig. 3 B, Fig. 3 C, wherein, X-axis represent along
The coordinate of a direction of TSV holes plane, Y-axis are perpendicular to the coordinate in the direction of X-axis, at crystal circle center, TSV top bumps
0.8-0.9um, wafer middle, TSV top bump 0.8-1.0um, at crystal round fringes, TSV top bumps 0.9-1.1um.By
Upper to understand, TSV is bottom-up to be filled up completely with.Meanwhile to the thick progress four-point probe measurement of copper of crystal column surface, measure
Figure is such as Fig. 4, and crystal column surface plating copper thickness average is 3.44um, uniformity 1.98%.
In TSV electro-coppering fill process steps, because the TSV electro-copperings filling of different openings rate and size needs early stage
Process debugging is carried out, just determines optimised process menu, up to before causing more excellent effect, is often produced not yet complete in debugging process
The TSV of filling；Simultaneously during TSV copper plating process runs goods automatically, due to extraneous or human factor TSV may be caused to electroplate
When only electroplated the situations of a part of Down machines, now need to handle the TSV wafer of this kind of situation.
In the prior art, processing mode is used directly to scrap processing or continuing to use not yet complete for not being filled up completely with TSV
Soak time in complement plated, increase electroplate liquid is carried out into electroplating technique menu, gives the processing of electroplate liquid acid etching copper oxide layer, then enter
Row plating, but it is ineffective.Due to the TSV for such situation, processing mode more fortunately not yet be present, often final all conducts
Piece processing is scrapped, adds process costs.
The content of the invention
The technical problem to be solved in the present invention, which is to realize not complete filling of silicon hole, to be filled up completely with.
Therefore, the embodiment of the present invention provides a kind of wafer silicon hole fill method, comprise the following steps：According to the first parameter
First time electroplating processes are carried out to wafer silicon hole, to fill the wafer silicon hole, wherein first parameter is included at least
One the first current value；First time electroplating processes are carried out to the wafer silicon hole according to the second parameter, to supplement to the crystalline substance
Circle silicon hole carries out supplement filling, wherein second parameter includes at least one second current value, and described at least a portion
Second current value is more than first current value.
Preferably, first current value and second current value are multiple, and are respectively provided with predefined procedure, and by suitable
Sequence gradually increases, wherein the minimum value in second current value is equal to the minimum value in first current value.
Preferably, the sub-minimum in second current value is equal to the maximum in first current value.
Preferably, first parameter also included for the corresponding with first current value first plating duration, described
Second parameter also included for the corresponding with second current value second plating duration.
Preferably, it is described according to the first parameter to wafer silicon hole carry out first time electroplating processes after, the basis
Before second parameter carries out first time electroplating processes to the wafer silicon hole, in addition to：Using etching solution to the wafer silicon
Through hole is handled.
Preferably, it is described to be included using aoxidizing copper etchant solution and carry out processing to the wafer silicon hole：Using hydrogen peroxide with
The mixed liquor of sulfuric acid, under desired speed is etched to the wafer silicon hole scheduled time.
Preferably, the desired speed is 30RPM, and the scheduled time is 20s.
Preferably, etched thickness scope is 10nm-100nm.
According to wafer silicon hole fill method provided by the invention, wafer silicon hole is entered first with less current value
Electroplating processes of row, now silicon hole may not be completely filled, on this basis, using larger current value to wafer
Silicon hole carries out secondary supplement electroplating processes, by not yet complete filling of wafer silicon hole realize it is final be filled up completely with, by
This can reduce material loss, reduce process costs.
Brief description of the drawings
, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical scheme of the prior art
The required accompanying drawing used is briefly described in embodiment or description of the prior art, it should be apparent that, in describing below
Accompanying drawing is some embodiments of the present invention, for those of ordinary skill in the art, before creative work is not paid
Put, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of a specific example of wafer silicon hole fill method in the embodiment of the present invention；
Fig. 2A is the result of X-Ray filling detections crystal circle center after being filled in background technology by the technological process debugged
Figure.
Fig. 2 B are the result among X-Ray filling detection wafers after being filled in background technology by the technological process debugged
Figure.
Fig. 2 C are the result of X-Ray filling detection crystal round fringes after being filled in background technology by the technological process debugged
Figure.
Fig. 3 A are that optical profilometer detects the result of crystal circle center after being filled in background technology by the technological process debugged
Figure；
Fig. 3 B are the result among optical profilometer detection wafer after being filled in background technology by the technological process debugged
Figure；
Fig. 3 C are that optical profilometer detects the result of crystal round fringes after being filled in background technology by the technological process debugged
Figure；
Fig. 4 is the four-point probe testing result figure debugged in background technology；
Fig. 5 A are that the X-Ray of abort in the embodiment of the present invention detects the result figure of crystal circle center；
Fig. 5 B are that the X-Ray of abort in the embodiment of the present invention detects the result figure among wafer；
Fig. 5 C are that the X-Ray of abort in the embodiment of the present invention detects the result figure of crystal round fringes；
Fig. 6 A are that the X-Ray in the embodiment of the present invention after complement plated detects crystal circle center's result figure；
Fig. 6 B are that the X-Ray in the embodiment of the present invention after complement plated detects wafer intermediate result figure；
Fig. 6 C are that the X-Ray in the embodiment of the present invention after complement plated detects crystal round fringes result figure；
Fig. 7 A are that the optical profilometer in the embodiment of the present invention after complement plated detects crystal circle center's result figure；
Fig. 7 B are that the optical profilometer in the embodiment of the present invention after complement plated detects wafer intermediate result figure；
Fig. 7 C are that the optical profilometer in the embodiment of the present invention after complement plated detects crystal round fringes result figure；
Fig. 8 is the four-point probe testing result figure after complement plated in the embodiment of the present invention.
Embodiment
Technical scheme is clearly and completely described below in conjunction with accompanying drawing, it is clear that described implementation
Example is part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
In the description of the invention, it is necessary to which explanation, term " first " and " second " are only used for describing purpose, and can not
It is interpreted as indicating or implying relative importance.
As long as in addition, technical characteristic involved in invention described below different embodiments non-structure each other
It is be combined with each other into conflict can.
The present embodiment provides a kind of wafer silicon hole fill method, and this method can be performed by electroplating device, such as Fig. 1 institutes
Show, comprise the following steps：
S10：First time electroplating processes are carried out to wafer silicon hole according to the first parameter, to fill wafer silicon hole, wherein
First parameter includes at least one first current value.
In silicon hole electroplates fill process step, before electroplating filling needs due to the silicon hole of different openings rate and size
Phase carries out process debugging, it is determined that the parameter of plating determines electroplating current menu, includes one or more current values.Plating filling
Metal have the metals such as copper, gold, tungsten, be typically filled using electro-coppering.
10x100um TSV are selected in the present embodiment, diameter is 10um, and depth is 100um, and its plated openings rate is about
0.19%, the TSV wafer Making programme electroplated is as described below：A wafer is provided, to its surface through SC1 solution cleaning, dryings；
Coat photoresist AZ4620, exposure, development；Etch 10x100umTSV；Remove photoresist cleaning；PECVD(Plasma Enhanced
Chemical Vapor Deposition) plasma enhanced chemical vapour deposition process make SiO2, its surface thickness is about
2um；PVD (Physical Vapor Deposition) physical vapour deposition (PVD) makes Ti/Cu (adhesion layer/Seed Layer), its surface
Thickness is about 500nm/1500nm, using electro-coppering fill process.
In the present embodiment, the process of plating is as shown in table 2, equivalent to electroplating device according to process menu as shown in table 2
First time plating is carried out, the order gone in table 2 is the order that electroplating device adopts parameter to TSV.
Table 2 electroplates electroplating current process menu when not being filled up completely with
After step S10 processing, detected to obtain the result as shown in Fig. 5 A, Fig. 5 B, Fig. 5 C as X-Ray, as illustrated,
The TSV of crystal circle center, wafer centre and crystal round fringes is not all filled up completely with, bottom-up filling extent half or so.
The reason for causing endless full packing has a variety of, such as is often produced up to before causing more excellent effect in debugging early stage
Not yet complete filling of silicon hole in debugging process；, may be due to simultaneously during silicon hole copper plating process runs goods automatically
Extraneous or human factor causes silicon hole only to electroplate the situation of a part when electroplating, and now needs the silicon hole to this kind of situation
Wafer carries out supplement filling, that is, performs step S20.
S20：First time electroplating processes are carried out to wafer silicon hole according to the second parameter, wafer silicon hole carried out with supplement
Supplement filling, wherein second parameter includes at least one second current value, and the second current value of at least a portion is more than the
One current value.Next need to carry out complement plated to above-mentioned not complete filling of silicon hole, the plating complement plated process menu of foundation, be
The process menu used during based on previously complete plating is on electroplating current compiler：Increase by a step or a few steps relatively electroplate residue
The small electric current of the current segment initial value do not electroplated, then it is combined into one plus the remaining current segment do not electroplated
Complement plated electric current formula, complement plated technique is carried out with this process menu.Complement plated process menu such as table 3：
Complement plated process menu when table 3 is not to being filled up completely with
After step S20 complement plateds, X-Ray detect as shown in Fig. 6 A, Fig. 6 B, Fig. 6 C, crystal circle center, among wafer and
The TSV of crystal round fringes has completed to be filled up completely with.Further through optical profilometer, to carrying out measuring to obtain Fig. 7 A, figure at the top of TSV
Shown in 7B, Fig. 7 C, TSV is bottom-up to be filled up completely with, and with disposable complete filling of TSV copper height of projection compared with one
Cause, at crystal circle center, TSV top bumps about 0.8-0.9um, wafer middle, TSV top bump 1.2-1.4um, crystal round fringes
Place, TSV top bumps 1.1-1.2um.Meanwhile carry out four-point probe measurement to the copper of crystal column surface is thick, measurement such as Fig. 8,
TSV wafer surface copper thickness average is 3.53um, uniformity 2.02%, itself and disposable complete filling of TSV wafer surface copper
Thick and uniformity also has preferable uniformity.
The wafer silicon hole fill method provided according to embodiments of the present invention, first with less current value to wafer silicon
Through hole carries out an electroplating processes, and now silicon hole may be completely filled, and on this basis, utilize larger current value
Secondary supplement electroplating processes are carried out to wafer silicon hole, by not yet complete filling of wafer silicon hole realization filling out completely finally
Fill, it is possible thereby to reduce material loss, reduce process costs.
Preferably, the first current value and second current value are multiple, and are respectively provided with predefined procedure, and in order by
It is cumulative big, wherein the minimum value in second current value is equal to the minimum value in first current value.
All include multiple current values in the electroplating current menu filled twice, and electric current is gradually incremented by chronological order,
Initial current value during complement plated is equal to current value when electroplating for the first time.Can be seen that from above-mentioned plating list current value be all according to
Secondary incremental, initial current is equal in initial current and table 2 in table 3.
Preferably, the sub-minimum in second current value is equal to the maximum in first current value.
As selectable embodiment, the second current value of the menu of the electric current of complement plated can be selected in abort menu
Any one current value, but in order to preferably be connected with complement plated menu, the current value in prioritizing selection during abort.
Preferably, the first parameter also included for the corresponding with the first current value first plating duration, and the second parameter is also wrapped
Include the second plating duration corresponding with second current value.
Also include electroplating time corresponding with each current value in plating menu, time value is the opening according to product TSV
Rate and depth, the current levels of each step have relation.Time in table 2 and table 3 is all the silicon hole in the present embodiment
Aperture opening ratio and size measuring draw, it is all equal not represent time value corresponding to all each step current values.
Preferably, step S11 is also included before step S20, first is carried out to wafer silicon hole according to according to the first parameter
After secondary electroplating processes, before carrying out first time electroplating processes to wafer silicon hole according to the second parameter, in addition to：Utilize etching
Liquid is handled wafer silicon hole.
Preferably, carrying out processing to the wafer silicon hole using etching solution includes：Utilize the mixing of hydrogen peroxide and sulfuric acid
Liquid, under desired speed is etched to the wafer silicon hole scheduled time.
Preferably, the desired speed is 30RPM, and the scheduled time is 20s.
Preferably, etched thickness scope is 10nm-100nm.
Complement plated technique is carried out to above-mentioned TSV, before complement plated electroplating technology, handled with oxidation copper etchant solution, scheme choosing
With hydrogen peroxide plus sulfuric acid mixture liquid to TSV wafer, 20s is etched in the case of rotating speed 30RPM, carries out microetch processing, it is contemplated that
Process costs, preferable copper etched thickness scope can be 10-100nm；After the etch is completed, complement plated technique is carried out.
Obviously, above-described embodiment is only intended to clearly illustrate example, and is not the restriction to embodiment.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of change or
Change.There is no necessity and possibility to exhaust all the enbodiments.And the obvious change thus extended out or
Among changing still in the protection domain of the invention.
Claims (8)
1. a kind of wafer silicon hole fill method, it is characterised in that comprise the following steps：
First time electroplating processes are carried out to wafer silicon hole according to the first parameter, to fill the wafer silicon hole, wherein described
First parameter includes at least one first current value；
First time electroplating processes are carried out to the wafer silicon hole according to the second parameter, the wafer silicon hole carried out with supplement
Supplement filling, wherein second parameter includes at least one second current value, and at least a portion second current value is big
In first current value.
2. wafer silicon hole fill method according to claim 1, it is characterised in that first current value and described
Two current values are multiple, and are respectively provided with predefined procedure, and gradually increase in order, wherein the minimum in second current value
Value is equal to the minimum value in first current value.
3. wafer silicon hole fill method according to claim 2, it is characterised in that secondary small in second current value
Value is equal to the maximum in first current value.
4. wafer silicon hole fill method according to claim 1, it is characterised in that first parameter also includes and institute
The first current value corresponding first plating duration is stated, second parameter also includes corresponding with second current value the
Two plating duration.
5. wafer silicon hole fill method according to claim 1, it is characterised in that it is described according to the first parameter to crystalline substance
It is described that first time plating is carried out to the wafer silicon hole according to the second parameter after circle silicon hole carries out first time electroplating processes
Before processing, in addition to：The wafer silicon hole is handled using etching solution.
6. wafer silicon hole fill method according to claim 5, it is characterised in that described to utilize etching solution to the crystalline substance
First silicon hole, which carries out processing, to be included：Using hydrogen peroxide and the mixed liquor of sulfuric acid, the wafer silicon hole is lost under desired speed
Carve the scheduled time.
7. wafer silicon hole fill method according to claim 6, it is characterised in that the desired speed is 30RPM, institute
It is 20s to state the scheduled time.
8. wafer silicon hole fill method according to claim 5, it is characterised in that etched thickness scope is 10nm-
100nm。
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| CN201710495773.5A CN107342273B (en) | 2017-06-26 | 2017-06-26 | Filling method for through silicon via of wafer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113363152A (en) * | 2020-03-06 | 2021-09-07 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364542A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Copper plating method in semiconductor device |
| CN103094187A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Forming method for silicon through hole |
| CN104465495A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming through silicon via |
-
2017
- 2017-06-26 CN CN201710495773.5A patent/CN107342273B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364542A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Copper plating method in semiconductor device |
| CN103094187A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Forming method for silicon through hole |
| CN104465495A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming through silicon via |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113363152A (en) * | 2020-03-06 | 2021-09-07 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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