CN107330177B - Clock tree fan-out default repairing method based on Tcl/Tk script - Google Patents
Clock tree fan-out default repairing method based on Tcl/Tk script Download PDFInfo
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Abstract
The invention discloses a clock tree fan-out default repairing method based on a Tcl/Tk script, which comprises the following steps: 1) inputting the full name of a pin of the fan-out default, the name of an insertion buffer and whether to execute the method for the first time; 2) traversing all fan-out units connected with the fan-out default pin pins, and averagely dividing all the units into two groups; 3) disconnecting the time sequence ports of all fan-out units from fan-out default pin pins; 4) grabbing the names of the corresponding levels of the fan-out units, and creating new buffers and connecting lines which need to be added under the corresponding levels; 5) and according to the principle of not changing the logic relation of the circuit, two groups of fan-out units are respectively connected with the outputs of the two buffers, and the inputs of the two buffers are respectively connected with the default pin pins. The method can quickly repair the fan-out default of the clock tree, accelerate the time of logic constraint convergence, reduce manual operation and improve the reliability and efficiency of digital physical design.
Description
Technical Field
The invention belongs to the technical field of digital physical design in a semiconductor integrated circuit, and particularly relates to a method for quickly repairing fanout default of logic and physical constraints of a clock tree in SoC (System on Chip) physical design with high working frequency and high speed.
Background
Clock tree synthesis is the core of digital physical design, clock signals transmitted by the clock tree drive the work of the whole system, and logical constraint violations on the clock tree must be cleaned up. When performing clock tree synthesis, first logic constraints such as fan-out, conversion time, and load capacitance need to be set. The fan-out convergence is an important target of logic convergence, and the overlarge fan-out can cause that a former-stage register is difficult to drive a latter-stage register, so that the time sequence of the stage cannot be accurately obtained through a process library, the precision of the setup time and the hold time is influenced, and a circuit cannot accurately work according to the clock beat. Existing digital physical design software such as icc (ic compiler) can solve most of the fan-out problem, but because there are many factors to be considered when the physical design software performs layout and routing, such as blocking position, standard cell congestion degree, timing problem, etc., there are some fan-out violations that are difficult to repair more or less.
One of the common solutions at this time is manual repair, but if the number of defaults is too large, the efficiency of manual repair is too low, and errors are easy to occur; another method is to use an ECO (Engineering Change Order) tool, but the ECO tool is expensive, for example, an ECO tool of a certain domestic company has at least 20 to 30 ten thousand renminbi, a user operation interface is not very friendly, and it takes a long time to initialize the ECO tool, and a script derived by the ECO tool must be executed by digital physical software.
In 3 months 2012, the Homing network discloses a thesis named 'research and implementation of design of rear end of 32-bit CPU dual-interface card chip based on SOC Encounter', and a 'in-situ optimization' method is proposed on page 57 in the text to solve fan-out default.
In 2006, 5, the knowlege network discloses a paper named "digital television set-top box chip digital back-end design", and in page 24 in the paper, a maximum fan-out integration method is provided, which integrates high fan-out of the whole design by using digital back-end design software astro, but different from the design, a specific fan-out default pin can be repaired.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a clock tree fan-out default repairing method based on a Tcl/Tk script, which can rapidly repair the clock tree fan-out default and can expand the application to repair the fan-out default at any stage of a digital physical design.
In order to solve the technical problem, the invention provides a clock tree fan-out default repairing method based on a Tcl/Tk script, which is characterized by comprising the following steps:
1) inputting the full name of a fan-out default pin, the name of an insertion buffer and whether to execute the method for the first time;
2) traversing all fan-out units connected with the fan-out default pins, and averagely dividing all the units into two groups;
3) disconnecting the time sequence ports of all the fan-out units from the fan-out default pins;
4) grabbing the names of the corresponding levels of the fan-out units, and creating new buffers and connecting lines which need to be added under the corresponding levels;
5) and according to the principle of not changing the logic relation of the circuit, two groups of fan-out units are respectively connected with the outputs of the two buffers, and the inputs of the two buffers are respectively connected with default pins.
In step 2), if the pin with fan-out default is the unit at the top layer, traversing all fan-out units through the logic port of the fan-out unit; and if the pins of the multi-level unit are the pins, all fan-out units are directly traversed according to the actual connection condition.
And 4), capturing the names of the corresponding levels of the fan-out units by using a regular expression.
In the step 4), the method specifically comprises the following steps:
generating a global control variable according to the input parameters whether to execute the method for the first time;
two new buffers and two new wires are created using global variables.
In the step 5), two new connecting lines are created by using the global variables, and the two groups of fan-out units are respectively connected; two new buffers are created using global variables, each connected to a newly created link.
Writing a fan-out repair software program for the steps, writing a logic processing part of software by adopting Tcl, and writing a software graphical interface by using Tk.
The invention achieves the following beneficial effects:
the invention uses Tcl/Tk language to write and repair the fanned ECO tool, mainly uses Tcl to finish the processing of the logic part, and uses Tk (graphical interface tool set of Tcl language) to finish the realization of the user interface of the tool. The tool can be integrated in a menu bar of an ICC (Integrated Circuit control) and a unit added on a layout of the tool can be directly seen on an ICC layout interface, interactive operation between different software is completely removed, the tool directly utilizes initial setting of the ICC, so that time is not spent on initial setting again, fan-out default can be quickly, effectively and accurately repaired, time of logic constraint convergence is accelerated, manual operation is reduced, and reliability and efficiency of digital physical design are improved.
Drawings
FIG. 1 is a flow chart of an implementation of the method of the present invention;
FIG. 2 fan-out repair software menu;
FIG. 3 is a fan-out repair software graphical interface;
FIG. 4 fanout reports before and after repair;
FIG. 5 layout comparison before and after fan-out software repair.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
The invention uses Tcl script to compile the function of logic processing part, uses Tk to compile graphical operation interface, and uses the interface provided by digital physical design software to integrate the compiling software into menu bar. The specific implementation of the program is shown in the flowchart of fig. 1. First, three parameters, such as the full name of the fan-out default pin and the name of the insertion buffer, whether to execute the method program for the first time, must be input, and these three parameters are used when solving the fan-out problem. It is then necessary to traverse all cells connected by the fan-out default pin and divide all cells into two groups on average. If a fan-out default pin is a unit at the top layer, all fan-out units need to be traversed through a logic port of the fan-out default pin; if the pins of the unit in multiple layers are provided, all fan-out units are directly traversed according to the actual connection condition. And then disconnecting the time sequence ports of all the fan-out units from the fan-out default pins, capturing the names of the corresponding levels of the fan-out units by using regular expressions, and creating buffers and connecting lines which need to be added under the corresponding levels. And finally, according to the principle that the logic relation of the circuit is not changed, the two groups of fan-out units are respectively connected with the outputs of the two buffers, and the inputs of the two buffers are respectively connected with default pins.
By using the method, only three parameters such as fan-out default pins, names of buffers and whether software of the method is executed for the first time need to be input, and after the software obtains the information, coordinate information of units connected with all the fan-out default pins and the default pin units can be automatically extracted, connecting lines and buffers needing to be added are automatically created, and the connecting lines are connected according to corresponding logical relations. The design method solves the problem of fan-out of corresponding pins only by inputting three parameters, greatly reduces manual operation and improves reliability. Originally, manual operation needs at least 10 minutes to repair a fan-out default of one pin, and by using the method, software is filled in three parameters, so that the problem of fan-out default repair by the software is less than 1 minute, and the efficiency is greatly improved. The input code of the software of the method is slightly changed, batch modification of fan-out default pins can be realized, and the expandability is strong.
1. Writing fan-out repair software according to an algorithm flow, wherein a logic processing part of Tcl writing software is mainly used, and a graphical interface is realized by using Tk.
2. The ICC is then started under the linux system (an open source operating system), and the source program file is read in the dialog box of the ICC, so that the software can be integrated in the menu bar of the ICC. As shown in fig. 2, the specific position is under the menu TclProgram.
3. Two options are seen under a Tcl Program menu, the first is a multilevel unit (hierarchy) fan-out default repair use, the second is a top level unit (top) fan-out default repair use, a detailed interface is shown in FIG. 3, a pin name of the fan-out default is input in a first input field, and the multilevel unit and the top level unit need to be distinguished correctly. The second dialog box enters the selected buffer name, typically selecting a buffer with moderate drive capability, which in fig. 3 is the CLKBUX8 buffer in the slow bank. The parameter entered in the third dialog box indicates whether the program is executed for the first time, if the program is executed for the first time, 1 is filled, and this variable controls the naming rule of the globally created net and buffer, otherwise 0 must be written. After the setting is completed and the button Fix is clicked, the Fix button is bound with a repair fanout software starting command based on the Tk, so that the software can automatically repair the fanout default problem. The fan-out of the pin u _ sync _ top/u _ jlxz _ s3/CTS _ CLK _50M _ CTO _ delay461/Y is repaired as an example.
It can be seen from the pre-repair report of FIG. 4 that the actual fan-out for this pin is 16, the fan-out constraint is 12, and thus the penalty number for this pin is 4, for a total of 6 fan-out violations on the pre-repair clock tree CLK _ 50M. It can be seen from the report after repair that there has been no previous pin violation in the report, and the number of fan-out violations for the clock tree CLK _50M has also been reduced from the previous 6 to 5. It can be seen from the report that the fan-out penalty of u _ sync _ top/u _ jlxz _ s3/CTS _ CLK _50M _ CTO _ delay461/Y pin has been successfully repaired.
It can be seen from fig. 5 that before repair, there are no other units around the fan-out default pin on the layout, in order to repair the fan-out default of the pin, two buffers are added to its accessories, the connection line of the fan-out default pin is broken, two suitable buffers are inserted, the two buffers are connected with the fan-out default pin, the previous single path is divided into two paths, the fan-out of the pin u _ sync _ top/u _ jlxz _ s3/CTS _ CLK _50M _ CTO _ delay461/Y is changed from the original 16 to 2, and the two buffers drive 8 standard units respectively, thus solving the problem of fan-out default of the pin.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (4)
1. A clock tree fan-out default repairing method based on a Tcl/Tk script is characterized by comprising the following steps:
1) inputting the full name of a fan-out default pin, the name of an insertion buffer and whether to execute the method for the first time;
2) traversing all fan-out units connected with the fan-out default pin pins, and averagely dividing all the units into two groups;
3) disconnecting the time sequence ports of all the fan-out units from the fan-out default pins;
4) grabbing the names of the corresponding levels of the fan-out units, and creating new buffers and connecting lines which need to be added under the corresponding levels;
5) according to the principle of not changing the logic relation of a circuit, two groups of fan-out units are respectively connected with the outputs of the two buffers, and the inputs of the two buffers are respectively connected with default pins;
in the step 4), the method specifically comprises the following steps:
generating a global control variable according to the input parameters whether to execute the method for the first time;
creating two new buffers and two new wires using global variables;
in the step 5), two new connecting lines are created by using the global variables, and the two groups of fan-out units are respectively connected; two new buffers are created using global variables, each connected to a newly created link.
2. The method for repairing the fan-out default of the clock tree based on the Tcl/Tk script as claimed in claim 1, wherein in step 2), if the pin with the fan-out default is the top unit, all fan-out units are traversed through the logic port thereof; and if the pins of the multi-level unit are the pins, all fan-out units are directly traversed according to the actual connection condition.
3. The method for repairing the fan-out default of the clock tree based on the Tcl/Tk script as claimed in claim 1, wherein in the step 4), a regular expression is used to capture the name of the corresponding level of the fan-out unit.
4. The method for repairing clock tree fan-out default based on Tcl/Tk script as claimed in claim 1, wherein for the above steps writing a fan-out repair software program, adopting the logic processing part of Tcl writing software, using Tk to write software graphical interface.
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| CN102436525A (en) * | 2011-10-27 | 2012-05-02 | 西安华芯半导体有限公司 | Method for automatically repairing hold time violation in multi-node parallel mode in integrated circuit designing process |
| CN103632001A (en) * | 2013-11-27 | 2014-03-12 | 中国人民解放军国防科学技术大学 | Retention time sequence optimization method based on multiplexing of buffer unit |
| CN104268352A (en) * | 2014-10-09 | 2015-01-07 | 中国电子科技集团公司第五十四研究所 | Quick fix method for clock skews in FPGA (field programmable gate array) realization |
| CN105302947A (en) * | 2015-10-16 | 2016-02-03 | 中国人民解放军国防科学技术大学 | Fan circle multi-fan-out path-based repeater insertion method |
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Patent Citations (4)
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| CN102436525A (en) * | 2011-10-27 | 2012-05-02 | 西安华芯半导体有限公司 | Method for automatically repairing hold time violation in multi-node parallel mode in integrated circuit designing process |
| CN103632001A (en) * | 2013-11-27 | 2014-03-12 | 中国人民解放军国防科学技术大学 | Retention time sequence optimization method based on multiplexing of buffer unit |
| CN104268352A (en) * | 2014-10-09 | 2015-01-07 | 中国电子科技集团公司第五十四研究所 | Quick fix method for clock skews in FPGA (field programmable gate array) realization |
| CN105302947A (en) * | 2015-10-16 | 2016-02-03 | 中国人民解放军国防科学技术大学 | Fan circle multi-fan-out path-based repeater insertion method |
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