CN107317734A - Integrated CN bus nodes chip structure based on SOC technologies - Google Patents

Abstract

The present invention relates to CAN integrated circuit, to propose integrated CN bus nodes chip structure, simplify the design of node of CAN communication system, reduce the design and debugging difficulty of CAN Communication System Design personnel, improve the Stability and dependability of system.For this, the technical solution adopted by the present invention is, integrated CN bus nodes chip based on SOC technologies, it is made up of master controller, CAN protocol controller unit, transmission circuit unit, master controller is used to realize the register configuration to CAN protocol controller and completes the reading and write-in of data；CAN protocol controller unit is used to realize CAN data link layer content, including data framing, error detection and acceptance filtenng；CAN transmission circuit units realize CAN physical layer content, complete the conversion of physical bus level and logic level.Manufacture and design occasion present invention is mainly applied to CAN equipment.

Description

Integrated CN bus nodes chip structure based on SOC technologies

Technical field

The present invention relates to CAN integrated circuit, specifically, it is related to the integrated CN bus nodes chip based on SOC technologies Structure.

Background technology

Wireless senser has the advantage that cable technology can not replace, because the features such as its is with low cost, flexibility is high progressively The links of Industry Control are penetrated into, the reliable data transmission of sensor and upper control machine can be realized with reference to fieldbus. For example, in the application of automobile direct-type pressure tire monitor system, need to be taken turns using the wireless pressure sensor of inside tires Barometric information in tire, and by CAN (Controller Area Network) bus transfer to upper control machine to sentence Whether disconnected tire pressure is abnormal, is controlled by keeping air pressure in tire normal afterwards.SOC (System on Chip) is to be on piece System, microprocessor, Analog IP core, digital IP kernel and memory (or control interface is stored outside piece) are integrated on one chip, It is typically customization, or towards the standardized product of special-purpose.SOC is the inexorable trend of integrated circuit development, is The certainty of technology development, is also the development of IC industry futures.

CAN controller LAN is the serial fieldbus communication protocol of ISO International standardizations, with its high reliability, The features such as high transfer rate, high real-time, it is widely used in the neck such as automotive electronics, Industry Control, aviation electronics and medicine equipment Domain.In traditional distributed wireless senser CAN data communication system, communication node mainly includes wireless senser, master Controller, CAN controller and CAN transceiver, Fig. 1 show for the implementation of conventional wireless sensor CAN network and node It is intended to.Master controller, CAN controller and transceiver need to use discrete chip in traditional communication system, node it is integrated Degree is relatively low, and CAN Communication System Design personnel need to debug master controller, CAN controller and transceiver respectively, increases The design and debugging difficulty of system designer are added.To solve problem above, herein based on SOC design technology and according to CAN Bus standard agreement CAN2.0B, devises a integrated master controller, CAN total using composite signal integrated circuits designing technique The high-speed communication chip of lane controller and transceiver, simplifies the design of node of CAN communication system, improves the stabilization of system Property and reliability.

Bibliography：

[1] power consumption wireless sensor network research of the Yin Guang floods based on CAN is with realizing [D] Changsha：National defence section Skill university, 2009.

[2] CAN Communication System Design [J] the computers of Li Xiao, Li Rui, Wang Zhibin, Han Feng based on DSP and FPGA Measurement and control, 2015,23 (1)：284-286.

[3] Chun Hua, Zeng Ming Pan, Si Yang Wang.CAN Bus Communication System Based On SOC Technology[C].International Conference on Intelligent Computing And Integrated Systems (ICISS), 2010：322–325.

The content of the invention

To overcome the deficiencies in the prior art, the present invention is directed to propose integrated CN bus nodes chip structure, simplifies CAN The design of node of communication system, reduces the design and debugging difficulty of CAN Communication System Design personnel, improves the stabilization of system Property and reliability.Therefore, the technical solution adopted by the present invention is, the integrated CN bus nodes chip based on SOC technologies, by master control Device processed, CAN protocol controller unit, transmission circuit unit are constituted, and master controller is used to realize to CAN protocol integrated test system The register configuration of device and the reading and write-in for completing data；CAN protocol controller unit is used to realize CAN number According to link layer content, including data framing, error detection and acceptance filtenng；CAN transmission circuit units realize CAN physical layer Content, completes the conversion of physical bus level and logic level.

Master controller is single-chip microcomputer ip cores, including CPU, memory, controller and I/O mouthful, wherein CPU are processing datas A width of 8bit central processor unit, one 8bit of single treatment binary number, and data be according to byte be unit And handled, single-chip microcomputer ip cores are by the way that I/O causes for gossip are existing and connection of CAN controller.

CAN protocol controller unit, is specifically made up of submodule REGISTERS, BTL, BSP, while completing and three State interface, tri-state PAD relevant interface logic conversion；Wherein, REGISTERS：The partial function of interface management logic is realized, is solved The order from CPU is released, the addressing of CAN registers is controlled, the read-write of internal register is realized, and interruption is provided to master controller Information and status information；BTL：Bit timing logic function is realized, on bus transfer data and CAN at the start of message (SOM) Bit data stream is synchronized, during receiving message after, timing skew is carried out subsynchronous again；BSP：Realize at bit stream The function of device and mistake manages logic, including submodule ACF, FIFO are managed, the error detection of CAN module is performed, arbitrates, fills out Fill and troubleshooting；ACF：For realizing acceptance fitration function, by being carried out to the control domain that message frame is received in bus Acceptance filtenng and examination are shielded, and determine if that buffer can be received by filtering to enter；FIFO：BSP submodules, for depositing The information for receiving and being identified from CAN is stored up, and the message number received is counted, while being overflow in data Spill over is produced when going out.

Transmitting element structure is specifically in transmission circuit, and two series resistor R1 and R2 obtain being used to provide total by partial pressure The recessive biasing of line, P0 and N0 transistors are used for generation and meet difference fiduciary level as defined in CAN, P0 and N0 transistors it Between the resistance R3 and R4 that concatenate be used to isolate dominant level and recessive level.

Receiving unit is made up of comparator in transmission circuit, specifically, N1 and N2 pipes composition level reduction circuit, using source Design is followed to reduce CANH level, P3, P4, P5, P6, N7, N8 transistor are the core circuit unit of comparator, N7, N8 pipe It is differential pair input stage, P3, P6 pipe are active load of the short circuit into diode, and P1, P2, N5, N6 pipe realize output from difference Single-ended conversion is assigned to, N3 constitutes image current mirror with N4 pipes, for carrying out direct current biasing to difference amplifier；Comparator has altogether There are two feedback networks, first is series current feedback by transistor N7 and N8 common source node, shows as negative-feedback；The Two be P4 and P5 pipes source-drain electrode shunt voltage feedback, this feedback network is positive feedback, when positive and negative feedforward coefficient be less than it is negative anti- During the coefficient of feedback, whole comparator circuit will appear as negative-feedback, while circuit will lose hysteresis effect, when the positive feedback of circuit When coefficient is more than degeneration factor, whole comparator circuit will show as positive feedback, while comparator circuit will appear from sluggishness Effect.

The features of the present invention and beneficial effect are：

According to CAN standard agreement with electrically providing and being communicated with reference to a high-speed CAN bus node of SOC design technology Chip, the integrated chip master controller, CAN protocol controller and transceiver realize node Miniaturization Design, can be quickly and easily Apply in high-speed wireless sensing device CAN communication system, improve the Stability and dependability of system.

Brief description of the drawings：

Fig. 1 conventional wireless sensor CAN network node structures.

Fig. 2 chip overall structure block diagrams.

Fig. 3 MCS51 single-chip microcomputer IP kernel block diagrams.

Fig. 4 protocol control units block diagrams.

Fig. 5 transmission circuit cellular construction figures.

Fig. 6 receives hysteresis comparator circuit design.

Embodiment

CAN node integrated chip includes master controller, CAN controller and transceiver, respectively to realize CAN The bus regulation of data link layer and physical layer.Functional module division, overall structure are carried out to chip according to standard agreement content Block diagram is as shown in Figure 2.

Wherein master controller uses MCS51 single-chip microcomputer IP kernels, and the register of CAN protocol controller is matched somebody with somebody for realizing Put and complete the reading and write-in of data.CAN protocol controller unit realizes CAN data link layer content, main To include data framing, error detection and acceptance filtenng etc..Interface management logic, bit stream processing are divided into according to its functional characteristics Device, acceptance fitration, bit timing logic, information buffer and mistake manages logic.Interface management logic is used to perform micro-control The order of device processed, the inside addressing of management bus control unit unit；Bit stream processor is used for control data buffer and CAN Between data flow perform the function such as error detection simultaneously；Acceptance fitration is used to recognize the frame identifier in CAN network； Bit timing logic is responsible for handling the bit timing related to bus；Information buffer is used for the information for storing transmitting-receiving, is divided into Transmission buffer and reception buffer；Mistake manages logic is used in wrong control, including false judgment and error handle etc. Hold.

CAN transmission circuit units realize CAN physical layer content, complete physical bus level and turn of logic level Change.Physical bus level is differential level form, and CANH is high level end, and CANL is low level end.TX ports will be through agreement control The data that device cell processing processed is crossed are sent to transmission circuit unit, are sent to afterwards by transmission circuit unit on physical bus；Receive The differential level received from physical bus is processed as data signal by Power Generation Road, and protocol controller list is transferred to by RX ends Member.

The framework of MCS51 single-chip microcomputer IP kernels is as shown in figure 3, mainly include CPU, memory, controller and I/O mouthful.Wherein CPU is the central processor unit that processing data bit wide is 8bit, can once handle 8bit binary number, and number Handled according to according to byte for unit, the CPU inside 8051 single-chip microcomputers is by arithmetic operator unit ALU, periphery Timer conter and the control register of inside, 3 bulk logic circuits composition；Controller controls the fortune of whole single-chip microcomputer OK, he is specifically made up of control logic, IR command registers, program counter and some other combinational logic circuits；MCS51 The memory of series is divided into device ROM and RAM, storage program and data is respectively used to, by the way of being separately addressed；51 series Single-chip microcomputer has 4 groups of I/O ports, and every group of port is all 8bit data bit width, and 51 series monolithics are to belong to bus type structure Type, it be able to can be connected by address/data bus with RAM, ROM memory or Parallel I/O Interface chip, I/O causes for gossip show With the connection of CAN controller.

According to the framework of CAN integrated chip and functional requirement, systems organization and function are carried out to digital circuit blocks Analysis, the protocol control units frame of final design is as shown in Figure 4.

TOP：Digital circuit top-level module, including submodule REGISTERS, BTL, BSP, at the same complete with tri-state interface, Interface logic conversion relevant tri-state PAD；REGISTERS：The partial function of interface management logic is realized, is explained from CPU's Order, controls the addressing of CAN registers, realizes the read-write of internal register, and provide interrupting information and state to master controller Information；BTL：Bit timing logic function is realized, bus transfer data is entered with the bit data stream in CAN at the start of message (SOM) Row is synchronous, during receiving message after, timing skew is carried out subsynchronous again；BSP：Realize bit stream processor and mistake Manage the function of logic, including submodule ACF, FIFO.Perform at error detection, arbitration, filling and the failure of CAN module Reason；ACF：BSP submodules, for realizing acceptance fitration function, by being carried out to the control domain that message frame is received in bus Acceptance filtenng and examination are shielded, and determine if that buffer can be received by filtering to enter；FIFO：BSP submodules, for depositing The information for receiving and being identified from CAN is stored up, and the message number received is counted, while being overflow in data Spill over is produced when going out.

Transmission circuit unit is level shifter interface, is provided according to CAN level, CANH and CANL level is respectively Low level " 0 " (dominance condition) is represented during 3.5V and 1.5V, CANH and CANL level represents that high level " 1 " is (hidden when being 2.5V Character state).Transmission circuit unit mainly includes two parts, is transtation mission circuit module and receiving circuit module, transmitting-receiving respectively Circuit unit structure is as shown in figure 5, resistance R5 is physical bus equivalent load resistance in figure, and R1 and R2 obtain 2.5V by partial pressure Voltage is used for the recessive biasing for providing bus, and R3 and R4 are used to isolate dominant level and recessive level, and two diodes play protection Effect prevents in bus that level is too high or too low and power supply impacted, and P0 is used to generation with N0 transistors and meets CAN advising Fixed fiduciary level.Electrically provided according to CAN, bus equivalent resistance representative value under standard application environment is 60 Ω, institute To ensure that transtation mission circuit has enough driving forces in actual design process, the setting of transtation mission circuit driving current need to leave one Fixed nargin, therefore carry out circuit design when being finally 50 Ω for bus load R5.When P0 is simultaneously turned on N0 transistors CANH and CANL level is respectively 3.5V, 1.5V, now needs to provide 40mA driving currents to bus, driving current is larger, is The size for meeting driving demand P0, the N0 switching transistor of bus is larger to provide enough output currents, and large scale switch is brilliant Body pipe prime is driven by the way of phase inverter cascade reaches faster switching speed.

Receiving circuit is a voltage hysteresis comparator, and patrolling for receiving terminal RX is changed by comparing the differential voltage in bus The state of collecting.Electrically provided according to CAN, it is " 0 " that the voltage difference between CANH and CANL, which is more than 0.9V interval scale bus logics state,； It is " 1 ", therefore the hysteresis voltage of comparator when the voltage difference between CANH and CANL is less than 0.5V interval scale bus logics state For 400mV.Occur when the positive-negative input end level difference value of usual hysteresis comparator is more than positive threshold value or less than negative threshold voltage State is overturn, i.e., transmission characteristic center level point is 0V, does not meet CAN logic state upset feature, therefore circuit design CANH level is first reduced into 0.7V, level signal and CANL after reduction are entered as the positive-negative input end of comparator core circuit Row compares, it is ensured that input and output feature is consistent with CAN level regulation, and comparator circuit design is as shown in Figure 6.N1 in figure With N2 pipes composition level reduction circuit, follow design that CANH level is reduced into 0.7V, P3, P4, P5, P6, N7, N8 crystal using source Pipe is the core circuit unit of comparator, and N7, N8 pipe are differential pair input stages, and P3, P6 pipe are short circuit having into diode Source is loaded, and P1, P2, N5, N6 pipe realize output from differential-to-single-ended conversion, and N3 constitutes image current mirror with N4 pipes, for pair Difference amplifier carries out direct current biasing.One has two feedback networks in this circuit, and first is common by transistor N7 and N8 The series current feedback of source node, shows as negative-feedback；Article 2 is the source-drain electrode shunt voltage feedback of P4 and P5 pipes, and this is anti- Feedthrough road is positive feedback.When positive and negative feedforward coefficient is less than the coefficient of negative-feedback, whole circuit will appear as negative-feedback, while circuit Hysteresis effect will be lost, when the positive and negative feedforward coefficient of circuit is more than degeneration factor, whole circuit will show as positive feedback, together When circuit will appear from hysteresis effect.

CAN node chip is mainly used in wireless senser and Industry Control neighborhood, it is convenient to sets up CAN and leads to Letter system can replace the communication node in traditional CAN bus system simultaneously, need to only be connected at CANH the and CANL ends of chip always Just can proper communication on the difference cable of linear system system.

Claims (5)

1. a kind of integrated CN bus nodes chip based on SOC technologies, it is characterized in that, by master controller, CAN protocol integrated test system Device unit, transmission circuit unit are constituted, and master controller is used to realizing to the register configuration of CAN protocol controller and complete Into the reading and write-in of data；CAN protocol controller unit is used to realize CAN data link layer content, including number According to framing, error detection and acceptance filtenng；CAN transmission circuit units realize CAN physical layer content, complete physical bus electricity The flat conversion with logic level.

2. the integrated CN bus nodes chip as claimed in claim 1 based on SOC technologies, it is characterized in that, master controller is single Piece machine ip cores, including CPU, memory, controller and I/O mouthful, wherein CPU are the central processing units that processing data bit wide is 8bit Unit, one 8bit of single treatment binary number, and data are handled according to byte for unit, single-chip microcomputer ip Core is by the way that I/O causes for gossip are existing and connection of CAN controller.

3. the integrated CN bus nodes chip as claimed in claim 1 based on SOC technologies, it is characterized in that, CAN agreement control Device unit processed, is specifically made up of submodule REGISTERS, BTL, BSP, while completing and tri-state interface, tri-state PAD is relevant connects Mouth logical transition；Wherein, REGISTERS：The partial function of interface management logic is realized, the order from CPU, control is explained The addressing of CAN registers, realizes the read-write of internal register, and provide interrupting information and status information to master controller；BTL： Bit timing logic function is realized, bus transfer data is synchronized with the bit data stream in CAN at the start of message (SOM), During receiving message afterwards, timing skew is carried out subsynchronous again；BSP：Realize bit stream processor and mistake manages logic Function, including submodule ACF, FIFO perform the error detection of CAN module, arbitration, filled and troubleshooting；ACF： For realizing acceptance fitration function, pass through filtering and the examination screen of being carried out an acceptance inspection to the control domain that message frame is received in bus Cover, determine if that buffer can be received by filtering to enter；FIFO：BSP submodules, connect for storing from CAN The information for receiving and being identified, and the message number received is counted, overflow letter while being produced when data are overflowed Number.

4. the integrated CN bus nodes chip as claimed in claim 1 based on SOC technologies, it is characterized in that, sent out in transmission circuit It is specifically that two series resistor R1 and R2 obtain biasing for providing the recessive of bus by partial pressure, P0 and N0 to send cellular construction Transistor meets difference fiduciary level as defined in CAN for generation, the resistance R3 and R4 concatenated between P0 and N0 transistors For isolating dominant level and recessive level.

5. the integrated CN bus nodes chip as claimed in claim 1 based on SOC technologies, it is characterized in that, connect in transmission circuit Receive unit to be made up of, specifically, N1 and N2 pipes composition level reduction circuit comparator, follow design to drop CANH level using source Low, P3, P4, P5, P6, N7, N8 transistor are the core circuit units of comparator, and N7, N8 pipe are differential pair input stage, P3, P6 The active load into diode for short circuit is managed, P1, P2, N5, N6 pipe realize output from differential-to-single-ended conversion, N3 and N4 Pipe constitutes image current mirror, for carrying out direct current biasing to difference amplifier；Comparator one has two feedback networks, first It is the series current feedback by transistor N7 and N8 common source node, shows as negative-feedback；Article 2 is the source and drain of P4 and P5 pipes Pole shunt voltage feedback, this feedback network is positive feedback, when positive and negative feedforward coefficient is less than the coefficient of negative-feedback, whole comparator Circuit will appear as negative-feedback, while circuit will lose hysteresis effect, when the positive and negative feedforward coefficient of circuit is more than degeneration factor, Whole comparator circuit will show as positive feedback, while comparator circuit will appear from hysteresis effect.