CN107316907A - Coplanar type thin film transistor (TFT) and its manufacture method - Google Patents
Coplanar type thin film transistor (TFT) and its manufacture method Download PDFInfo
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- CN107316907A CN107316907A CN201710491023.0A CN201710491023A CN107316907A CN 107316907 A CN107316907 A CN 107316907A CN 201710491023 A CN201710491023 A CN 201710491023A CN 107316907 A CN107316907 A CN 107316907A
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- 239000010409 thin film Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010936 titanium Substances 0.000 claims abstract description 90
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 90
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 88
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 83
- 229910052802 copper Inorganic materials 0.000 claims abstract description 74
- 239000010949 copper Substances 0.000 claims abstract description 74
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 230000004888 barrier function Effects 0.000 claims abstract description 34
- 239000012212 insulator Substances 0.000 claims abstract description 24
- 239000010408 film Substances 0.000 claims description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 229910004205 SiNX Inorganic materials 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract 2
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- -1 metal Mo Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000004078 waterproofing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of coplanar type thin film transistor (TFT), including：It is overlying on the grid on substrate；It is overlying on the gate insulator on grid；The source electrode being overlying on gate insulator and drain electrode, the channel region between source electrode and drain electrode, source electrode and drain electrode are double-layer structure, and bottom is layers of copper, and top layer is titanium layer, and titanium layer is located in layers of copper and part is located at channel region side；Semiconductor layer is provided with channel region, titanium layer is contacted with semiconductor layer, titanium layer includes titanium barrier layer, titanium barrier layer isolation layers of copper and semiconductor layer.The present invention solves the problem of layers of copper is contacted with semiconductor layer at channel region, it is to avoid copper atom spreads to semiconductor layer, so as to play the purpose of isolation copper and semiconductor layer.
Description
Technical field
The invention belongs to thin-film transistor technologies field, more particularly to a kind of coplanar type thin film transistor (TFT) and its manufacturer
Method, array base palte, liquid crystal panel, display device.
Background technology
In panel display apparatus, Thin Film Transistor-LCD (Thin Film Transistor Liquid
Crystal Display, abbreviation TFT-LCD) there is small volume, relatively low low in energy consumption, manufacturing cost and the features such as Low emissivity.
In coplanar type thin-film transistor structure, as shown in figure 1, coplanar type thin film transistor (TFT) 10, including it is overlying on substrate 01
On grid 02, the gate insulator 03 being overlying on grid 02, the source electrode that is overlying on gate insulator 03 and drain electrode, wherein, source
Pole and drain electrode are double-layer structure, bottom layers of copper 041, top layer is titanium layer 042, be overlying on source electrode and drain electrode on semiconductor layer 05,
Wherein, semiconductor layer 05 is IGZO semiconductor layers, the insulating barrier 06 being overlying on semiconductor layer 05.Wherein, channel region 07 is located at source
Between pole and drain electrode.At channel region 07, because layers of copper, titanium layer are etched simultaneously, the side at channel region, source electrode and drain electrode meeting
Come in contact with semiconductor layer, i.e. layers of copper 041 is directly contacted with semiconductor layer 05.And for IGZO semiconductors, there is copper
Atom is in the diffusion problem of IGZO films, and this can cause the short circuit of TFT devices, switch failure.
In this case, for the diffusion problem of copper atom, the present invention proposes a kind of new coplanar type thin film transistor (TFT)
Structure：Side at raceway groove sets barrier layer, and layers of copper is kept apart with semiconductor layer.
The content of the invention
It is an object of the invention to provide it is a kind of solve because the copper atom in layers of copper spreads in the semiconductor layer cause it is thin
The coplanar type TFT thin film transistor of film transistor shorted devices.
The present invention provides a kind of coplanar type thin film transistor (TFT), including：Grid；Source electrode；Drain electrode；And channel region, positioned at source
Between pole and drain electrode；Wherein, the source electrode and drain electrode are included positioned at the layers of copper of bottom and positioned at layers of copper top and portion
Divide the titanium layer positioned at the channel region side；Semiconductor layer is provided with the channel region, the titanium layer connects with the semiconductor layer
Touch.
Preferably, the titanium layer includes titanium barrier layer, and the titanium barrier layer is arranged at the channel region side, the titanium resistance
Barrier covers the layers of copper, and isolates the layers of copper and semiconductor layer.
Preferably, the distance between the layers of copper of the source electrode and the layers of copper of drain electrode are more than titanium layer and the drain electrode of the source electrode
The distance between titanium layer.
Preferably, in addition to gate insulator, it is the grid, the gate insulator below the gate insulator
Top be the source electrode, drain electrode and semiconductor layer.
Preferably, the gate insulator uses SiOXAnd SiNXFilm layer is combined, wherein, SiNXFilm layer is located at the grid
Top, the SiOXFilm layer is located at the SiNXThe top of film layer.
Preferably, the semiconductor layer is IGZO semiconductor layers
The present invention provides a kind of array base palte, including crisscross gate line and data wire again, in addition to foregoing is total to
Face type thin film transistor (TFT), the coplanar type thin film transistor (TFT) is located at the infall of the gate line and data wire.
The present invention provides a kind of method for manufacturing coplanar type thin film transistor (TFT) again, and this method includes：
The first step：Form grid；
Second step：Form the gate insulator being overlying on the grid；
3rd step：Source electrode and the drain electrode for being overlying on the gate insulator are formed, the source electrode and drain electrode are at least by Titanium
The titanium layer of formation is constituted, and forms channel region between source electrode and drain electrode, and the titanium layer is positioned at channel region；
4th step：The semiconductor layer being located in channel region is formed, the titanium layer of the titanium layer and drain electrode of semiconductor layer and source electrode connects
Touch.
Preferably, the 3rd step is concretely comprised the following steps：
The layers of copper formed by metallic copper is deposited on gate insulator；
One layer of first photoresist layer is coated with layers of copper；
First photoresist layer is exposed, the length exposed on photoresist layer is a；The layers of copper below photoresist layer is pointed to simultaneously
Quarter processing was carried out, the length of layers of copper etching is b, wherein, b>a>0；
Remove the first photoresist layer；
The titanium layer formed by Titanium is deposited in layers of copper, and titanium layer is located at the surface and side of layers of copper；
One layer of second photoresist layer is coated with titanium layer；
Second photoresist layer is exposed, the length exposed on photoresist layer is a；The titanium layer below photoresist layer is pointed to simultaneously
Processing is performed etching, channel region is formed and channel region side is provided with titanium barrier layer；
Remove the second photoresist layer；
Semiconductor layer is sputtered in trench area.
Preferably, the second step is concretely comprised the following steps：
SiN is covered on gridXFilm layer；
In SiNXSiO is formed in film layerXFilm layer.
The present invention keeps apart layers of copper with semiconductor layer at channel region, so that in follow-up titanium layer patterning process,
Layers of copper at channel region is covered, so as to stop that layers of copper is contacted with semiconductor layer.
Brief description of the drawings
Fig. 1 is the structural representation of existing coplanar type thin film transistor (TFT)；
Fig. 2 is the structural representation of coplanar type thin film transistor (TFT) of the present invention；
Fig. 3-Fig. 8 is the decomposition texture schematic diagram of the manufacture method of coplanar type thin film transistor (TFT) of the present invention.
Embodiment
Below in conjunction with the accompanying drawings and specific embodiment, the present invention is furture elucidated, it should be understood that these embodiments are merely to illustrate
The present invention rather than limitation the scope of the present invention, after the present invention has been read, those skilled in the art are each to the present invention's
The modification for planting the equivalent form of value falls within the application appended claims limited range.
As shown in Fig. 2 the present invention coplanar type thin film transistor (TFT) 100, including be overlying on substrate 1 grid 2, be overlying on grid
The channel region 7 of gate insulator 3 on 2, the source electrode and drain electrode, formation being overlying on gate insulator 3 between source electrode and drain electrode,
Wherein, source electrode and drain electrode are double-layer structure, including the layers of copper 41 positioned at bottom and the titanium layer 42 positioned at top layer, wherein, titanium layer
42 are located in layers of copper 41 and are partly located at the side of channel region 7, and channel region 7 is interior to be provided with semiconductor layer 5, and semiconductor layer 5 is overlying on source
On pole and drain electrode, titanium layer 42 is contacted with semiconductor layer 5.The distance between the layers of copper of source electrode and the layers of copper of drain electrode are more than the titanium of source electrode
The distance between layer and the titanium layer of drain electrode.
Preferably, metal used in grid is Mo, AL, Cu, Ti or single metal or composition metal in other metals；Grid
Insulating barrier 3 uses SiOXAnd SiNXFilm layer is combined, SiN is covered on gridXFilm layer, in SiNXSiO is formed in film layerXFilm layer.Its
In, SiNXWater resistance it is superior, by SiOxOxygen atom can be provided for IGZO by being placed in upper strata, prevent SiNxMiddle H diffusion shadow
Ring.Semiconductor layer 5 is IGZO semiconductor layers.
Coplanar type thin film transistor (TFT) 100 also includes the insulating barrier 6 being overlying on semiconductor layer 5, it is preferable that insulating barrier 6 can be adopted
Use SiOxOr SiNxOr combination.
Titanium layer 42 includes titanium barrier layer 8, and titanium barrier layer 8 is located at channel region 7, and titanium barrier layer 8 is isolated layers of copper 41 and partly led
Body layer 5, it is to avoid the copper atom of layers of copper 41 is diffused into semiconductor layer 5.Specifically, titanium barrier layer 8 is arranged on the side of channel region 7
Face, can cover the side of the layers of copper 41 at channel region 7.Because the contact resistance between titanium and IGZO semiconductors is 0.001 Europe
Nurse, therefore the present invention is used as the barrier layer between layers of copper and IGZO semiconductor layers from titanium.Preferably due to titanium originally source
Existing metal in pole and drain electrode, therefore, titanium barrier layer 8 are a part for titanium layer 42, it is not necessary to extra increase barrier layer, section
Production cost is saved.
Layers of copper 41 used carving technology, reserved the position of titanium barrier layer 8, so as to which titanium barrier layer 8 is deposited on into layers of copper
41 outside, it is to avoid contacted with semiconductor layer 5,
Fig. 3-Fig. 8 is the method schematic diagram of the coplanar type thin film transistor (TFT) of the present invention of manufacture, and this method includes：
S01：As shown in figure 3, the patterning of grid 2 is formed, the grid 2 being overlying on substrate 1 is formed, is concretely comprised the following steps：Film forming,
Exposure, etching.Wherein, the material used in grid 2 is single metal or the composition metals such as metal Mo, AL, Cu, Ti.
S02：As shown in figure 4, the film forming of gate insulator 3, forms the gate insulator 3 being overlying on grid 2.Preferably, grid
Pole insulating barrier 3 uses SiOXAnd SiNXFilm layer is combined, SiN is covered on gridXFilm layer, in SiNXSiO is formed in film layerXFilm layer.
By the superior SiN of water proofing propertyXLower floor is placed in, by SiOXUpper strata is placed in, so as to provide oxygen atom for IGZO semiconductors, SiN is preventedX
Middle H's extends influence.
S03：Form source electrode and the drain electrode being overlying on gate insulator 3, the titanium that source electrode and drain electrode are at least formed by Titanium
Layer is constituted, and forms channel region between source electrode and drain electrode, and the titanium layer is positioned at channel region.
Preferably, source electrode and drain electrode are double-layer structure, and bottom is layers of copper 41, and top layer is titanium layer 42.
Concretely comprise the following steps：
S031：The layers of copper formed by metallic copper is deposited on gate insulator.
S032：One layer of first photoresist layer 91 is coated with layers of copper.
S033：First photoresist layer 91 is exposed, the length exposed on photoresist layer is a；It is pointed to simultaneously under photoresist layer
The layers of copper of side carried out quarter processing, and layers of copper patterns to be formed, and the length of layers of copper etching is b, wherein, b>a>0；As shown in figure 5, from
And reserve the space of deposition titanium barrier layer.During operation, the adherence between photoresist and layers of copper can be suitably reduced, so as to promote copper
Crossing for layer is carved.
S034：Remove the first photoresist layer 91.
S035：The titanium layer 42 formed by Titanium is deposited in layers of copper 41, and titanium layer is located at the surface and side of layers of copper.
S036：One layer of second photoresist layer 92 is coated with titanium layer.
S037：Second photoresist layer 92 is exposed, the length exposed on photoresist layer is a；It is pointed to simultaneously under photoresist layer
The titanium layer of side performs etching processing, and titanium layer patterns to be formed, and forms channel region 7 and channel region side is provided with titanium barrier layer 8, such as
Shown in Fig. 6.In the side titanium deposition of channel region 7, the titanium barrier layer 8 formed between layers of copper 41 and IGZO semiconductor layers 5, so as to cover
Layers of copper 41 at lid channel region 7 so that source electrode and the titanium layer 42 of drain electrode are less than source electrode and leakage between channel region 7 apart from b
Gap a of the layers of copper 41 of pole at channel region 7.During operation, the adherence between photoresist and titanium layer can be suitably lifted, so as to keep away
Exempt from crossing for titanium layer to carve.
S038：Remove the second photoresist layer；
S04：As shown in fig. 7, IGZO film forming, semiconductor layer is sputtered in channel region, half be overlying on source electrode and drain electrode is formed
Conductor layer 5.Semiconductor layer 5 is located in channel region 7, utilizes the titanium barrier layer 8 at channel region 7, it is to avoid contact, prevent with layers of copper 41
Copper atom is diffused into semiconductor layer.
S05：As shown in figure 8, forming the insulating barrier 6 being overlying on semiconductor layer 5；Concretely comprise the following steps film forming, exposure, etching.
Wherein, the material of insulating barrier 6 can use SiOXOr SiNXOr combination.
The manufacture method of the present invention, its technique needs 5 road light shields altogether, wherein forming layers of copper and sharing same when forming titanium layer
Light shield, relative to Lift-off techniques (stripping technology), has lacked 1 road light shield, has optimized production technology, saved manufacturing cost.
The present invention is based on the diffusion problem between copper and IGZO, by layers of copper patterning process, at channel region
Copper carries out appropriate crossing and carved, and the side at channel region sets barrier layer, so that the copper at titanium covering channel region.Due to copper with
Stress between titanium is just matched, and the neutralization stress of laminated film is reduced, and improves the adhesion between metallic copper and dielectric film,
And the contact resistance between titanium and IGZO is 0.001 ohm, therefore the barrier layer between copper and IGZO layers is used as from titanium.And
Due to existing metal in titanium originally source electrode and drain electrode, it is not necessary to extra increase barrier layer.Solve copper atom to
Spread in IGZO films, cause the leakage current of TFT devices to increase, the problem of switch failure, reached and avoided copper atom to IGZO
The technique effect spread in film.
Claims (10)
1. a kind of coplanar type thin film transistor (TFT), including：
Grid (2)；
Source electrode；
Drain electrode；And
Channel region (7), between source electrode and drain electrode；Wherein,
The source electrode and drain electrode are including above the layers of copper (41) and being located at positioned at the layers of copper (41) of bottom and partly
The titanium layer (42) of channel region (7) side；Be provided with semiconductor layer (5) in the channel region (7), the titanium layer (42) with it is described
Semiconductor layer (5) is contacted.
2. coplanar type thin film transistor (TFT) according to claim 1, it is characterised in that the titanium layer (42) includes titanium barrier layer
(8), the titanium barrier layer (8) is arranged at the channel region (7) side, and the titanium barrier layer (8) covers the layers of copper (41), and
Isolate the layers of copper (41) and semiconductor layer (5).
3. coplanar type thin film transistor (TFT) according to claim 1, it is characterised in that the layers of copper of the source electrode and the copper of drain electrode
The distance between layer (41) is more than the distance between the titanium layer of the source electrode and the titanium layer (42) of drain electrode.
4. coplanar type thin film transistor (TFT) according to claim 1, it is characterised in that described also including gate insulator (3)
It above the grid, the gate insulator is the source electrode, drain electrode and semiconductor layer to be below gate insulator.
5. coplanar type thin film transistor (TFT) according to claim 4, it is characterised in that the gate insulator (3) uses SiOX
And SiNXFilm layer is combined, wherein, SiNXFilm layer is located at the top of the grid, the SiOXFilm layer is located at the SiNXFilm layer
Top.
6. coplanar type thin film transistor (TFT) according to claim 1, it is characterised in that the semiconductor layer (5) is IGZO half
Conductor layer.
7. a kind of array base palte, including crisscross gate line and data wire, it is characterised in that also including claim 1-6
Any one of coplanar type thin film transistor (TFT), the coplanar type thin film transistor (TFT) is located at the friendship of the gate line and data wire
At fork.
8. a kind of method for manufacturing coplanar type thin film transistor (TFT), this method includes：
The first step：Form grid (2)；
Second step：Formation is overlying on the gate insulator (3) on the grid (2)；
3rd step：Formation is overlying on source electrode and the drain electrode of the gate insulator (3), and the source electrode and drain electrode are at least by Titanium shape
Into titanium layer constitute, and between source electrode and drain electrode formed channel region (7), the titanium layer be located at channel region；
4th step：The semiconductor layer (5) being located in channel region is formed, the titanium layer of the titanium layer and drain electrode of semiconductor layer and source electrode connects
Touch.
9. method according to claim 8, it is characterised in that the 3rd step is concretely comprised the following steps：
The layers of copper formed by metallic copper is deposited on gate insulator (3)；
One layer of first photoresist layer is coated with layers of copper；
First photoresist layer is exposed, the length exposed on photoresist layer is a；The layers of copper below photoresist layer is pointed to simultaneously to carry out
Quarter processing is crossed, the length of layers of copper etching is b, wherein, b>a>0；
Remove the first photoresist layer；
The titanium layer formed by Titanium is deposited in layers of copper, and titanium layer is located at the surface and side of layers of copper；
One layer of second photoresist layer is coated with titanium layer；
Second photoresist layer is exposed, the length exposed on photoresist layer is a；The titanium layer below photoresist layer is pointed to simultaneously to carry out
Etching processing, forms channel region and channel region side is provided with titanium barrier layer；
Remove the second photoresist layer.
10. method according to claim 8, it is characterised in that the second step is concretely comprised the following steps：
SiN is covered on gridXFilm layer；
In SiNXSiO is formed in film layerXFilm layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109616524A (en) * | 2018-11-28 | 2019-04-12 | 南京中电熊猫平板显示科技有限公司 | Thin film transistor (TFT) and its manufacturing method |
| CN114185209A (en) * | 2022-02-17 | 2022-03-15 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109616524A (en) * | 2018-11-28 | 2019-04-12 | 南京中电熊猫平板显示科技有限公司 | Thin film transistor (TFT) and its manufacturing method |
| CN114185209A (en) * | 2022-02-17 | 2022-03-15 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and display device |
| CN114185209B (en) * | 2022-02-17 | 2022-05-27 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and display device |
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Application publication date: 20171103 |