CN107302025B - A kind of VDMOS device with anti-single particle effect - Google Patents
A kind of VDMOS device with anti-single particle effect Download PDFInfo
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- 239000002245 particle Substances 0.000 title claims abstract description 58
- 230000000694 effects Effects 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 120
- 239000002184 metal Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 description 8
- 238000000407 epitaxy Methods 0.000 description 5
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- 230000008901 benefit Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 208000035859 Drug effect increased Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
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- 238000004377 microelectronic Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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Abstract
The present invention provides a kind of VDMOS device with anti-single particle effect, predominantly the first conductive type semiconductor buried layer is arranged in the second conductive type semiconductor body area in the technical solution adopted by the present invention, generate hole barrier, hole is prevented to flow through the second conductive type semiconductor body area, and the second conductive type semiconductor column being connected with source electrode is set in the epitaxial layer of side under the gate, hole access is provided, the anti-single particle of VDMOS when being incident on all positions present invention greatly enhances single-particle burns ability, anti-single particle grid wear ability simultaneously can also be improved well, furthermore, the VDMOS device of anti-single particle effect proposed by the present invention is under the premise of guaranteeing breakdown voltage, effectively reduce the conducting resistance of device, simultaneously because reducing the area coverage of gate electrode, the VDMOS structure it is close Capacitor is strangled to substantially reduce.
Description
Technical field
The present invention relates to technical field of semiconductor device, and in particular to a kind of VDMOS device with anti-single particle effect.
Background technique
Fast development with from power electronic technique to high-frequency high-power application field, VDMOS become field of power electronics
In one of irreplaceable important devices, it is increasing using the power electronic circuit of VDMOS.The structure devices generally use
Secondary diffusion or ion implantation technique are formed, and are multi cell devices, are easily integrated, and power density is big, and more subconductivity, and frequency is special
Property is good.VDMOS is one of mainstream device of power MOS at present.As power switch, VDMOS has high pressure resistant, switching speed
Fastly, it is widely used the advantages that low on-resistance, low driving power, good thermal stability, low noise and simple manufacturing process
In the various fields such as Switching Power Supply, AC Drive, variable-frequency power sources, computer equipment, and obtain ideal effect.
The irradiation effect of semiconductor devices is a complicated problem, because of different types of irradiation, to semiconductor devices
Influence be different.There are mainly four types of the irradiation of type to generate irradiation effect to semiconductor devices, they are matter respectively
Son, electronics, neutron and gamma-rays.Microelectronic component is had an important influence on and the factor of most study mainly has γ accumulated dose spoke
It penetrates, gamma dose rate radiation, neutron irradiation and single particle effect.
The single particle effect of VDMOS is broadly divided into single event gate rupture (SEB) and single event burnout (SEGR).As power MOS
When pipe turns off, it may occur that SEGR damage.I.e. when heavy ion bombardment side under the gate, the track in substrate nearby generates high density
Plasma, under electric field action, electron hole pair is opposite to drift about, and the charge accumulated on the downside of grid is formed, at this point, grid is similar
Capacitor with a large amount of charge accumulateds can puncture gate oxygen structure when capacitor both ends pressure difference is sufficiently high, to cause irrecoverable
Physical damnification.
Between the source N+ of VDMOS, P-channel and the drift region N- being lightly doped, there is a parasitic transistor structure, they
Emitter region, base area and the collecting zone of parasitic transistor are respectively constituted, under normal circumstances, the emitter and base stage of parasitic transistor are logical
It crosses source electrode and realizes short circuit, so that the external behavior to device does not have an impact.Under radiation environment, particle is injected in VDMOS device
A large amount of electron hole pairs are generated in part, under drift field and diffusion double action, is spread and is drifted about, and wink power generation stream is formed.Wink
The horizontal proliferation of power generation stream generates pressure drop on the resistance of base area, when pressure drop increases to certain value, parasitic transistor conducting.When
When the drain-source voltage of MOS transistor is greater than breakdown voltage, the electric current for flowing through transistor can further be fed back, so that depletion region
Current density is gradually increasing, and causes second breakdown between drain-source, if junction temperature is more than permissible value, source-drain junction is caused to burn.
Thus reduce the resistance below VDMOS device N+ source region, i.e. the increase area Pbody concentration is to improve having of burning of device anti-single particle
Efficacious prescriptions method.For traditional structure as shown in Figure 1, considering the influence to device threshold, the area Pbody concentration cannot be too big, to reduction VDMOS
Without obvious effect, traditional structure does not have anti-single particle substantially and burns ability resistance below device N+ source region.As shown in Fig. 2,
A kind of invention " VDMOS device with anti-single particle effect " of Publication No. CN105118862A proposes a kind of novel
VDMOS device introduces the second conductive type semiconductor column and separate gate structures in the area JFET, obtains preferable anti-single particle effect
It should be able to power and lower Miller capacitance.But for the structure, the second conductive type semiconductor column position is incident in single-particle
When can obtain preferable anti-single particle effect capability, and be incident on other positions in single-particle, when such as body contact zone, fight simple grain
The raising of sub- effect capability is very limited.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of with anti-single particle effect
VDMOS device.
For achieving the above object, technical solution of the present invention is as follows:
A kind of VDMOS device with anti-single particle effect, it is the drain metal electrode that is cascading from bottom to up, heavily doped
Miscellaneous first conductive type semiconductor substrate, the first conductive type semiconductor epitaxial layer, source metal electrode；First conductive-type
There is type semiconductor layer inner upper the second conductive type semiconductor body area, the second conductive type semiconductor column and first to lead
Electric type semiconductor area；The doping concentration in first conductive type semiconductor area is the first conductive type semiconductor epitaxial layer
10 times or more, the second conductive type semiconductor column is located between two the second conductive type semiconductor body areas, and second is conductive
Type semiconductor column upper surface is connect with source metal electrode, and first conductive type semiconductor area is located at the second conduction type
Between semiconductor body and the second conductive type semiconductor column；The first conductive type semiconductor epitaxial layer upper surface and source electrode
There is gate structure and dielectric layer between metal；The gate structure is by gate oxide and positioned at the more of gate oxide upper surface
Crystal silicon grid are constituted, and the first conductive type semiconductor area is completely covered in the polysilicon gate；The second conductive type semiconductor body
There is the first conductive type semiconductor source region, the second conductive type semiconductor body contact zone and the first conduction type half in area
Conductor buried layer；The upper surface of the first conductive type semiconductor source region and the second conductive type semiconductor body contact zone is and source
The connection of pole metal electrode；The first conductive type semiconductor buried layer is located at the first conductive type semiconductor source region and the second conduction
The side of type semiconductor body contact zone and bottom section, the first conductive type semiconductor buried layer is by the first conductive type semiconductor
Source region and the second conductive type semiconductor body contact zone are surrounded completely, the first conductive type semiconductor buried layer and the first conduction type
By the second conductive type semiconductor body section every first between semiconductor source region and the second conductive type semiconductor body contact zone
Pass through the second conductive type semiconductor body section between conductive type semiconductor buried layer and the first conductive type semiconductor epitaxial layer
Every.
It is preferred that the gate structure is slot grid structure.
It is preferred that the first conduction type is p-type, the second conduction type is N-type；Or first conduction type be N
Type, the second conduction type are p-type.
The invention has the benefit that greatly improving the anti-simple grain of VDMOS when single-particle is incident on all positions
Son burns ability, while anti-single particle grid are worn ability and can also be improved well.Further it is proposed that anti-single particle effect
The VDMOS device answered effectively reduces the conducting resistance of device under the premise of guaranteeing breakdown voltage.Simultaneously because reducing grid
The Miller capacitance of the area coverage of electrode, the VDMOS structure substantially reduces.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of ordinary power VDMOS in the prior art；
Fig. 2 is a kind of knot of the invention " VDMOS device with anti-single particle effect " of Publication No. CN105118862A
Structure schematic diagram；
Fig. 3 is a kind of structural schematic diagram of VDMOS device with anti-single particle effect of the invention；
Fig. 4 be in the prior art ordinary power VDMOS occur single-particle radiation when electrons and holes flow graph；
Fig. 5 is a kind of invention " VDMOS device with anti-single particle effect " of Publication No. CN105118862A in list
Particle is incident on electrons and holes flow graph when JFET zone position；
Fig. 6 is a kind of invention " VDMOS device with anti-single particle effect " of Publication No. CN105118862A in list
Particle is incident on electrons and holes flow graph when body contact zone position；
Fig. 7 is a kind of VDMOS with anti-single particle effect of the invention when single-particle is incident on body contact zone position
Electrons and holes flow graph.
Wherein, 1 is source metal electrode, and 2 be polysilicon gate, and 3 be gate oxide, and 4 be dielectric layer, and 5 be the first conductive-type
Type semiconductor source region, 6 be the second conductive type semiconductor body area, and 7 be the second conductive type semiconductor body contact zone, and 8 be first
Conductive type semiconductor epitaxial layer, 9 be the first conductive type semiconductor of heavy doping substrate, and 10 be drain metal electrode, and 11 be the
Two conductive type semiconductor columns, 12 be the first conductive type semiconductor area, and 13 be the first conductive type semiconductor buried layer.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
As shown in figure 3, a kind of VDMOS device with anti-single particle effect, be cascading the gold that drains from bottom to up
Belong to electrode 10, the first conductive type semiconductor of heavy doping substrate 9, the first conductive type semiconductor epitaxial layer 8, source metal electrode
1；First conductive type semiconductor epitaxial layer, 8 inner upper has the second conductive type semiconductor body area 6, the second conductive-type
Type semiconductor column 11 and the first conductive type semiconductor area 12；The doping concentration in first conductive type semiconductor area 12 is
10 times or more of one conductive type semiconductor epitaxial layer 8, the second conductive type semiconductor column 11 are located at two second conductions
Between type semiconductor body area 6,11 upper surface of the second conductive type semiconductor column is connect with source metal electrode 1, and described first
Conductive type semiconductor area 12 is between the second conductive type semiconductor body area 6 and the second conductive type semiconductor column 11；Institute
Stating has gate structure and dielectric layer 4 between 8 upper surface of the first conductive type semiconductor epitaxial layer and source metal 1；The grid
Polysilicon gate 2 of the pole structure by gate oxide 3 and positioned at 3 upper surface of gate oxide is constituted, and the polysilicon gate 2 is completely covered
First conductive type semiconductor area 12；There is the first conductive type semiconductor source in the second conductive type semiconductor body area 6
Area 5, the second conductive type semiconductor body contact zone 7 and the first conductive type semiconductor buried layer 13；First conduction type
The upper surface of semiconductor source region 5 and the second conductive type semiconductor body contact zone 7 is connect with source metal electrode 1；Described
One conductive type semiconductor buried layer 13 is located at the first conductive type semiconductor source region 5 and the second conductive type semiconductor body contact zone
7 side and bottom section, the first conductive type semiconductor buried layer 13 are conductive by the first conductive type semiconductor source region 5 and second
Type semiconductor body contact zone 7 is surrounded completely, the first conductive type semiconductor buried layer 13 and the first conductive type semiconductor source region 5
And second be spaced between conductive type semiconductor body contact zone 7 by the second conductive type semiconductor body area 6, the first conduction type
It is spaced between semiconductor buried layer 13 and the first conductive type semiconductor epitaxial layer 8 by the second conductive type semiconductor body area 6.
Preferably, the gate structure is slot grid structure.
Preferably, the first conduction type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, second
Conduction type is p-type.
Next by taking the VDMOS device of N-channel anti-single particle effect as an example, illustrate the working principle of the invention:
(1) forward conduction of device:
VDMOS device provided by the present invention with anti-single particle effect, electrode connection mode when forward conduction
Are as follows: polysilicon gate 2 increases current potential, and the current potential on drain metal electrode 10 gradually rises, and source metal electrode 1 connects low potential.
When polysilicon gate 2 connects high potential and is greater than threshold voltage relative to source metal electrode 1,6 surface shape of the area PXing Ti
At inversion layer, 13 surface of n type buried layer forms accumulation layer, and channel is collectively formed in inversion layer and accumulation layer.When drain metal electrode 10
On current potential gradually rise, electronics flows to heavily doped N-type substrate 9 from N-type source region 5.So relative to conventional VDMOS, the present invention
In the provided VDMOS device with anti-single particle effect increased n type buried layer 13 and p-type column 11 do not influencing device just
Often conducting.And since accumulation layer is more readily formed relative to inversion layer, threshold voltage can reduce to a certain extent, thus in phase
Available thicker gate oxide under same threshold voltage, obtains smaller grid leakage current.The present invention has the drawback that P
Type column 11 and N-type epitaxy layer 8 mutually exhaust, and reduce the increase that the area JFET area causes conducting resistance.But p-type column 11 and N-type
Epitaxial layer forms half super-junction structure of class, can be by increasing by properly increasing drift region 8 on the basis of guaranteeing breakdown voltage
With the concentration in the area JFET 12, the conducting resistance of device is reduced.
(2) reverse blocking of device:
VDMOS device provided by the present invention with anti-single particle effect, electrode connection mode when reverse blocking
Are as follows: drain metal electrode 10 connects high potential, and source metal electrode 1 and polysilicon gate 2 connect low potential.
The reverse blocking principle and routine VDMOS of VDMOS device provided by the present invention with anti-single particle effect are former
Manage it is identical, PN junction composed by the area Dou YouPXing Ti 6 and N-type epitaxy layer 8 provide pressure resistance, depletion layer mainly toward N-type epitaxy layer 8 expand
Exhibition.And since p-type column 11 and N-type epitaxy layer form half super-junction structure of class, breakdown voltage can be improved to a certain extent.
(3) anti-single particle radiation principle:
As shown in figure 4, the position JFET is most sensitive region, high energy particle excitation as single-particle incidence routine VDMOS
Electron hole pair out, wherein hole can only flow to source electrode by 5 area XiaPXing Ti 6 of N-type source region, therefore easily cause parasitic three poles
The unlatching of pipe；On the other hand, the carrier for being accumulated in the area JFET surface can also cause the voltage difference of grid oxygen two sides to increase, and generate grid
It wears.
As shown in figure 5, the invention as single-particle incidence Publication No. CN105118862A is " a kind of to have anti-single particle effect
VDMOS device " provided by anti-single particle effect VDMOS device the position JFET when, due to the P being connected with source electrode 1
The introducing of type column 11, the transverse electric field formed between p-type column and N-type epitaxy layer 8, high energy particle excitation generate electronics-
Hole is to rear, and electronics is received by drain metal electrode 10, and hole is not moved under the action of transverse electric field to p-type column 11, directly
It is received by source metal electrode 1；Since N type junction structure being not present in p-type column 11, parasitic transistor is not present, thus effectively
Avoid the conducting of parasitic transistor.In addition, single event gate rupture occurs mainly in the gate oxide portion of the area JFET upper surface portion
Point, grid structure is made into discrete by this structure, is source metal between polysilicon gate 2, substantially improves single event gate rupture effect.
But when it is incident on other positions, as shown in fig. 6, due to hole apart from p-type column 11 farther out, via the area PXing Ti 6 reach source
The path resistor of pole 1 is smaller, so most of hole flows to source metal electrode 1 by the area PXing Ti 6, equally be easy to cause and posts
The unlatching of raw triode.That is the invention of Publication No. CN105118862A " a kind of VDMOS device with anti-single particle effect "
Anti-single particle effect capability when single-particle is incident on other positions is weaker.
For Publication No. CN105118862A invention " a kind of VDMOS device with anti-single particle effect " at remaining
The weaker problem of the anti-single particle effect capability of position, the VDMOS device provided by the present invention with anti-single particle effect is in P
N type buried layer 13 is introduced in the area Xing Ti 6.As shown in fig. 7, the area n type buried layer 13 and PXing Ti 6 mutually exhausts, hole barrier is formed
Layer.Generated hole can not be flowed through the area PXing Ti 6 and be reached source electrode due to the presence of barrier layer when single-particle incidence, can only be via
P-type column 11 reaches source electrode, avoids the unlatching of parasitic triode.So the VDMOS of anti-single particle effect provided by the present invention
Device to single-particle incidence in any position the case where all there is anti-single particle effect capability well.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed without departing from the spirit and technical ideas disclosed in the present invention
All equivalent modifications or change, should be covered by the claims of the present invention.
Claims (3)
1. a kind of VDMOS device with anti-single particle effect, it is characterised in that: be cascading drain metal from bottom to up
Electrode (10), heavy doping the first conductive type semiconductor substrate (9), the first conductive type semiconductor epitaxial layer (8), source metal
Electrode (1)；First conductive type semiconductor epitaxial layer (8) inner upper have the second conductive type semiconductor body area (6),
Second conductive type semiconductor column (11) and the first conductive type semiconductor area (12)；First conductive type semiconductor area
(12) doping concentration is 10 times or more of the first conductive type semiconductor epitaxial layer (8), second conductive type semiconductor
Column (11) is located between two the second conductive type semiconductor body areas (6), the second conductive type semiconductor column (11) upper surface with
Source metal electrode (1) connection, first conductive type semiconductor area (12) is located at the second conductive type semiconductor body area (6)
Between the second conductive type semiconductor column (11)；The first conductive type semiconductor epitaxial layer (8) upper surface and source electrode gold
Belonging to has gate structure and dielectric layer (4) between (1)；The gate structure is by gate oxide (3) and is located at gate oxide (3)
The polysilicon gate (2) of upper surface is constituted, and the first conductive type semiconductor area (12) is completely covered in the polysilicon gate (2)；It is described
There is the first conductive type semiconductor source region (5), the second conductive type semiconductor body in second conductive type semiconductor body area (6)
Contact zone (7) and the first conductive type semiconductor buried layer (13)；The first conductive type semiconductor source region (5) and second
The upper surface of conductive type semiconductor body contact zone (7) is connect with source metal electrode (1)；First conduction type is partly led
Body buried layer (13) is located at the side of the first conductive type semiconductor source region (5) and the second conductive type semiconductor body contact zone (7)
And bottom section, the first conductive type semiconductor buried layer (13) is by the first conductive type semiconductor source region (5) and the second conductive-type
Type semiconductor body contact zone (7) is surrounded completely, the first conductive type semiconductor buried layer (13) and the first conductive type semiconductor source
It is spaced between area (5) and the second conductive type semiconductor body contact zone (7) by the second conductive type semiconductor body area (6), the
It is partly led between one conductive type semiconductor buried layer (13) and the first conductive type semiconductor epitaxial layer (8) by the second conduction type
The area Ti Ti (6) interval.
2. a kind of VDMOS device with anti-single particle effect according to claim 1, it is characterised in that: the grid
Structure is slot grid structure.
3. a kind of VDMOS device with anti-single particle effect according to claim 1 or 2, it is characterised in that: first leads
Electric type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, the second conduction type be p-type.
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| CN201710625741.2A CN107302025B (en) | 2017-07-27 | 2017-07-27 | A kind of VDMOS device with anti-single particle effect |
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| CN201710625741.2A CN107302025B (en) | 2017-07-27 | 2017-07-27 | A kind of VDMOS device with anti-single particle effect |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108831835A (en) * | 2018-06-22 | 2018-11-16 | 重庆平伟实业股份有限公司 | The forming method of power semiconductor |
| CN108831834A (en) * | 2018-06-22 | 2018-11-16 | 重庆平伟实业股份有限公司 | The forming method of power semiconductor |
| CN109801957B (en) * | 2018-12-05 | 2022-04-26 | 中国科学院微电子研究所 | Super junction device structure, device and preparation method |
| CN109786465B (en) * | 2018-12-17 | 2022-07-15 | 重庆平伟实业股份有限公司 | Power semiconductor device and method for manufacturing the same |
| CN112768521B (en) * | 2019-10-21 | 2022-08-12 | 东南大学 | Lateral double-diffused metal oxide semiconductor device |
| CN113097300A (en) * | 2019-12-23 | 2021-07-09 | 华润微电子（重庆）有限公司 | Power device and manufacturing method thereof |
| CN117673161A (en) * | 2024-02-01 | 2024-03-08 | 深圳天狼芯半导体有限公司 | Planar gate silicon carbide device, preparation method thereof and chip |
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