CN107301952B - Self-alignment method for grid field plate, source electrode and drain electrode in planar power device - Google Patents
Self-alignment method for grid field plate, source electrode and drain electrode in planar power device Download PDFInfo
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- CN107301952B CN107301952B CN201710406570.4A CN201710406570A CN107301952B CN 107301952 B CN107301952 B CN 107301952B CN 201710406570 A CN201710406570 A CN 201710406570A CN 107301952 B CN107301952 B CN 107301952B
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000011248 coating agent Substances 0.000 claims abstract description 12
- 238000000576 coating method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66515—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned selective metal deposition simultaneously on the gate and on source or drain
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention relates to a self-alignment method of a grid field plate, a source electrode and a drain electrode in a planar power device, which comprises the steps of forming an insulating layer on a substrate, coating negative photoresist, and carrying out photoetching development to form a first grid/source/drain electrode region; etching the bottom insulating layer of the first grid/source/drain electrode area to form a grid/source/drain electrode groove; coating positive photoresist for photoetching development, and forming positive photoresist filling in the gate groove and the first gate region; forming a source/drain metal layer in the source/drain trench; removing the negative/positive photoresist filling; forming a gate insulating layer on the upper surface of the device; coating a negative photoresist on the gate insulating layer for photoetching development, and forming a second gate region on the negative photoresist and above the gate trench; forming a gate metal layer in the gate groove and the second gate region; and removing the coated negative photoresist. The invention eliminates misalignment between the gate and the source/drain; the processing allowance of the device is improved; the yield of large-diameter wafer devices is improved.
Description
Technical Field
The invention relates to a self-alignment method of a grid field plate, a source electrode and a drain electrode in a planar power device.
Background
In planar power conversion devices where the gate is used for schottky contacts or MIS contacts and the source and drain are used for ohmic contacts, where the gate, source and drain are all formed in fixed positions, i.e., where alignment between the gate and source and drain is required, existing methods use a separate gate mask that requires alignment with the source/drain mask when forming the gate, source and drain, however, depending on the capabilities of the camera tool, such conventional methods will always result in misalignment between the gate and source/drain, or fail to meet the alignment requirements.
Disclosure of Invention
The invention aims to provide a self-alignment method of a grid field plate and a source electrode and a drain electrode in a planar power device.
In order to achieve the purpose, the invention adopts the technical scheme that:
a self-alignment method of a grid field plate and a source electrode and a drain electrode in a planar power device comprises the following steps:
(1) forming an insulating layer on a substrate, coating a negative photoresist on the insulating layer, carrying out photoetching development on the negative photoresist through a grid, a source electrode and a drain electrode mask plate, and forming a first grid region, a source electrode region and a drain electrode region on the negative photoresist;
(2) etching the insulating layer at the bottoms of the first gate region, the source region and the drain region to form a gate groove, a source groove and a drain groove;
(3) coating positive photoresist on the upper surface of the device, carrying out photoetching development on the positive photoresist through a grid field plate mask plate, and forming positive photoresist filling in the grid groove and the first grid region;
(4) forming a source metal layer and a drain metal layer in the source trench and the drain trench;
(5) removing the negative photoresist and the positive photoresist coated in the steps (1) and (3) to fill;
(6) forming a grid electrode insulating layer on the upper surface of the device;
(7) coating a negative photoresist on the gate insulating layer, carrying out photoetching development on the negative photoresist through a gate field plate mask plate, and forming a second gate region on the negative photoresist and above the gate trench, wherein the width of the second gate region is greater than that of the gate trench;
(8) forming a gate metal layer in the gate groove and the second gate region;
(9) and removing the negative photoresist coated in the step (6).
Preferably, in (1), the insulating layer includes a first insulating layer formed on the substrate, a second insulating layer formed on the first insulating layer, and a negative photoresist is coated on the second insulating layer.
Further preferably, the thickness of the first insulating layer is 0 to 25 nm; the thickness of the second insulating layer is 25-200 nm.
Further preferably, the first insulating layer and the second insulating layer are oxide insulating layers or nitride insulating layers.
Preferably, in (2), the insulating layer is etched to the substrate for the bottom of the first gate region, source region and drain region.
Preferably, in (2), the etching is wet etching or dry etching.
Preferably, in (6), the gate insulating layer is a silicon nitride insulating layer or an oxide insulating layer.
Preferably, in (6), the gate insulating layer has a thickness of 0 to 20 nm.
Preferably, in (7), the height of the second gate region forming the gate metal layer is 50-250 nm.
Preferably, the metal layer is removed by a liftoff process in (4) and (8), and the source metal layer, the drain metal layer and the gate metal layer are annealed.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages and effects:
1. misalignment between the gate and the source/drain is effectively eliminated;
2. the machining allowance of the small geometric device is improved;
3. the yield of the large-diameter wafer device is effectively improved.
Drawings
FIGS. 1-10 are step diagrams of this embodiment.
Wherein: 1. a substrate; 20. a first insulating layer; 21. a second insulating layer; 2a, a grid groove; 2b, source electrode grooves; 2c, a drain electrode groove; 30. a negative photoresist; 30a, a first gate region; 30b, a source region; 30c, a drain region; 31. a negative photoresist; 31a, a second gate region; 4. filling positive photoresist; 5. a metal layer; 5b, a source metal layer; 5c, a drain metal layer; 6. a gate insulating layer; 7. a metal layer; 7a, a gate metal layer.
Detailed Description
The invention is further described below with reference to the accompanying drawings and embodiments:
a self-alignment method of a grid field plate, a source electrode and a drain electrode in a planar power device specifically comprises the following steps:
(1) forming an insulating layer on the substrate 1, wherein the insulating layer specifically comprises: a first insulating layer 20 formed on the substrate 1, a second insulating layer 21 formed on the first insulating layer 20, the thickness of the first insulating layer 20 being 0-25nm, the thickness of the second insulating layer 21 being 25-200nm, and an oxide insulating layer or a nitride insulating layer may be used for the first insulating layer 20 and the second insulating layer 21, as shown in fig. 1;
(2) coating a negative photoresist 30 on the second insulating layer 21, performing photolithography development on the negative photoresist 30 through a Gate, Source and Drain mask (Gate/Source/Drain mask), and forming a first Gate region 30a, a Source region 30b and a Drain region 30c on the negative photoresist 30, as shown in fig. 2;
(3) etching the insulating layer at the bottom of the first gate region 30a, the source region 30b and the drain region 30c to form a gate trench 2a, a source trench 2b and a drain trench 2c, and etching the oxide layer to the substrate 1, wherein wet etching (wet etching) and dry etching (dry etching) can be performed by using an etching manner, as shown in fig. 3;
(4) coating positive photoresist on the device, carrying out photoetching development on the positive photoresist through a Gate field plate mask, and forming positive photoresist filling 4 in the Gate groove 2a and the first Gate region 30a, wherein the positive photoresist filling is formed on the negative photoresist 30 on two sides of the first Gate region 30a except the filling inside and outside the Gate groove 2a and the first Gate region 30a due to the adoption of the Gate field plate mask, as shown in fig. 4;
(5) forming a source metal layer 5b and a drain metal layer 5c in the source trench 2b and the drain trench 2c, and simultaneously forming a metal layer 5 on the whole negative photoresist 30 and the positive photoresist filling 4 in addition to forming an ohmic metal layer in the source trench 2b and the drain trench 2c, as shown in fig. 5;
(6) removing the negative photoresist 30 and the metal layer 5 on the positive photoresist filling layer 4 in a liftoff process, removing the negative photoresist 30 and the positive photoresist filling layer 4 coated in the steps (2) and (4), as shown in fig. 6, and annealing the source metal layer 5b and the drain metal layer 5 c;
(7) forming a gate insulating layer 6 on the upper surface of the device, wherein the thickness of the gate insulating layer 6 is 0-20nm, and the gate insulating layer 6 may be a silicon nitride insulating layer or an oxide insulating layer, as shown in fig. 7;
(8) coating a negative photoresist 31 on the Gate insulating layer 6, performing photolithography development on the negative photoresist 31 through a Gate field plate mask (Gate field plate), forming a second Gate region 31a on the negative photoresist 31 and the Gate trench 2a, wherein the width of the second Gate region 31a is greater than that of the Gate trench 2a, as shown in fig. 8;
(9) forming a gate metal layer 7a in the gate trench 2a and the second gate region 31a, wherein the height of the gate metal layer 7 formed on the second gate region 31a is 50-250nm, as shown in fig. 9; in addition to forming the gate metal layer 7a in the gate trench 2a and the second gate region 31a, the metal layer 7 is also formed on the negative photoresist 31;
(10) and removing the metal layer 7 on the negative photoresist 31 by a liftoff process, and removing the negative photoresist 31 coated in the step (8) to form the product shown in fig. 10.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A self-alignment method of a grid field plate, a source electrode and a drain electrode in a planar power device is characterized in that: the method comprises the following steps:
(1) forming an insulating layer on a substrate, coating a negative photoresist on the insulating layer, carrying out photoetching development on the negative photoresist through a grid, a source electrode and a drain electrode mask plate, and forming a first grid region, a source electrode region and a drain electrode region on the negative photoresist;
(2) etching the insulating layer at the bottoms of the first gate region, the source region and the drain region to form a gate groove, a source groove and a drain groove;
(3) coating positive photoresist on the upper surface of the device, carrying out photoetching development on the positive photoresist through a grid field plate mask plate, and forming positive photoresist filling in the grid groove and the first grid region;
(4) forming a source metal layer and a drain metal layer in the source trench and the drain trench;
(5) removing the negative photoresist and the positive photoresist coated in the steps (1) and (3) to fill;
(6) forming a grid electrode insulating layer on the upper surface of the device;
(7) coating a negative photoresist on the gate insulating layer, carrying out photoetching development on the negative photoresist through a gate field plate mask plate, and forming a second gate region on the negative photoresist and above the gate trench, wherein the width of the second gate region is greater than that of the gate trench;
(8) forming a gate metal layer in the gate groove and the second gate region;
(9) and (5) removing the negative photoresist formed in the step (7).
2. The self-alignment method of the gate field plate and the source electrode and the drain electrode in the planar power device as claimed in claim 1, wherein: in (1), the insulating layer includes a first insulating layer formed on the substrate, a second insulating layer formed on the first insulating layer, and a negative photoresist is coated on the second insulating layer.
3. The self-alignment method of the gate field plate and the source electrode and the drain electrode in the planar power device as claimed in claim 2, wherein: the thickness of the first insulating layer is 0-25 nm; the thickness of the second insulating layer is 25-200 nm.
4. The self-alignment method of the gate field plate and the source electrode and the drain electrode in the planar power device as claimed in claim 2, wherein: the first insulating layer and the second insulating layer are oxide insulating layers or nitride insulating layers.
5. The self-alignment method of the gate field plate and the source electrode and the drain electrode in the planar power device as claimed in claim 1, wherein: in (2), the insulating layer is etched to the substrate at the bottom of the first gate region, the source region and the drain region.
6. The self-alignment method of the gate field plate and the source electrode and the drain electrode in the planar power device as claimed in claim 1, wherein: in (2), the etching is wet etching or dry etching.
7. The self-alignment method of the gate field plate and the source electrode and the drain electrode in the planar power device as claimed in claim 1, wherein: in (6), the gate insulating layer is a silicon nitride insulating layer or an oxide insulating layer.
8. The self-alignment method of the gate field plate and the source electrode and the drain electrode in the planar power device as claimed in claim 1, wherein: in (6), the gate insulating layer has a thickness of 0 to 20 nm.
9. The self-alignment method of the gate field plate and the source electrode and the drain electrode in the planar power device as claimed in claim 1, wherein: in (8), the height of the gate metal layer formed in the second gate region is 50-250 nm.
10. The self-alignment method of the gate field plate and the source electrode and the drain electrode in the planar power device as claimed in claim 1, wherein: and (5) removing through a liftoff process in the steps (5) and (9), and annealing the source metal layer, the drain metal layer and the gate metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710406570.4A CN107301952B (en) | 2017-06-02 | 2017-06-02 | Self-alignment method for grid field plate, source electrode and drain electrode in planar power device |
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| CN201710406570.4A CN107301952B (en) | 2017-06-02 | 2017-06-02 | Self-alignment method for grid field plate, source electrode and drain electrode in planar power device |
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| CN107301952A CN107301952A (en) | 2017-10-27 |
| CN107301952B true CN107301952B (en) | 2019-12-27 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5356824A (en) * | 1992-02-26 | 1994-10-18 | France Telecom Establissement Autonome De Droit Public | Process for the production of a thin film transistor having a double gate and an optical mask |
| CN1189699A (en) * | 1997-01-27 | 1998-08-05 | 三菱电机株式会社 | Field-effect transistor and its mfg. method |
| TW508828B (en) * | 1999-08-24 | 2002-11-01 | Koninkl Philips Electronics Nv | Thin-film transistors and method for producing the same |
| US9337105B1 (en) * | 2014-12-03 | 2016-05-10 | Samsung Electronics Co., Ltd. | Methods for fabricating semiconductor devices with wet etching |
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2017
- 2017-06-02 CN CN201710406570.4A patent/CN107301952B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5356824A (en) * | 1992-02-26 | 1994-10-18 | France Telecom Establissement Autonome De Droit Public | Process for the production of a thin film transistor having a double gate and an optical mask |
| CN1189699A (en) * | 1997-01-27 | 1998-08-05 | 三菱电机株式会社 | Field-effect transistor and its mfg. method |
| TW508828B (en) * | 1999-08-24 | 2002-11-01 | Koninkl Philips Electronics Nv | Thin-film transistors and method for producing the same |
| US9337105B1 (en) * | 2014-12-03 | 2016-05-10 | Samsung Electronics Co., Ltd. | Methods for fabricating semiconductor devices with wet etching |
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| CN107301952A (en) | 2017-10-27 |
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