CN107276768A - A kind of C interface plate circuit for LEU - Google Patents
A kind of C interface plate circuit for LEU Download PDFInfo
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- CN107276768A CN107276768A CN201710516969.8A CN201710516969A CN107276768A CN 107276768 A CN107276768 A CN 107276768A CN 201710516969 A CN201710516969 A CN 201710516969A CN 107276768 A CN107276768 A CN 107276768A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/06—Answer-back mechanisms or circuits
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B61—RAILWAYS
- B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
- B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor
- B61L27/40—Handling position reports or trackside vehicle data
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B61—RAILWAYS
- B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
- B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor
- B61L27/70—Details of trackside communication
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mechanical Engineering (AREA)
- Computer Security & Cryptography (AREA)
- Train Traffic Observation, Control, And Security (AREA)
Abstract
The present invention relates to a kind of C interface plate circuit for LEU, including fpga logic processing unit, C6 signal processing units, C4 signal processing units and C1 signal processing units, described fpga logic processing unit is connected with C6 signal processing units, C4 signal processing units and C1 signal processing units respectively, and described C6 signal processing units are connected with C4 signal processing units；The message information received is converted to the corresponding control signal of C1, C6 signal correspondence hardware circuit by described fpga logic processing unit, realizes that message is sent to transponder, and realize the real-time precise acquisition of C4 signals.Compared with prior art, the present invention can safely and effectively carry out message reception, message conversion, C6 signals and the transmission of C1 signals, while C4 signals can be detected accurately in real time, judge that train passes through state.
Description
Technical field
The present invention relates to Source of Railway Communication and Signalling field, more particularly, to a kind of C interface plate electricity for LEU
Road.
Background technology
LEU (LEU) is the key equipment that variable message is transmitted in responder system, it with ground transponder,
Car antenna three constitutes point type signal transmission system so that trackside equipment can be believed with mobile unit in the transmission of spaced point position
Breath.LEU (LEU) can change the data for producing or storing no less than 256 kinds of change informations with outside control condition
Message；Possess by station ground control centre or interlock system in the data message of the middle storage of LEU (LEU)
Appearance is modified, updated；When meeting Train Approaching ground active balise simultaneously, the data that LEU (LEU) is sent
Message should keep constant requirement.
C interface plate is LEU and Balise connecting plates, is responsible for digital message information being converted to analog signal being sent to
Balise.The interface board refines function defining interface：C1 interfaces are that LEU transmits Up-link message interfaces to active balise；
C4 interfaces are that active balise has interface of the train by information to LEU transmissions；C6 interfaces are LEU electric to active balise interface
Road provides power interface.
C1 interfaces are transmission base band, and the transponder transmitting message of 1024 is carried out code conversion, is converted by LEU
For DBPL codes, sent incessantly to active balise by cable.In LEU output 120 Ω resistive loads of termination, signal amplitude
Vpp is 14V~18V.C6 interfaces provide electric energy for active beacon, and its frequency is 8.82Khz, and 170 Ω resistive loads are terminated in LEU
When its Vpp be 20V~23V sine wave.When C4 signals occur, load impedance is by the Ω of normal condition 150<Zia<300 Ω change
For Za<15 Ω, its conversion time is 200<T<350uS, Td<150uS.
C interface plate plays key effect in LEU, and it is accurate safe and efficient by ground data by C1 signals and C6 signals
It is sent in the ATP system of train, while can gather the produced C4 signals of transponder as train passes through transponder
Electric signal.Therefore, the efficient C interface plate of design safety is significant.
The content of the invention
It is an object of the present invention to overcome the above-mentioned drawbacks of the prior art and provide one kind is used for Ground Electronic
The C interface plate circuit of unit.
The purpose of the present invention can be achieved through the following technical solutions：
A kind of C interface plate circuit for LEU, it is characterised in that including fpga logic processing unit, C6
Signal processing unit, C4 signal processing units and C1 signal processing units, described fpga logic processing unit are believed with C6 respectively
Number processing unit, C4 signal processing units and the connection of C1 signal processing units, described C6 signal processing units with C4 signals
Manage unit connection；
The message information received is converted to C1, C6 signal correspondence hardware circuit pair by described fpga logic processing unit
The control signal answered, realizes that message is sent to transponder, and realize the real-time precise acquisition of C4 signals.
Described C6 signal processing units include DDS chips, I-V signals conversion circuit, the activated amplifier being sequentially connected
And transformer；
I sine wave signal amounts are produced as 8.82Khz sine wave signal generators using DDS chips, turned by I-V signals
Change circuit and activated amplifier converts the signal to V sine wave signal amounts, final signal input transformer carries out coupling with C1 signals
Close superposition output 8.82Khz energy carrier signals.
Described DDS chips use AD9851 chips.
Described C1 signal processing units are opened including C1_DBPL+ signal input parts, C1_DBPL- signal input parts, first
Close pipe combinational circuit, second switch pipe combinational circuit, the first constant-current source, the second constant-current source and transformer, described C1_DBPL+
Signal input part, first switch pipe combinational circuit, the first constant-current source and transformer are sequentially connected；Described C1_DBPL- signals are defeated
Enter end, the second constant-current source of second switch pipe combinational circuit and transformer to be sequentially connected.
Described C4 signal processing units include the simple end sampling resistor of mutual inductor and multichannel comparison circuit, and described is mutual
The simple end sampling resistor of sense coil, multichannel comparison circuit and fpga logic processing unit are sequentially connected；
C4 signals on C interface circuit are gathered by the simple end sampling resistor of mutual inductor, pass through multichannel comparison circuit level
The mode compared detects the appearance of C4 signals.
Described multichannel comparison circuit uses LM2903D chips.
Described fpga logic processing unit includes C signal core processing module, packet sending and receiving module, quantity of state and postbacks mould
Block, packet parsing module, C1 message RAM buffer areas, DBPL coding modules, C6 signal DDS configuration modules, return step on Signal Pretreatment
Module, C4 positive and inverse code parsing modules, described C signal core processing module postback mould with packet sending and receiving module, quantity of state respectively
Block, packet parsing module, C1 message RAM buffer areas, C6 signal DDS configuration modules and the connection of C4 positive and inverse codes parsing module, it is described
C1 message RAM buffer areas be connected by DBPL coding modules with C1 signal processing units, described C6 signal DDS configuration modules
It is connected with C6 signal processing units, described C4 positive and inverse codes parsing module steps on signal pre-processing module and C4 signal transactings by returning
Unit is connected.
Described C1 message RAM buffer areas are compiled provided with A areas and B areas, described C signal core processing module is divided into DBPL
Code module passes through control signal wire and realizes that taking authority exchanges, it is to avoid message is repeated erasable to cause message to be sent out in reading process
Raw mistake.
For C1 signals, first by packet parsing resume module after, it would be desirable to the packet storage of conversion is in C1 messages RAM
1~4 passage memory block of buffer area correspondence, described DBPL coding modules are provided after respective channel memory block message is encoded
C1_DBPL+/C1_DBPL- signals control C1 signal processing units.
For C4 signals, the semaphore stepped on is returned according to four tunnels, signal pre-processing module is stepped on to returning the C4 signals stepped on by returning
Carry out determining whether short circuit, open circuit and abnormality in advance；If it has, then it is permanent high or permanent low to change positive and inverse code state；If it has not,
Then represent C4 signals normal, handled to C4 positive and inverse code parsing modules；
For C6 signals, on C interface plate after electricity, automatic start C6 signal DDS configuration modules are to outside DDS chips
AD9851 is configured.
Compared with prior art, the present invention has advantages below：
1) autonomous Design is realized in LEU and proposed in C interface plate circuit, this programme based on Spartan 3E Series FPGAs
System architecture solution.
2) according to the system architecture proposed, each C signal processing module in autonomous Design FPGA.
3) innovative design part C signal hardware circuit implementation in this implementation.
The message that the present invention realizes C interface plate and ALSTOM active beacons is communicated, and can safely and effectively carry out message
Receive, message is changed, C signal is sent, while C4 signals can be detected accurately in real time, judges that train passes through state.For LEU
Middle C interface plate research and development propose one kind and possess the safe conversion implementation of feasibility high efficiency message.Ground for the country in terms of LEU
Hair provides new a solution, enriches Train Control field innovation.
Brief description of the drawings
Fig. 1 is C interface plate structured flowchart；
Fig. 2 is C6 signal processing circuit schematic diagrames；
Fig. 3 is C1 signal processing circuit schematic diagrames；
Fig. 4 is C4 signal processing circuit schematic diagrames；
Fig. 5 is FPGA internal structure schematic diagrams.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is a part of embodiment of the present invention, rather than whole embodiments.Based on this hair
Embodiment in bright, the every other reality that those of ordinary skill in the art are obtained on the premise of creative work is not made
Example is applied, should all belong to the scope of protection of the invention.
The present invention is to be realized according to SUBSET-036 European standard autonomous Designs in LEU in C interface plate circuit, this programme
Propose and be based on Spartan 3E Series FPGA system architecture solutions and innovative design part C signal hardware realization electricity
Road.
This famine proposed using XC3S500E types FPGA as C interface plate core processing unit, and in independent development FPGA
Each signal processing module, is mainly used in controlling to realize that C1, C6 signal correspondence hardware circuit are converted to the message information received
Analog signal is sent to Balise, realizes the real-time collection of C4 signals and sends the signal collected to S interface boards.
As shown in figure 1, a kind of C interface plate circuit for LEU, including fpga logic processing unit 1, C6
Signal processing unit 2, C4 signal processing units 3 and C1 signal processing units 4, described fpga logic processing unit respectively with C6
Signal processing unit, C4 signal processing units and the connection of C1 signal processing units, described C6 signal processing units and C4 signals
Processing unit is connected；
Described fpga logic processing unit provides corresponding control signal and gives C1, C6 signal correspondence hardware circuit, will receive
To message information be converted to analog signal and be sent to transponder, and realize the real-time precise acquisition of C4 signals.
Pass through each signal transacting mould of independent development in the present invention by main logic processor of one piece of XC3S500E types FPGA
Block, realizes that message data is received and dispatched, realizes C1 signal four-way DBPL high efficient codings, realize and C6 signaling modules are configured, realize C4
Signal is precisely gathered.
As shown in Fig. 2 described C6 signal processing units 2 include DDS chips 21, the I-V signals conversion electricity being sequentially connected
Road 22, activated amplifier 23 and transformer 24；
I sine wave signal amounts are produced as 8.82Khz sine wave signal generators using DDS chips, turned by I-V signals
Change circuit and activated amplifier converts the signal to V sine wave signal amounts, final signal input transformer carries out coupling with C1 signals
Close superposition output 8.82Khz energy carrier signals.Described DDS chips use AD9851 chips.
As shown in figure 3, described C1 signal processing units 3 include C1_DBPL+ signal input parts 31, C1_DBPL- signals
Input 32, first switch pipe combinational circuit 33, second switch pipe combinational circuit 34, the first constant-current source 35, the second constant-current source 36
And transformer, described C1_DBPL+ signal input parts, first switch pipe combinational circuit, the first constant-current source and transformer connect successively
Connect；Described C1_DBPL- signal input parts, the second constant-current source of second switch pipe combinational circuit and transformer is sequentially connected.
C1 signal processing units, directly receive the C1_DBPL+/C1_DBPL- signals that FPGA is provided, are driven by signal wire
Device controls two metal-oxide-semiconductors to constitute C1 signal generator modules with mutual inductor.Constant-current source is built on two push-and-pull branch roads first, is led to
Cross and change the impedance value of branch road to change the simple terminal voltage of mutual inductor.
As shown in figure 4, described C4 signal processing units 4 include the simple end sampling resistor 41 of mutual inductor and multichannel compares
Circuit 42, the simple end sampling resistor 41 of described mutual inductor, multichannel comparison circuit 42 and fpga logic processing unit 1 connect successively
Connect；
C4 signals (200 on C interface circuit are gathered by the simple end sampling resistor of mutual inductor<T<350uS), multichannel is passed through
The mode that comparison circuit level compares detects the appearance of C4 signals.
Described multichannel comparison circuit uses LM2903D chips.
As shown in figure 5, described fpga logic processing unit 1 includes C signal core processing module 11, packet sending and receiving module
12nd, quantity of state postbacks module 13, packet parsing module 14, C1 message RAM buffer areas 15, DBPL coding modules 16, C6 signals DDS
Configuration module 17, return step on signal pre-processing module 18, C4 positive and inverse codes parsing module 19,1 point of described C signal core processing module
Module 13, packet parsing module 14, C1 message RAM buffer areas 15, C6 signals are not postbacked with packet sending and receiving module 12, quantity of state
DDS configuration modules 17 and C4 positive and inverse codes parsing module 19 are connected, and described C1 message RAM buffer areas 15 pass through DBPL coding modules
16 are connected with C1 signal processing units, and described C6 signal DDS configuration modules 17 are connected with C6 signal processing units, described C4
Positive and inverse code parsing module 19 is stepped on signal pre-processing module 18 and is connected with C4 signal processing units by returning.
The control module of FPGA processing unit Independent Development Design each processing units.The serial data of indoor design two-way 232
Transceiver interface module, realizes that message is received, another road realizes that monitor state amount is postbacked all the way.The present invention constructs four in FPGA
Passage message conversion hardware structure, design realizes internal each C signal processing module, realizes that highly effective and safe message is changed.
Described C1 message RAM buffer areas are compiled provided with A areas and B areas, described C signal core processing module is divided into DBPL
Code module passes through control signal wire and realizes that taking authority exchanges, it is to avoid message is repeated erasable to cause message to be sent out in reading process
Raw mistake.
For C1 signals, first by packet parsing resume module after, it would be desirable to the packet storage of conversion is in C1 messages RAM
1~4 passage memory block of buffer area correspondence, described DBPL coding modules are provided after respective channel memory block message is encoded
C1_DBPL+/C1_DBPL- signals control C1 signal processing units.
For C4 signals, the semaphore stepped on is returned according to four tunnels, signal pre-processing module is stepped on to returning the C4 signals stepped on by returning
Carry out determining whether short circuit, open circuit and abnormality in advance；If it has, then it is permanent high or permanent low to change positive and inverse code state；If it has not,
Then represent C4 signals normal, handled to C4 positive and inverse code parsing modules；
For C6 signals, on C interface plate after electricity, automatic start C6 signal DDS configuration modules are to outside DDS chips
AD9851 is configured.
The message that the present invention realizes C interface plate and ALSTOM active beacons is communicated, and can safely and effectively carry out message
Receive, message is changed, C signal is sent, while C4 signals can be detected accurately in real time, judges that train passes through state.For LEU
Middle C interface plate research and development propose one kind and possess the safe conversion implementation of feasibility high efficiency message.Ground for the country in terms of LEU
Hair provides new a solution, enriches Train Control field innovation.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, various equivalent modifications can be readily occurred in or replaced
Change, these modifications or substitutions should be all included within the scope of the present invention.Therefore, protection scope of the present invention should be with right
It is required that protection domain be defined.
Claims (10)
1. a kind of C interface plate circuit for LEU, it is characterised in that believe including fpga logic processing unit, C6
Number processing unit, C4 signal processing units and C1 signal processing units, described fpga logic processing unit respectively with C6 signals
Processing unit, C4 signal processing units and the connection of C1 signal processing units, described C6 signal processing units and C4 signal transactings
Unit is connected；
It is corresponding that the message information received is converted to C1, C6 signal correspondence hardware circuit by described fpga logic processing unit
Control signal, realizes that message is sent to transponder, and realize the real-time precise acquisition of C4 signals.
2. a kind of C interface plate circuit for LEU according to claim 1, it is characterised in that described
C6 signal processing units include DDS chips, I-V signals conversion circuit, activated amplifier and the transformer being sequentially connected；
I sine wave signal amounts are produced as 8.82Khz sine wave signal generators using DDS chips, electricity is converted by I-V signals
Road and activated amplifier convert the signal to V sine wave signal amounts, and final signal input transformer with C1 signals couple and folded
Plus output 8.82Khz energy carrier signals.
3. a kind of C interface plate circuit for LEU according to claim 2, it is characterised in that described
DDS chips use AD9851 chips.
4. a kind of C interface plate circuit for LEU according to claim 1, it is characterised in that described
C1 signal processing units include C1_DBPL+ signal input parts, C1_DBPL- signal input parts, first switch pipe combinational circuit, the
Two switching tube combinational circuits, the first constant-current source, the second constant-current source and transformer, described C1_DBPL+ signal input parts, first
Switching tube combinational circuit, the first constant-current source and transformer are sequentially connected；Described C1_DBPL- signal input parts, second switch pipe
The constant-current source of combinational circuit second and transformer are sequentially connected.
5. a kind of C interface plate circuit for LEU according to claim 1, it is characterised in that described
C4 signal processing units include the simple end sampling resistor of mutual inductor and multichannel comparison circuit, and the simple end of described mutual inductor is adopted
Sample resistance, multichannel comparison circuit and fpga logic processing unit are sequentially connected；
C4 signals on C interface circuit are gathered by the simple end sampling resistor of mutual inductor, compared by multichannel comparison circuit level
Mode detect C4 signals appearance.
6. a kind of C interface plate circuit for LEU according to claim 5, it is characterised in that described
Multichannel comparison circuit uses LM2903D chips.
7. a kind of C interface plate circuit for LEU according to claim 1, it is characterised in that described
Fpga logic processing unit includes C signal core processing module, packet sending and receiving module, quantity of state and postbacks module, packet parsing mould
Block, C1 message RAM buffer areas, DBPL coding modules, C6 signal DDS configuration modules, return step on signal pre-processing module, C4 positive and inverse codes
Parsing module, described C signal core processing module postbacks module, packet parsing mould with packet sending and receiving module, quantity of state respectively
Block, C1 message RAM buffer areas, C6 signal DDS configuration modules and the connection of C4 positive and inverse codes parsing module, described C1 messages RAM delay
Deposit area to be connected with C1 signal processing units by DBPL coding modules, described C6 signal DDS configuration modules and C6 signal transactings
Unit is connected, and described C4 positive and inverse codes parsing module is stepped on signal pre-processing module and be connected with C4 signal processing units by returning.
8. a kind of C interface plate circuit for LEU according to claim 7, it is characterised in that described
C1 message RAM buffer areas pass through control provided with A areas and B areas, described C signal core processing module is divided into DBPL coding modules
Signal wire realizes that taking authority exchanges, it is to avoid message causes message to make a mistake in reading process by repeatedly erasable.
9. a kind of C interface plate circuit for LEU according to claim 7, it is characterised in that for C1
Signal, first by packet parsing resume module after, it would be desirable to the packet storage of conversion C1 message RAM buffer areas correspondence 1~4
Passage memory block, described DBPL coding modules provide C1_DBPL+/C1_ after respective channel memory block message is encoded
DBPL- signals control C1 signal processing units.
10. a kind of C interface plate circuit for LEU according to claim 7, it is characterised in that for C4
Signal, the semaphore stepped on is returned according to four tunnels, is stepped on signal pre-processing module by returning and is judged whether in advance to returning the C4 signals stepped on
For short circuit, open circuit and abnormality；If it has, then it is permanent high or permanent low to change positive and inverse code state；If it has not, then representing C4 signals just
Often, handled to C4 positive and inverse code parsing modules；
For C6 signals, on C interface plate after electricity, automatic start C6 signal DDS configuration modules are entered to outside DDS chips AD9851
Row configuration.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710516969.8A CN107276768B (en) | 2017-06-29 | 2017-06-29 | C interface board circuit for ground electronic unit |
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|---|---|---|---|
| CN201710516969.8A CN107276768B (en) | 2017-06-29 | 2017-06-29 | C interface board circuit for ground electronic unit |
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| CN107276768B CN107276768B (en) | 2023-07-11 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107804345A (en) * | 2017-10-26 | 2018-03-16 | 北京交大思诺科技股份有限公司 | A kind of configurable LEU of contact information and its implementation |
| CN107942779A (en) * | 2017-11-10 | 2018-04-20 | 北京全路通信信号研究设计院集团有限公司 | L EU processing board |
| CN108674448A (en) * | 2018-05-11 | 2018-10-19 | 北京交大思诺科技股份有限公司 | Distributing is shunt guard system |
| CN109634340A (en) * | 2018-12-19 | 2019-04-16 | 卡斯柯信号有限公司 | A kind of voltage controlled current source output circuit |
| CN109884450A (en) * | 2019-03-19 | 2019-06-14 | 卡斯柯信号有限公司 | A kind of device and method detecting transponder cable status |
| CN110336646A (en) * | 2019-07-26 | 2019-10-15 | 卡斯柯信号有限公司 | A kind of DBPL code mining device and method suitable for LEU |
| CN110928274A (en) * | 2019-12-09 | 2020-03-27 | 通号(北京)轨道工业集团有限公司轨道交通技术研究院 | Test system of LEU equipment |
| CN112653690A (en) * | 2020-12-18 | 2021-04-13 | 卡斯柯信号有限公司 | Analog demodulation circuit for acquiring message by C interface of ground electronic unit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070273470A1 (en) * | 2004-05-14 | 2007-11-29 | Maurizio Fiz | Device For Safe Data Transmission To Railway Beacons |
| CN102857366A (en) * | 2012-06-08 | 2013-01-02 | 北京和利时***工程有限公司 | Trackside electronic device for transparent transmission of information of high-speed railway responder |
| CN103475311A (en) * | 2013-09-03 | 2013-12-25 | 周健 | Special circuit for signal generation in TDLAS (Tunable Diode Laser Absorption Spectroscopy) |
| WO2017016178A1 (en) * | 2015-07-29 | 2017-02-02 | 国核自仪***工程有限公司 | Interface signal remapping method based on fpga |
| CN106560372A (en) * | 2016-07-22 | 2017-04-12 | 卡斯柯信号有限公司 | Obturation mode adaptive control system based on vehicle controller |
-
2017
- 2017-06-29 CN CN201710516969.8A patent/CN107276768B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070273470A1 (en) * | 2004-05-14 | 2007-11-29 | Maurizio Fiz | Device For Safe Data Transmission To Railway Beacons |
| CN102857366A (en) * | 2012-06-08 | 2013-01-02 | 北京和利时***工程有限公司 | Trackside electronic device for transparent transmission of information of high-speed railway responder |
| CN103475311A (en) * | 2013-09-03 | 2013-12-25 | 周健 | Special circuit for signal generation in TDLAS (Tunable Diode Laser Absorption Spectroscopy) |
| WO2017016178A1 (en) * | 2015-07-29 | 2017-02-02 | 国核自仪***工程有限公司 | Interface signal remapping method based on fpga |
| CN106560372A (en) * | 2016-07-22 | 2017-04-12 | 卡斯柯信号有限公司 | Obturation mode adaptive control system based on vehicle controller |
Non-Patent Citations (6)
| Title |
|---|
| J. -H. BAEK: "The Study on train separation control & safety braking model technology using balise for conventional lines", INTELEC 2009 - 31ST INTERNATIONAL TELECOMMUNICATIONS ENERGY CONFERENCE, INCHEON, KOREA (SOUTH), 2009, pages 1 - 4 * |
| 刘钊江等: "有源应答器C接口的设计与实现", 《铁路通信信号工程技术》 * |
| 刘钊江等: "有源应答器C接口的设计与实现", 《铁路通信信号工程技术》, no. 04, 25 August 2013 (2013-08-25), pages 2 * |
| 屈环宇;屈百达;: "一种高精度可调相差的多路正弦信号源设计", 单片机与嵌入式***应用, no. 09 * |
| 道客巴巴，SUNHONGD28: "应答器及地面电子单元（LEU）", 《道客巴巴，HTTPS://WWW.DOC88.COM/P-9903304582729.HTML》 * |
| 道客巴巴，SUNHONGD28: "应答器及地面电子单元（LEU）", 《道客巴巴，HTTPS://WWW.DOC88.COM/P-9903304582729.HTML》, 13 January 2015 (2015-01-13), pages 2 - 3 * |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107804345A (en) * | 2017-10-26 | 2018-03-16 | 北京交大思诺科技股份有限公司 | A kind of configurable LEU of contact information and its implementation |
| CN107804345B (en) * | 2017-10-26 | 2019-09-13 | 北京交大思诺科技股份有限公司 | A kind of Ground Electronics Unit and its implementation that contact information is configurable |
| CN107942779A (en) * | 2017-11-10 | 2018-04-20 | 北京全路通信信号研究设计院集团有限公司 | L EU processing board |
| CN107942779B (en) * | 2017-11-10 | 2020-10-23 | 北京全路通信信号研究设计院集团有限公司 | LEU handles board |
| CN108674448B (en) * | 2018-05-11 | 2020-06-09 | 北京交大思诺科技股份有限公司 | Distributed shunting protection system |
| CN108674448A (en) * | 2018-05-11 | 2018-10-19 | 北京交大思诺科技股份有限公司 | Distributing is shunt guard system |
| CN109634340A (en) * | 2018-12-19 | 2019-04-16 | 卡斯柯信号有限公司 | A kind of voltage controlled current source output circuit |
| CN109634340B (en) * | 2018-12-19 | 2023-10-13 | 卡斯柯信号有限公司 | Voltage-controlled constant-current source output circuit |
| CN109884450A (en) * | 2019-03-19 | 2019-06-14 | 卡斯柯信号有限公司 | A kind of device and method detecting transponder cable status |
| CN109884450B (en) * | 2019-03-19 | 2024-04-16 | 卡斯柯信号有限公司 | Device and method for detecting cable state of transponder |
| CN110336646A (en) * | 2019-07-26 | 2019-10-15 | 卡斯柯信号有限公司 | A kind of DBPL code mining device and method suitable for LEU |
| CN110928274A (en) * | 2019-12-09 | 2020-03-27 | 通号(北京)轨道工业集团有限公司轨道交通技术研究院 | Test system of LEU equipment |
| CN112653690A (en) * | 2020-12-18 | 2021-04-13 | 卡斯柯信号有限公司 | Analog demodulation circuit for acquiring message by C interface of ground electronic unit |
| CN112653690B (en) * | 2020-12-18 | 2022-07-26 | 卡斯柯信号有限公司 | Analog demodulation circuit for acquiring message by C interface of ground electronic unit |
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| CN107276768B (en) | 2023-07-11 |
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