CN107248846A - Biasing circuit, clock circuit, chip and electronic equipment - Google Patents
Biasing circuit, clock circuit, chip and electronic equipment Download PDFInfo
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- CN107248846A CN107248846A CN201710686888.2A CN201710686888A CN107248846A CN 107248846 A CN107248846 A CN 107248846A CN 201710686888 A CN201710686888 A CN 201710686888A CN 107248846 A CN107248846 A CN 107248846A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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Abstract
The present invention relates to the field of integrated circuit technologies, and in particular, to a bias circuit, a clock circuit, a chip, and an electronic device. The bias circuit includes: the operational amplifier circuit is used for inputting a reference voltage; a first current source for providing a first current; a switching circuit; a compensation circuit connected to the first node for providing a second current; the third current flowing through the zero temperature coefficient circuit is equal to the sum of the first current and the second current. Since the reference voltage is constant and the total resistance of the zero temperature coefficient circuit is not affected by the temperature but remains constant, the third current flowing through the zero temperature coefficient circuit is constant. It is apparent that it can reduce the calculation deviation with respect to the conventional art. And the compensation circuit is able to supply the second current, which obviously, through its compensation action, is able to reduce the influence of voltage fluctuations of the external power supply or disturbances of the impedance of the switch itself on the calculation of the first current.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of biasing circuit, clock circuit, chip and electronics
Equipment.
Background technology
Clock circuit has as the important module in microprocessor chip, its performance quality to microprocessor chip
Significance.
Conventional clock circuit uses RC clock circuits, and RC clock circuits are more classical because of its structure, in integrated circuits by
Extensive use.Wherein, biasing circuit is widely used in RC clock circuits, and biasing circuit is by exporting bias voltage, to cooperate with during RC
Clock circuit output clock signal.
Inventor has found that conventional clock circuit at least has problems with during the present invention is realized：Due to biasing
Each discrete component of circuit is easily influenceed by the temperature of chip circumference environment, so that the clock letter of RC clock circuits output
Number precision it is not high.
The content of the invention
One purpose of the embodiment of the present invention aims to provide a kind of biasing circuit, clock circuit, chip and electronic equipment, its
Solve the precision that conventional bias circuit has not been able to improve the clock signal of clock circuit output.
In order to solve the above technical problems, the embodiment of the present invention provides following technical scheme：
In a first aspect, the embodiment of the present invention discloses a kind of biasing circuit, the biasing circuit includes：Discharge circuit, bag
In-phase input end, inverting input and amplifier output end are included, the in-phase input end is used for input reference voltage；First electric current
Source, for providing the first electric current；On-off circuit, including switch input terminal, output switching terminal and switch control terminal, the amplifier are defeated
Go out end to be connected with the switch control terminal, the inverting input is all connected to first node with the output switching terminal, described
Switch input terminal is connected with first current source；Zero-temperature coefficient circuit, it is connected to the first node；Compensation circuit,
It is connected to the first node, for providing the second electric current；The 3rd electric current for flowing through the zero-temperature coefficient circuit is equal to institute
State the first electric current and the second electric current sum.
Alternatively, the biasing circuit also includes：Bleeder circuit, the bleeder circuit is connected to the first node, stream
The 4th electric current through the bleeder circuit is equal to first electric current and subtracts the 3rd electric current with the second electric current sum.
Alternatively, the zero-temperature coefficient circuit includes first resistor unit and second resistance unit, the first resistor
One end of unit is connected to the first node, one end of the other end of the first resistor unit and the second resistance unit
Connection, the other end ground connection of the second resistance unit, wherein, the first resistor unit includes at least one positive temperature coefficient
Resistance, the second resistance unit includes at least one negative temperature coefficient resister, or, the first resistor unit is included at least
One negative temperature coefficient resister, the second resistance unit includes at least one positive temperature coefficient resistor.
Alternatively, the compensation circuit includes 3rd resistor unit, and one end of the 3rd resistor unit is used to be connected to
External power source, the other end of the 3rd resistor unit is connected to the first node.
Alternatively, the bleeder circuit includes the 4th resistance unit and the 5th resistance unit, the 4th resistance unit
One end connects the first node, and the other end of the 4th resistance unit is connected with one end of the 5th resistance unit, institute
State the other end ground connection of the 5th resistance unit.
Alternatively, the resistance of the 4th resistance unit is adjustable.
In second aspect, the embodiment of the present invention provides a kind of clock circuit, and the clock circuit includes：Any of the above-described
Biasing circuit；First capacitor cell；First comparator, its in-phase input end is connected with first capacitor cell, anti-phase input
End is connected to the first node of the biasing circuit；Second capacitor cell；Second comparator, its in-phase input end and described second
Capacitor cell is connected, and inverting input is connected to the Section Point of the biasing circuit；Triggers circuit, including the first triggering input
End, the second triggering input and trigger output end, the first triggering input are connected with the output end of the first comparator,
The second triggering input is connected with the output end of second comparator, and the trigger output end is used to export clock letter
Number.
Alternatively, the triggers circuit includes trigger, the first phase inverter and the second phase inverter, the output of the trigger
End is connected to the input of first phase inverter, and the output end of first phase inverter is connected to the defeated of second phase inverter
Enter end, the output end of second phase inverter is used to export clock signal.
Alternatively, first capacitor cell include the second current source, first switch, second switch, the 3rd phase inverter and
First electric capacity, second current source is connected to the input of the first switch, and the output end of the first switch is connected to
Section Point, the control end of the first switch is connected to the 3rd node, the 3rd node respectively with first phase inverter
Input and the 3rd phase inverter input connection, the input of the second switch, one end of the first electric capacity and institute
The in-phase input end for stating first comparator is all connected to the Section Point, the control end of the second switch and the described 3rd anti-
The output end connection of phase device, the output end of the second switch is connected to ground terminal, the other end ground connection of first electric capacity.
Alternatively, second capacitor cell include the 3rd current source, the 3rd switch, the 4th switch, the 4th phase inverter and
Second electric capacity, the 3rd current source is connected to the input of the 3rd switch, and the output end of the 3rd switch is connected to
Fourth node, the control end of the 3rd switch is connected to the 5th node, the 5th node respectively with second phase inverter
Input and the 4th phase inverter input connection, it is described 4th switch input, one end of the second electric capacity and institute
The in-phase input end for stating the second comparator is all connected to the fourth node, the control end of the 4th switch and the described 4th anti-
The output end connection of phase device, the output end of the 4th switch is connected to ground terminal, the other end ground connection of second electric capacity.
In the third aspect, the embodiment of the present invention provides a kind of chip, and the chip includes the clock circuit of any of the above-described.
In fourth aspect, the embodiment of the present invention provides a kind of electronic equipment, and the electronic equipment includes any of the above-described
Clock circuit.
In each of the invention embodiment, because reference voltage is constant, and zero-temperature coefficient circuit all-in resistance not by
Keep constant to the influence of temperature, therefore, it is constant to flow through the 3rd electric current of zero-temperature coefficient circuit.Therefore, the first electricity
The first electric current that stream source is provided subtracts the second electric current equal to the 3rd electric current, relative to conventional art, it is clear that it can reduce calculating
Deviation.Also, compensation circuit can provide the second electric current, it is clear that by the compensating action of compensation circuit, it can reduce outside
The interference of the voltage pulsation of power supply or the impedance of switch itself and to calculate the first electric current influence.
Brief description of the drawings
One or more embodiments are illustrative by the picture in corresponding accompanying drawing, these exemplary theorys
The element with same reference numbers label is expressed as similar element in the bright restriction not constituted to embodiment, accompanying drawing, removes
Composition is not limited the non-figure having in special statement, accompanying drawing.
Fig. 1 is that the embodiment of the present invention provides a kind of theory diagram of clock circuit；
Fig. 2 is that the embodiment of the present invention provides a kind of structural representation of biasing circuit；
Fig. 3 is that another embodiment of the present invention provides a kind of structural representation of biasing circuit；
Fig. 4 is that the embodiment of the present invention provides a kind of structural representation of clock circuit；
Fig. 5 is that the embodiment of the present invention provides a kind of timing diagram of clock circuit.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, not
For limiting the present invention.
The embodiment of the present invention provides a kind of clock circuit.The clock circuit is used for all kinds of integrated chips, and it can export tool
There is the clock signal of a clock cycle, for example, it with dutycycle 50% is that high level, dutycycle 50% are that the clock signal, which is,
Low level square-wave signal.Therefore, a clock signal is made up of the level corresponding to two 1/2 clock cycle.Chip when
Under the regulation and control of clock signal, without any confusion according to writing logic normal work.The chip can be general processor, data signal
Processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), single-chip microcomputer, ARM (Acorn RISC
) or other PLDs, discrete gate or transistor logic, discrete nextport hardware component NextPort or these parts Machine
Any combinations.Further, the chip can also be any conventional processors, controller, microcontroller or state machine.Processor also may be used
To be implemented as the combination of computing device, for example, the combination of DSP and microprocessor, multi-microprocessor, one or more micro- places
Manage device combination DSP core or any other this configuration.
In certain embodiments, the chip can also constitute electronic equipment with other peripheral circuit modules, so that the electricity
Sub- equipment completes certain application function.
Referring to Fig. 1, Fig. 1, which is the embodiment of the present invention, provides a kind of theory diagram of clock circuit.As shown in figure 1, this when
Clock circuit 10 includes：Biasing circuit 11, the first capacitor cell 12, first comparator 13, the second capacitor cell 14, the second comparator
15 and triggers circuit 16.
Biasing circuit 11 provides reference voltage V ref, the in-phase input end of first comparator 13 and the in first node 11a
One capacitor cell 12 is connected, and the inverting input of first comparator 13 is connected to the first node 11a of biasing circuit 11, the second ratio
In-phase input end compared with device 15 is connected with the second capacitor cell 14, and the inverting input of the second comparator 15 is connected to biasing circuit
11 first node 11a.Triggers circuit 16 includes the first triggering input 16a, the second triggering input 16b and trigger output end
16c, the first triggering input 16a is connected with the output end of first comparator 13, the second triggering input 16b and the second comparator
15 output end connection, trigger output end 16c is used to export clock signal clk _ OUT.
First capacitor cell 12 replaces charge and discharge with the second capacitor cell 14.At first 1/2 of clock signal
In clock cycle, the first capacitor cell 12 charges, and the second capacitor cell 14 discharges, and the trigger output end 16c of triggers circuit 16 is defeated
Go out high level signal.Within the clock cycle of second 1/2 of clock signal, when the first capacitor cell 12 discharges, the second electric capacity
When unit 14 charges, the trigger output end 16c output low level signals of triggers circuit 16.Wherein, triggers circuit 16 can be by
The burrs on edges processing of one capacitor cell 12 or the voltage signal of the second capacitor cell 14 output is clean, 50% duty of accurate output
The clock signal of ratio.
Referring to Fig. 2, Fig. 2, which is the embodiment of the present invention, provides a kind of structural representation of biasing circuit.As shown in Fig. 2 should
Biasing circuit 11 includes：Discharge circuit 111, the first current source 112, on-off circuit 113, zero-temperature coefficient circuit 114 and benefit
Repay circuit 115.
Discharge circuit 111 includes in-phase input end 111a, inverting input 111b and amplifier output end 111c, discharge circuit
111 in-phase input end 111a is used for input reference voltage Vref, and the first current source 112 is used to provide the first electric current Ia.Switch
Circuit 113 includes switch input terminal 113a, output switching terminal 113b and switch control terminal 113c, amplifier output end 111c and switch
Control end 113c connections, inverting input 111b and output switching terminal 111c is all connected to first node 11a, switch input terminal
113a is connected with the first current source 112.The input end of zero-temperature coefficient circuit 114 all connects with the output end of compensation circuit 115
First node 11a is connected to, the output head grounding of zero-temperature coefficient circuit 114, the input of compensation circuit 115 is connected to external power source
VDD。
Wherein, compensation circuit 115 is used to provide the second electric current Ib, wherein, flow through the 3rd electricity of zero-temperature coefficient circuit 114
Flow Ic and be equal to the first electric current Ia and the second electric current Ib sums, that is, the first electric current Ia=Ic-Ib.
According to the short empty disconnected principle of void, the voltage residing for the in-phase input end 111a of discharge circuit 111 is equal to inverting input
Voltage residing for 111b, that is, Vref=V1, wherein, V1 is the corresponding voltages of first node 11a.
Zero-temperature coefficient circuit by the positive compensation of positive temperature coefficient resistor and the negative compensating action of negative temperature coefficient resister,
When the temperature of the surrounding environment of zero-temperature coefficient circuit 114 is raised and lowered, positive temperature coefficient electricity in zero-temperature coefficient circuit 114
The positive compensation of resistance and the negative compensation of negative temperature coefficient resister are acted on simultaneously, and counteracting makes zero-temperature coefficient electricity because of the temperature change of environment
The variable quantity of the all-in resistance on road 114, so that the all-in resistance of zero-temperature coefficient circuit 114 is constant, due to zero-temperature coefficient circuit
114 all-in resistance is constant, and (reference voltage V ref is constant, therefore V1 is not equal to V1 for the both end voltage of zero-temperature coefficient circuit 114
Become), and the all-in resistance of zero-temperature coefficient circuit 114 is not affected by the influence of temperature and keeps constant, and therefore, the 3rd electric current Ic is not
Become.Relative to conventional art, it is clear that it can reduce the deviation for calculating the first electric current Ia.Also, when external power source VDD occurs
When fluctuation or the impedance of the switch in clock circuit produce interference, because compensation circuit 115 can provide the second electric current Ib, lead to
The compensating action of overcompensation circuit 115, to a certain extent, its voltage pulsation that can reduce external power source VDD or switch
The interference of the impedance of itself and to calculate the first electric current Ia influence.
In integrated chip design field, due to being limited by the limitation of technique platform and device instrument, when biasing circuit is
The electrical parameter that other circuit modules of clock circuit are provided has not been able to realize diversified introducing, and has not been able to flexibly by adjusting
Save the electrical parameter of biasing circuit and adjust the clock frequency of clock circuit.Therefore, in certain embodiments, as shown in figure 3, partially
Circuits 11 also include bleeder circuit 116, and the input of bleeder circuit 116 is connected to first node 11a, bleeder circuit 116
Output end is connected to ground terminal.Because the voltage V1 residing for first node 11a is constant, therefore, the 4th electricity of bleeder circuit 116 is flowed through
Flow Id constant.Therefore, the 4th electric current Id is equal to the first electric current Ia and the second electric current Ib sums subtract the 3rd electric current Ic, that is,：Id
=Ia+Ib-Ic.
It is understood that the total resistance value of the bleeder circuit 116 can be with flexible configuration, it was found from above formula, when changing
When becoming the total resistance value of bleeder circuit 116, the first electric current Ia just can be adjusted, therefore, when the first electric current Ia is introduced into clock electricity
During the calculating on road, by adjusting the total resistance value of bleeder circuit 116, the clock frequency of clock circuit just can be adjusted.
In order to elaborate the embodiment of the present invention, when elaborating provided in an embodiment of the present invention with reference to Fig. 4 and Fig. 5
The operation principle of clock circuit.
As shown in figure 4, zero-temperature coefficient circuit 114 includes first resistor unit R 1 and second resistance unit R 2, the first electricity
One end of resistance unit R 1 is connected to first node 11a, the other end of first resistor unit R 1 and one end of second resistance unit R 2
Connection, the other end ground connection of second resistance unit R 2, wherein, first resistor unit R 1 is positive temperature coefficient resistor, second resistance
Unit R 2 is negative temperature coefficient resister.In certain embodiments, first resistor unit R 1 includes at least one positive temperature coefficient electricity
Resistance, second resistance unit R 2 includes at least one negative temperature coefficient resister, or, in further embodiments, first resistor list
First R1 includes at least one negative temperature coefficient resister, and second resistance unit R 2 includes at least one positive temperature coefficient resistor.
Compensation circuit 115 includes 3rd resistor unit R 3, and one end of 3rd resistor unit R 3 is used for externally connected power supply
VDD, the other end of 3rd resistor unit R 3 is connected to first node 11a.
Bleeder circuit 116 includes the 4th resistance unit R4 and the 5th resistance unit R5, and the 4th resistance unit R4 one end connects
First node 11a is met, the 4th resistance unit R4 other end is connected with the 5th resistance unit R5 one end, the 5th resistance unit R5
The other end ground connection.Wherein, the 4th resistance unit R4 is the adjustable resistance of resistance, in actual applications, the 4th resistance unit R4
The resistance set with multiple resistor taps can be regarded, different resistor taps are accessed, just can introduce different resistances.
In each above-mentioned embodiment, first resistor unit R 1, second resistance unit R 2,3rd resistor unit R the 3, the 4th
The resistance that resistance unit R4 and the 5th resistance unit R5 can be made up of some single resistant series is integrated, can also be single electricity
Resistance, the content that those skilled in the art are instructed and guided according to embodiments of the present invention all can be to first resistor unit R 1, second resistance
Unit R 2,3rd resistor unit R 3, the 4th resistance unit R4 and the 5th resistance unit R5 configure suitable resistance, to realize the present invention
The purpose of embodiment, will not be described here.
Triggers circuit 16 includes trigger 161, the first phase inverter OP1 and the second phase inverter OP2, the output of trigger 161
End is connected to the first phase inverter OP1 input, and the first phase inverter OP1 output end is connected to the second phase inverter OP2 input
End, the second phase inverter OP2 output end is used to export clock signal clk _ OUT.
First capacitor cell 12 include the second current source 121, first switch S1, second switch S2, the 3rd phase inverter OP3 and
First electric capacity C1, the second current source 121 is connected to first switch S1 input, and first switch S1 output end is connected to second
Node 11b, first switch S1 control end are connected to the 3rd node 11c, and the 3rd node 11c is respectively with the first phase inverter OP1's
Input and the 3rd phase inverter OP3 input connection, second switch S2 input, the first electric capacity C1 one end and the first ratio
In-phase input end compared with device 13 is all connected to Section Point 11b, second switch S2 control end and the 3rd phase inverter OP3 output
End connection, second switch S2 output end is connected to ground terminal, the first electric capacity C1 other end ground connection.
Second capacitor cell 14 include the 3rd current source the 141, the 3rd switch S3, the 4th switch S4, the 4th phase inverter OP4 and
Second electric capacity C2, the 3rd current source 141 is connected to the 3rd switch S3 input, and the 3rd switch S3 output end is connected to the 4th
Node 11d, the 3rd switch S3 control end is connected to the 5th node 11e, and the 5th node 11e is respectively with the second phase inverter OP2's
Input and the 4th phase inverter OP4 input connection, the 4th switch S4 input, the second electric capacity C2 one end and the second ratio
In-phase input end compared with device 15 is all connected to fourth node 11d, the 4th switch S4 control end and the 4th phase inverter OP4 output
End connection, the 4th switch S4 output end is connected to ground terminal, the second electric capacity C2 other end ground connection.
Wherein, the first electric current Ia of the first current source 112 output is I, and the second current source 121 and the 3rd current source 141 are defeated
The electric current gone out is all MI,
The operation principle of clock circuit is as follows：
Also referring to Fig. 4 and Fig. 5.Biasing circuit 11 provides voltage V1 in first node 11a, at the same time, works as CLK_A
For high level, when CLK_B is low level, S1 closures, S2 disconnects, and S3 closures, S4 disconnects.Then, the second current source 121 is first
Electric capacity C1 charges, the second electric capacity C2 electric discharges, and therefore, the RAMPA that the first electric capacity C1 voltage is as shown in Figure 5 gradually rises, and second
Electric capacity C2 voltage is biased to ground terminal.
When CLK_A is low level, CLK_B is high level.Therefore, S1 disconnects, and S2 closures, S3 disconnects, S4 closures.Then,
First electric capacity C1 discharges, the 3rd current source 141 is that the second electric capacity C2 charges, therefore, and the second electric capacity C2 voltage is as shown in Figure 5
RAMPB gradually rises, and the first electric capacity C1 voltage is biased to ground terminal.
By alternately switching the first electric capacity C1 and the second electric capacity C2 discharge and recharge, trigger 161 by first comparator 13 and
The output of second comparator 15 is handled, so that outputting standard dutycycle is 50% clock pulses.
Further, clock frequency f calculating process is as follows：
First electric current
According to formula CU=Qt, learn：MIt=CVa, Va=k*Vref.
Wherein, t is the charging interval of the first electric capacity or the second electric capacity, and C is the capacitance of the first electric capacity or the second electric capacity, Va
The both end voltage of first electric capacity or the second electric capacity, k is partial pressure coefficient.
Therefore,
Then：The clock frequency of clock circuit
Therefore, it was found from the corresponding formula first half of clock frequency, because the all-in resistance that R1 and R2 is constituted is constant, therefore,
The temperature coefficient of the clock circuit is smaller.It was found from the formula is latter half of, due to introducing external voltage VDD, itself and clock are frequently
Rate is inversely proportional, the interference of its voltage pulsation that can reduce external power source or the switch impedance of itself.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；At this
Under the thinking of invention, it can also be combined between the technical characteristic in above example or non-be the same as Example, step can be with
Realized with random order, and there are many other changes of the different aspect of the present invention as described above, for simplicity, they do not have
Have and provided in details；Although the present invention is described in detail with reference to the foregoing embodiments, the ordinary skill people of this area
Member should be understood：It can still modify to the technical scheme described in foregoing embodiments, or to which part skill
Art feature carries out equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from each reality of the application
Apply the scope of a technical scheme.
Claims (12)
1. a kind of biasing circuit, it is characterised in that including：
Discharge circuit, including in-phase input end, inverting input and amplifier output end, the in-phase input end are used for input reference
Voltage；
First current source, for providing the first electric current；
On-off circuit, including switch input terminal, output switching terminal and switch control terminal, the amplifier output end are controlled with the switch
End processed connection, the inverting input and the output switching terminal are all connected to first node, the switch input terminal with it is described
First current source is connected；
Zero-temperature coefficient circuit, it is connected to the first node；
Compensation circuit, it is connected to the first node, for providing the second electric current；
The 3rd electric current for flowing through the zero-temperature coefficient circuit is equal to first electric current and the second electric current sum.
2. biasing circuit according to claim 1, it is characterised in that the biasing circuit also includes：Bleeder circuit, it is described
Bleeder circuit is connected to the first node, and the 4th electric current for flowing through the bleeder circuit is equal to first electric current and described the
Two electric current sums subtract the 3rd electric current.
3. biasing circuit according to claim 2, it is characterised in that the zero-temperature coefficient circuit includes first resistor list
Member and second resistance unit, one end of the first resistor unit are connected to the first node, the first resistor unit
The other end is connected with one end of the second resistance unit, the other end ground connection of the second resistance unit, wherein, described first
Resistance unit includes at least one positive temperature coefficient resistor, and the second resistance unit includes at least one negative temperature coefficient electricity
Resistance, or, the first resistor unit includes at least one negative temperature coefficient resister, and the second resistance unit includes at least one
Individual positive temperature coefficient resistor.
4. biasing circuit according to claim 3, it is characterised in that the compensation circuit includes 3rd resistor unit, institute
Stating one end of 3rd resistor unit is used for externally connected power supply, and the other end of the 3rd resistor unit is connected to described first
Node.
5. biasing circuit according to claim 4, it is characterised in that the bleeder circuit includes the 4th resistance unit and the
Five resistance units, one end of the 4th resistance unit connects the first node, the other end of the 4th resistance unit with
One end connection of 5th resistance unit, the other end ground connection of the 5th resistance unit.
6. biasing circuit according to claim 5, it is characterised in that the resistance of the 4th resistance unit is adjustable.
7. a kind of clock circuit, it is characterised in that including：
Biasing circuit as described in any one of claim 1 to 6；
First capacitor cell；
First comparator, its in-phase input end is connected with first capacitor cell, and inverting input is connected to the biased electrical
The first node on road；
Second capacitor cell；
Second comparator, its in-phase input end is connected with second capacitor cell, and inverting input is connected to the biased electrical
The first node on road；
Triggers circuit, including the first triggering input, the second triggering input and trigger output end, the first triggering input
It is connected with the output end of the first comparator, the second triggering input is connected with the output end of second comparator,
The trigger output end is used to export clock signal.
8. clock circuit according to claim 7, it is characterised in that the triggers circuit includes trigger, first anti-phase
Device and the second phase inverter, the output end of the trigger are connected to the input of first phase inverter, first phase inverter
Output end be connected to the input of second phase inverter, the output end of second phase inverter is used to export clock signal.
9. clock circuit according to claim 8, it is characterised in that first capacitor cell include the second current source,
First switch, second switch, the 3rd phase inverter and the first electric capacity, second current source are connected to the input of the first switch
End, the output end of the first switch is connected to Section Point, and the control end of the first switch is connected to the 3rd node, described
3rd node is connected with the input of first phase inverter and the input of the 3rd phase inverter respectively, the second switch
Input, the in-phase input end of one end of the first electric capacity and the first comparator be all connected to the Section Point, it is described
The control end of second switch is connected with the output end of the 3rd phase inverter, and the output end of the second switch is connected to ground terminal,
The other end ground connection of first electric capacity.
10. clock circuit according to claim 9, it is characterised in that second capacitor cell include the 3rd current source,
3rd switch, the 4th switch, the 4th phase inverter and the second electric capacity, the 3rd current source are connected to the input of the 3rd switch
End, the output end of the 3rd switch is connected to fourth node, and the control end of the 3rd switch is connected to the 5th node, described
5th node is connected with the input of second phase inverter and the input of the 4th phase inverter respectively, the 4th switch
Input, the in-phase input end of one end of the second electric capacity and second comparator be all connected to the fourth node, it is described
The control end of 4th switch is connected with the output end of the 4th phase inverter, and the output end of the 4th switch is connected to ground terminal,
The other end ground connection of second electric capacity.
11. a kind of chip, it is characterised in that including the clock circuit as described in any one of claim 7 to 10.
12. a kind of electronic equipment, it is characterised in that including the clock circuit as described in any one of claim 7 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710686888.2A CN107248846A (en) | 2017-08-11 | 2017-08-11 | Biasing circuit, clock circuit, chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710686888.2A CN107248846A (en) | 2017-08-11 | 2017-08-11 | Biasing circuit, clock circuit, chip and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN107248846A true CN107248846A (en) | 2017-10-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710686888.2A Pending CN107248846A (en) | 2017-08-11 | 2017-08-11 | Biasing circuit, clock circuit, chip and electronic equipment |
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| CN (1) | CN107248846A (en) |
Cited By (4)
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| CN109150164A (en) * | 2018-08-13 | 2019-01-04 | 广州瀚辰信息科技有限公司 | Generate the chip of constant reference current |
| CN112162584A (en) * | 2020-08-31 | 2021-01-01 | 江苏东海半导体科技有限公司 | Current bias circuit with adjustable and compensable current value |
| CN112667013A (en) * | 2020-12-24 | 2021-04-16 | 上海贝岭股份有限公司 | Current comparison type clock generation circuit and chip |
| CN113346878A (en) * | 2021-06-17 | 2021-09-03 | 南京英锐创电子科技有限公司 | Clock circuit and electronic device |
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| CN112667013A (en) * | 2020-12-24 | 2021-04-16 | 上海贝岭股份有限公司 | Current comparison type clock generation circuit and chip |
| CN112667013B (en) * | 2020-12-24 | 2022-06-14 | 上海贝岭股份有限公司 | Current comparison type clock generation circuit and chip |
| CN113346878A (en) * | 2021-06-17 | 2021-09-03 | 南京英锐创电子科技有限公司 | Clock circuit and electronic device |
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