CN107240606B - Ferroelectric field effect transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a ferroelectric field effect transistor, comprising: a substrate; a channel layer formed on the substrate; a source region and a drain region formed on the channel layer, the source region and the drain region being symmetrically formed at both ends of the channel layer; a buffer layer formed on the channel layer and between the source region and the drain region; a ferroelectric gate dielectric layer formed on the buffer layer; a gate electrode formed on the ferroelectric gate dielectric layer; a source electrode formed on the source region; and a drain electrode formed on the drain region. The invention adopts beta-Ga₂O₃As a channel material, the transistor has better radiation resistance. Meanwhile, the invention also provides a preparation method of the ferroelectric field effect transistor.

Description

Ferroelectric field effect transistor and preparation method thereof

Technical Field

The invention relates to a transistor and a preparation method thereof, in particular to a ferroelectric field effect transistor and a preparation method thereof.

Background

In recent years, China develops rapidly in the field of aerospace, such as successful launching and returning of ' shenzhou ' series spacecrafts, ' big Dipper ' satellite navigation system construction, ' Chang ' e ' moon exploration engineering, implementation of ' Tiangong ' space laboratories and the like, and higher requirements are put forward for the reliability problem of long-term use of memory chips. However, since the anti-radiation reinforcement technology belongs to a highly sensitive technology in aerospace technology, almost all research institutions of aerospace major countries and large-scale microelectronic companies in the world invest a great deal of manpower and material resources in the field, and develop the radiation effect mechanism and reinforcement technology research of semiconductor materials, devices, integrated circuits and memories so as to seize strategic high points, compete for the sky right and obtain the maximum commercial benefits. A missile technology control system (MTCR) is established in Western 33 countries including American Japanese Europe, and strict control or forbidden operation is definitely performed on China by specifying an anti-radiation reinforcement and simulation test technology and the like.

Ferroelectric memories are one of the leading and research focuses of information technology. Compared with the traditional semiconductor memory, the ferroelectric memory has the characteristics of high-density information storage and quick erasing and writing, has the remarkable advantages of low voltage, low cost, low loss, small volume, irradiation resistance and the like, and has great industrialization potential. Because the storage unit of the ferroelectric memory controls the on and off states according to the polarization of the ferroelectric material, the given storage state of one unit can be changed because the polarization of the storage unit cannot be changed by radiation sources such as alpha particles, cosmic rays, heavy ions, gamma rays, X rays and the like, so that the ferroelectric memory has extremely strong radiation resistance and is particularly suitable for the application of space and aerospace technologies. The existing research shows that the ionization radiation resistance of the ferroelectric memory reaches more than 105Gy, the gamma instantaneous dose rate resistance is more than 109Gy/s, the neutron radiation resistance reaches 1015cm-2, and single-particle disturbance is avoided, while the gamma radiation damage tolerance of the traditional MOS field effect tube is only about 102 Gy.

Therefore, compared with the traditional non-volatile memory such as Flash, the ferroelectric memory adopting the ferroelectric thin film material as the storage medium has better radiation resistance. However, the ferroelectric memory includes an array of Si field effect transistors, and the radiation resistance of the ferroelectric memory is limited by the radiation resistance of the Si field effect transistors. In order to prolong the service life of the ferroelectric memory in a space radiation environment, a Si field effect transistor in the ferroelectric memory needs to be reinforced in radiation resistance, and compared with a first-generation semiconductor material Si, second-generation and third-generation semiconductor materials generally have larger atomic displacement threshold energy and forbidden bandwidth, so that the ferroelectric memory has better radiation resistance and temperature stability. Therefore, in recent years, the integration of ferroelectric thin film materials with second and third generation semiconductor materials such as GaAs, SiC, GaN, and diamond has received great attention from researchers in the ferroelectric field.

Disclosure of Invention

In view of the above, the present invention aims to overcome the above-mentioned disadvantages of the prior art and provide a ferroelectric field effect transistor with low power consumption and good radiation resistance.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a ferroelectric field effect transistor comprising:

a substrate;

a channel layer formed on the substrate;

a source region and a drain region formed on the channel layer, the source region and the drain region being symmetrically formed at both ends of the channel layer;

a buffer layer formed on the channel layer and between the source region and the drain region;

a ferroelectric gate dielectric layer formed on the buffer layer;

a gate electrode formed on the ferroelectric gate dielectric layer;

a source electrode formed on the source region;

and

a drain electrode formed on the drain region.

Preferably, the channel layer is formed of beta-Ga₂O₃And (3) material composition.

Using beta-Ga₂O₃The FeFET serving as a channel material provides guarantee for radiation hardening resistance and temperature stability improvement of the FeFET. beta-Ga 2O3 is used as a wide bandgap semiconductor material with good thermal stability and chemical stability, is expected to have very good radiation resistance, has larger bandgap width, higher Balia quality factor (BFOM) value and cheaper price than SiC and GaN, and can improve the overall radiation resistance and temperature stability of the ferroelectric thin film FeFET by using beta-Ga 2O3 as a channel material.

Preferably, the channel layer is further doped with tin, and the doping concentration of the tin is 10¹⁵～10¹⁶cm^-3。

Preferably, the thickness of the channel layer is 200nm to 300 nm.

Preferably, the source electrode includes a Ti source electrode and an Au source electrode, the Au source electrode being formed on the Ti source electrode; the drain electrode includes a Ti drain electrode and an Au drain electrode, and the Au drain electrode is formed on the Ti drain electrode.

Preferably, the substrate is composed of a silicon material or a germanium material.

Preferably, the buffer layer is an insulating layer, or the buffer layer is a double-layer structure composed of an insulating layer and a metal layer.

Preferably, the ferroelectric gate dielectric layer is made of Bi₄Ti₃O₁₂、SrBi₂Ta₂O₉、PbTiO₃、BaTiO₃、BiFeO₃At least one of La, Nd, Ce, Sr, Zr, Mn, W and Na, and Bi₄Ti₃O₁₂、SrBi₂Ta₂O₉、PbTiO₃、BaTiO₃、BiFeO₃Is doped with at least one of the formed substances, or Zr is doped with HfO₂Si doped HfO₂Al-doped HfO₂Y doped HfO₂At least one of (1).

Preferably, when the buffer layer has a double-layer structure consisting of an insulating layer and a metal, the insulating layer has a thickness of 2nm to 10nm, and the metal layer has a thickness of 50nm to 80 nm.

Preferably, the thickness of the ferroelectric gate dielectric layer is 5 nm-600 nm.

Meanwhile, the invention also provides a preparation method of the ferroelectric field effect transistor, which comprises the following steps:

(1) forming a channel layer on a substrate;

(2) forming a source electrode layer and a drain electrode layer on the channel layer formed in the step (1);

(3) performing ion implantation on the source electrode layer and the drain electrode layer in the step (2) by adopting an ion implantation process to form a source electrode region and a drain electrode region;

(4) performing activation treatment on the source region and the drain region obtained in the step (3) to obtain a source electrode and a drain electrode;

(5) depositing a buffer layer on the channel layer processed in the step (4);

(6) depositing a ferroelectric gate dielectric layer on the buffer layer in the step (5);

(7) depositing gate metal on the ferroelectric gate dielectric layer in the step (6) to obtain a gate electrode;

(8) removing the buffer layer, the ferroelectric gate dielectric layer and the gate electrode on the source region and the drain region processed in the step (7);

(9) and (5) forming a source electrode and a drain electrode on the source electrode and the drain electrode which are processed in the step (8), and obtaining the ferroelectric field effect transistor.

Preferably, in the step (1), a channel layer is epitaxially grown on the substrate by using a low-temperature solid source molecular beam epitaxy process, wherein the epitaxy temperature is 500-700 ℃, and the deposition rate is 0.6 μm/h.

Preferably, a 365nm I-line photoetching process is adopted in the steps (2) and (8). One skilled in the art can select an appropriate etch recipe as desired.

Preferably, in the step (2), the conditions of the ion implantation process are as follows: in N⁺Source region and N⁺The implantation energy of the drain region is 20-25KeV, and the dosage is 10¹⁸-10¹⁹cm^-3Si of (2)⁺Ions.

Preferably, the process of activating in step (4) is as follows: and (4) carrying out thermal annealing treatment on the source region and the drain region in the step (3) at 800-950 ℃.

The process adopted in the step (6) is a suitable film deposition process recognized in the art, and includes, but is not limited to, film deposition processes such as magnetron sputtering, pulsed laser deposition, atomic layer deposition, and the like.

Preferably, the gate metal in step (7) is at least one of TiN, TaN and Pt.

Preferably, a magnetron sputtering process is adopted in the step (10), the temperature of the magnetron sputtering process is 200-300 ℃, the thickness of Ti metal sputtered on the source electrode and the drain electrode is 20-30 nm, and the thickness of Au metal sputtered on the source electrode and the drain electrode is 100-150 nm.

Compared with the prior art, the invention has the beneficial effects that:

the invention adopts beta-Ga₂O₃As a channel material, a wide bandgap semiconductor material with good thermal stability and chemical stability is expected to have very good radiation resistance, and can reinforce the radiation resistance of a channel part.

Drawings

FIG. 1 is a cross-sectional structural view of a ferroelectric field effect transistor according to the present invention;

FIG. 2 is a flow chart of a method of fabricating a ferroelectric field effect transistor according to the present invention;

wherein, 1, a substrate; 2. a channel layer; 3. a source region; 4. a buffer layer; 5. a ferroelectric gate dielectric layer; 6. a gate electrode; 7. a drain region; 8. a Ti drain electrode; 9. an Au drain electrode; 10. a Ti source electrode; 11. and an Au source electrode.

Detailed Description

To better illustrate the objects, aspects and advantages of the present invention, the present invention will be further described with reference to the accompanying drawings and specific embodiments.

Example 1

An embodiment of the present invention relates to a ferroelectric field effect transistor, a cross-sectional structure of which is shown in fig. 1, and the ferroelectric field effect transistor includes:

a substrate 1, the substrate 1 being composed of a silicon material;

a channel layer 2 formed on a substrate 1, the channel layer 2 being formed of beta-Ga₂O₃The channel layer 2 is also doped with tin, the doping concentration of the tin is 10¹⁵cm^-3；

A source region 3 and a drain region 7 formed on the channel layer 2, the source region 3 and the drain region 7 being symmetrically formed at both ends of the channel layer 2;

a buffer layer 4 formed on the channel layer 2 and between the source region 3 and the drain region 7;

a ferroelectric gate dielectric layer 5 formed on the buffer layer 4;

a gate electrode 6 formed on the ferroelectric gate dielectric layer 5;

a source electrode formed on the source region 3, the source electrode including a Ti source electrode 10 and an Au source electrode 11, the Au source electrode 11 being formed on the Ti source electrode 10;

and

and a drain electrode formed on the drain region 7, the drain electrode including a Ti drain electrode 8 and an Au drain electrode 9, the Au drain electrode 9 being formed on the Ti drain electrode 8.

Wherein the thickness of the channel layer is 200 nm; the buffer layer is composed of an insulating layer, specifically a hafnium-based dielectric material, and the hafnium-based dielectric material is HfO₂The thickness of the buffer layer is 8 nm; the ferroelectric gate dielectric layer is made of Zr-doped HfO₂And the thickness of the ferroelectric gate dielectric layer is 5 nm.

An embodiment of the method for manufacturing a ferroelectric field effect transistor according to this embodiment includes the following steps:

step 1, epitaxial growth of beta-Ga₂O₃Layer (b):

epitaxially growing a layer of beta-Ga on a substrate by using a low-temperature solid source molecular beam epitaxy process₂O₃Layer with thickness of 200nm, epitaxial temperature of 500 deg.C, deposition rate of 0.6 μm/h, FIG. 2(a) is a schematic structural diagram of the substrate, and FIG. 2(b) is epitaxially grown beta-Ga₂O₃A schematic structure diagram after the trench;

step 2, forming an active layer by photoetching:

by means of a photolithographic process on beta-Ga₂O₃Forming a source layer, a channel and a drain layer on the layers, wherein the channel is located at beta-Ga₂O₃The source electrode layer and the drain electrode layer are respectively positioned at the two sides of the channel;

and 3, doping to form a source region and a drain region:

adopting an ion implantation process to carry out ion implantation on the source electrode layer and the drain electrode layer, wherein the implantation conditions are as follows: in N⁺Source region and N⁺The implantation energy of the type drain region is 25KeV, and the dosage is 10¹⁹cm^-3Si of (2)⁺Ions forming a source region and a drain region;

and 4, activating:

performing activation treatment on the source region and the drain region by thermal annealing at 950 ℃ for 30min to obtain the source region and the drain region, wherein fig. 2(c) is a schematic structural diagram of the source region and the drain region obtained by the activation treatment;

step 5, depositing a buffer layer:

depositing HfO with the thickness of 8nm on the active layer formed in the step 4 by utilizing an atomic layer deposition process under the environment that the temperature is 280 ℃ and the pressure is 15hPa₂Layer, forming an insulating dielectric film, FIG. 2(d) deposition of HfO₂A schematic view of the structure after insulating the dielectric film;

step 6, depositing a ferroelectric gate dielectric layer:

depositing 5nm thick ferroelectric Zr doped HfO on the insulating dielectric film formed in step 5 by using atomic layer deposition process under the conditions of 300 ℃ temperature and 20hPa pressure₂Film, FIG. 2(e) is a schematic view of the deposition of ferroelectric Zr doped HfO₂A schematic structure diagram after film formation;

step 7, depositing a gate electrode:

by utilizing a magnetron sputtering process, under the conditions that the temperature is 300 ℃, the pressure is 0.32Pa and the sputtering power is 115W, the ferroelectric Zr is doped with HfO₂Growing 120nm TiN on the film, and FIG. 2(f) is a schematic structural diagram after depositing gate metal TiN;

step 8, photoetching and etching:

forming source/drain electrode windows by photolithography, and etching the buffer layer/ferroelectric HfO on the source and drain₂TiN, FIG. 2(g) etching buffer layer HfO over source and drain₂Ferroelectric HfO₂A schematic structure diagram after TiN is finished;

step 9, depositing a source electrode and a drain electrode:

and (c) depositing Au/Ti source and drain electrodes with the thickness of 20nm/100nm in the source and drain electrode window formed in the step (8) by utilizing a magnetron sputtering process under the conditions that the temperature is 260 ℃, the pressure is 0.12Pa and the sputtering power is 200W, and then completing the manufacture of the transistor by stripping, wherein fig. 2(h) is a structural schematic diagram of the completed transistor.

Example 2

An embodiment of the present invention relates to a ferroelectric field effect transistor, a cross-sectional structure of which is shown in fig. 1, and the ferroelectric field effect transistor includes:

a substrate 1, the substrate 1 being composed of a germanium material;

a channel layer 2 formed on a substrate 1, the channel layer 2 being formed of beta-Ga₂O₃The channel layer 2 is also doped with tin, the doping concentration of the tin is 10¹⁶cm^-3；

A source region 3 and a drain region 7 formed on the channel layer 2, the source region 3 and the drain region 7 being symmetrically formed at both ends of the channel layer 2;

a buffer layer 4 formed on the channel layer 2 and between the source region 3 and the drain region 7;

a ferroelectric gate dielectric layer 5 formed on the buffer layer 4;

a gate electrode 6 formed on the ferroelectric gate dielectric layer 5;

a source electrode formed on the source region 3, the source electrode including a Ti source electrode 10 and an Au source electrode 11, the Au source electrode 11 being formed on the Ti source electrode 10;

and

and a drain electrode formed on the drain region 7, the drain electrode including a Ti drain electrode 8 and an Au drain electrode 9, the Au drain electrode 9 being formed on the Ti drain electrode 8.

Wherein the thickness of the channel layer is 300 nm; the buffer layer is composed of a double-layer structure consisting of an insulating layer and a metal layer, the insulating layer is composed of a hafnium-based dielectric material, the metal layer is TiN, and the hafnium-based dielectric material is Al₂O₃The thickness of the insulating layer is 2nm, and the thickness of the metal TiN is 50 nm; the ferroelectric gate dielectric layer is made of SrBi₂Ta₂O₉And the thickness of the ferroelectric gate dielectric layer is 100 nm.

An embodiment of the method for manufacturing a ferroelectric field effect transistor according to this embodiment includes the following steps:

step 1, epitaxial growth of beta-Ga₂O₃Layer (b):

epitaxially growing a layer of beta-Ga on a substrate by using a low-temperature solid source molecular beam epitaxy process₂O₃A layer having a thickness of 300nm, an epitaxial temperature of 700 deg.C and a deposition rate of 0.6 μm/h, wherein FIG. 2(a) is a schematic view of the structure of the substrate, and FIG. 2(b) is epitaxially grown beta-Ga₂O₃A schematic structure diagram after the trench;

step 2, forming an active layer by photoetching:

by means of a photolithographic process on beta-Ga₂O₃Forming a source layer, a channel and a drain layer on the layers, wherein the channel is located at beta-Ga₂O₃The source electrode layer and the drain electrode layer are respectively positioned at the two sides of the channel;

and 3, doping to form a source region and a drain region:

adopting an ion implantation process to carry out ion implantation on the source electrode layer and the drain electrode layer, wherein the implantation conditions are as follows: in N⁺Source region and N⁺The implantation energy of the type drain region is 20KeV, and the dosage is 10¹⁸cm^-3Si of (2)⁺Ions forming a source region and a drain region;

and 4, activating:

performing activation treatment on the source region and the drain region by thermal annealing at 800 ℃ for 30min to obtain the source region and the drain region, wherein fig. 2(c) is a schematic structural diagram of the source region and the drain region obtained by the activation treatment;

step 5, depositing a buffer layer:

depositing Al with a thickness of 2nm on the active layer formed in step 4 by using an atomic layer deposition process under the conditions of a temperature of 260 ℃ and a pressure of 12hPa₂O₃Forming an insulating layer film, and forming an insulating layer film Al on the insulating layer film Al by utilizing a magnetron sputtering process under the conditions that the temperature is 300 ℃, the pressure is 0.32Pa and the sputtering power is 115W₂O₃Growing 50nm TiN, and FIG. 2(d) is a schematic structural diagram after depositing a buffer layer;

step 6, depositing a ferroelectric gate dielectric layer:

depositing 100nm ferroelectric SrBi on the insulating dielectric film formed in step 5 by using an atomic layer deposition process under the conditions of 280 ℃ of temperature and 15hPa of pressure₂Ta₂O₉Film, FIG. 2(e) deposition of ferroelectric SrBi₂Ta₂O₉A schematic structure diagram after film formation;

step 7, depositing a gate electrode:

utilizing magnetron sputtering technology, under the conditions of 300 ℃ of temperature, 0.32Pa of pressure and 115W of sputtering power, under the conditions of ferroelectric SrBi₂Ta₂O₉Growing 120nm TiN on the film, and FIG. 2(f) is a schematic structural diagram after depositing gate metal TiN;

step 8, photoetching and etching:

forming source and drain electrode windows by photoetching, and etching buffer layers/SrBi on the source electrode and the drain electrode₂Ta₂O₉TiN, FIG. 2(g) is etching buffer layer Al on source and drain₂O₃/SrBi₂Ta₂O₉A schematic structure diagram after TiN is finished;

step 9, depositing a source electrode and a drain electrode:

and (c) depositing Au/Ti source and drain electrodes with the thickness of 25nm/125nm in the source and drain electrode window formed in the step (8) by utilizing a magnetron sputtering process under the conditions that the temperature is 200 ℃, the pressure is 0.12Pa and the sputtering power is 200W, and then completing the manufacture of the transistor by stripping, wherein fig. 2(h) is a structural schematic diagram of the completed transistor.

Example 3

An embodiment of the present invention relates to a ferroelectric field effect transistor, a cross-sectional structure of which is shown in fig. 1, and the ferroelectric field effect transistor includes:

a substrate 1, the substrate 1 being composed of a silicon material;

a channel layer 2 formed on a substrate 1, the channel layer 2 being formed of beta-Ga₂O₃The channel layer 2 is also doped with tin, the doping concentration of the tin is 10¹⁵cm^-3；

A source region 3 and a drain region 7 formed on the channel layer 2, the source region 3 and the drain region 7 being symmetrically formed at both ends of the channel layer 2;

a buffer layer 4 formed on the channel layer 2 and between the source region 3 and the drain region 7;

a ferroelectric gate dielectric layer 5 formed on the buffer layer 4;

a gate electrode 6 formed on the ferroelectric gate dielectric layer 5;

a source electrode formed on the source region 3, the source electrode including a Ti source electrode 10 and an Au source electrode 11, the Au source electrode 11 being formed on the Ti source electrode 10;

and

and a drain electrode formed on the drain region 7, the drain electrode including a Ti drain electrode 8 and an Au drain electrode 9, the Au drain electrode 9 being formed on the Ti drain electrode 8.

Wherein the thickness of the channel layer is 250 nm; the buffer layer is composed of a double-layer structure composed of an insulating layer and a metal layer, the insulating layer is composed of a hafnium-based dielectric material, the metal layer is TiN, the hafnium-based dielectric material is HfAlO, the thickness of the insulating layer is 10nm, and the thickness of the metal TiN is 80 nm; the ferroelectric gate dielectric layer is made of Zr doped PbTiO₃The thickness of the ferroelectric gate dielectric layer is 280 nm.

An embodiment of the method for manufacturing a ferroelectric field effect transistor according to this embodiment includes the following steps:

step 1, epitaxial growth of beta-Ga₂O₃Layer (b):

epitaxially growing a layer of beta-Ga on a substrate by using a low-temperature solid source molecular beam epitaxy process₂O₃A layer with a thickness of 250nm, an epitaxial temperature of 600 ℃ and a deposition rate of 0.6 [ mu ] m/h, wherein FIG. 2(a) is a schematic view of the structure of the substrate, and FIG. 2(b) is epitaxially grown beta-Ga₂O₃A schematic structure diagram after the trench;

step 2, forming an active layer by photoetching:

by means of a photolithographic process on beta-Ga₂O₃Forming a source layer, a channel and a drain layer on the layers, wherein the channel is located at beta-Ga₂O₃The source electrode layer and the drain electrode layer are respectively positioned at the two sides of the channel;

and 3, doping to form a source region and a drain region:

adopting an ion implantation process to carry out ion implantation on the source electrode layer and the drain electrode layer, wherein the implantation conditions are as follows: in N⁺Source region and N⁺The implantation energy of the type drain region is 25KeV, and the dosage is 10¹⁹cm^-3Si of (2)⁺Ions forming a source region and a drain region;

and 4, activating:

performing activation treatment on the source region and the drain region by thermal annealing at 880 ℃ for 30min to obtain the source region and the drain region, wherein fig. 2(c) is a schematic structural diagram of the source region and the drain region obtained by the activation treatment;

step 5, depositing a buffer layer:

depositing a HfAlO layer with the thickness of 6nm on the active layer formed in the step 4 by utilizing an atomic layer deposition process under the environment that the temperature is 260 ℃ and the pressure is 12hPa to form an insulating dielectric film, wherein the figure 2(d) is a structural schematic diagram after the HfAlO insulating dielectric film is deposited;

step 6, depositing a ferroelectric gate dielectric layer:

the energy density of the laser pulse is 2J/cm by using a pulsed laser deposition process and single pulse energy of 300mJ²Depositing Pb (Zr) with a thickness of 280nm on HfAlO formed in step 5 at a laser repetition frequency of 10Hz and a deposition temperature of 700 ℃ under a deposition oxygen pressure of 100mTorr_0.53Ti_0.47)O₃Ferroelectric thin film, FIG. 2(e) for depositing Pb (Zr)_0.53Ti_0.47)O₃A schematic structure diagram behind the ferroelectric film;

step 7, depositing a gate electrode:

using ultra-high vacuum electron beam process to prepare the catalyst in Pb (Zr)_0.53Ti_0.47)O₃Growing 80nm TaN on the ferroelectric film, and FIG. 2(f) is a schematic structural diagram after depositing gate metal TaN;

step 8, photoetching and etching:

forming source and drain electrode windows by photoetching, and etching buffer layers HfAlO/Pb (Zr) on the source electrode and the drain electrode_0.53Ti_0.47)O₃FIG. 2(g) shows etching of buffer layer HfAlO/Pb (Zr) on source and drain_0.53Ti_0.47)O₃A structural schematic diagram after TaN completion;

step 9, depositing a source electrode and a drain electrode:

and (3) depositing Au/Ti source and drain electrodes with the thickness of 30nm/150nm in the source and drain electrode window formed in the step (8) by utilizing a magnetron sputtering process under the conditions that the temperature is 300 ℃, the pressure is 0.12Pa and the sputtering power is 200W, and then completing the manufacture of the transistor by stripping, wherein fig. 2(h) is a structural schematic diagram of the completed transistor.

Example 4

An embodiment of the present invention relates to a ferroelectric field effect transistor, a cross-sectional structure of which is shown in fig. 1, and the ferroelectric field effect transistor includes:

a substrate 1, the substrate 1 being composed of a germanium material;

a channel layer 2 formed on a substrate 1, the channel layer 2 being formed of beta-Ga₂O₃The channel layer 2 is also doped with tin, the doping concentration of the tin is 10¹⁶cm^-3；

A source region 3 and a drain region 7 formed on the channel layer 2, the source region 3 and the drain region 7 being symmetrically formed at both ends of the channel layer 2;

a buffer layer 4 formed on the channel layer 2 and between the source region 3 and the drain region 7;

a ferroelectric gate dielectric layer 5 formed on the buffer layer 4;

a gate electrode 6 formed on the ferroelectric gate dielectric layer 5;

a source electrode formed on the source region 3, the source electrode including a Ti source electrode 10 and an Au source electrode 11, the Au source electrode 11 being formed on the Ti source electrode 10;

and

and a drain electrode formed on the drain region 7, the drain electrode including a Ti drain electrode 8 and an Au drain electrode 9, the Au drain electrode 9 being formed on the Ti drain electrode 8.

Wherein the thickness of the channel layer is 250 nm; the buffer layer is made of a hafnium-based dielectric material, the hafnium-based dielectric material is HfN, and the thickness of the buffer layer is 10 nm; the ferroelectric gate dielectric layer is made of Nd and Bi₄Ti₃O₁₂And doping the formed substance, wherein the thickness of the ferroelectric gate dielectric layer is 600 nm.

An embodiment of the method for manufacturing a ferroelectric field effect transistor according to this embodiment includes the following steps:

step 1, step AGrowing of beta-Ga₂O₃Layer (b):

epitaxially growing a layer of beta-Ga on a substrate by using a low-temperature solid source molecular beam epitaxy process₂O₃A layer with a thickness of 250nm, an epitaxial temperature of 500 ℃ and a deposition rate of 0.6 [ mu ] m/h, wherein FIG. 2(a) is a schematic view of the structure of the substrate, and FIG. 2(b) is epitaxially grown beta-Ga₂O₃A schematic structure diagram after the trench;

step 2, forming an active layer by photoetching:

by means of a photolithographic process on beta-Ga₂O₃Forming a source layer, a channel and a drain layer on the layers, wherein the channel is located at beta-Ga₂O₃The source electrode layer and the drain electrode layer are respectively positioned at the two sides of the channel;

and 3, doping to form a source region and a drain region:

adopting an ion implantation process to carry out ion implantation on the source electrode layer and the drain electrode layer, wherein the implantation conditions are as follows: in N⁺Source region and N⁺The implantation energy of the type drain region is 25KeV, and the dosage is 10¹⁹cm^-3Si of (2)⁺Ions forming a source region and a drain region;

and 4, activating:

performing activation treatment on the source region and the drain region by thermal annealing at 950 ℃ for 30min to obtain the source region and the drain region, wherein fig. 2(c) is a schematic structural diagram of the source region and the drain region obtained by the activation treatment;

step 5, depositing a buffer layer:

depositing HfO with a thickness of 10nm on the active layer formed in step 4 by an atomic layer deposition process under the conditions of a temperature of 280 ℃ and a pressure of 12hPa₂Layer, forming an insulating dielectric film, FIG. 2(d) deposition of HfO₂A schematic structural diagram behind the buffer layer film;

step 6, depositing a ferroelectric gate dielectric layer:

the energy density of the laser pulse is 2.5J/cm by using a pulsed laser deposition process and single pulse energy of 320mJ²Laser repetition frequency of 12Hz, deposition oxygen pressure of 200mTorr, deposition temperature of 750 ℃, and forming an insulating dielectric film HfO in step 5₂Upper depositionBi with a thickness of 320nm_3.15Nd_0.85Ti₃O₁₂Ferroelectric thin film, FIG. 2(e) is deposition of Bi_3.15Nd_0.85Ti₃O₁₂A schematic structure diagram behind the ferroelectric film;

step 7, depositing a gate electrode:

using an ultra-high vacuum electron beam process in Bi_3.15Nd_0.85Ti₃O₁₂80nm Pt grows on the ferroelectric film, and FIG. 2(f) is a schematic structural diagram after gate metal Pt is deposited;

step 8, photoetching and etching:

forming source and drain electrode windows by photoetching, and etching the buffer layer HfO on the source electrode and the drain electrode₂/Bi_3.15Nd_0.85Ti₃O₁₂Pt, FIG. 2(g) for etching buffer layer HfO on source and drain₂/Bi_3.15Nd_0.85Ti₃O₁₂Schematic structure after Pt is finished;

step 9, depositing a source electrode and a drain electrode:

and (c) depositing Au/Ti source and drain electrodes with the thickness of 20nm/100nm in the source and drain electrode window formed in the step (8) by utilizing a magnetron sputtering process under the conditions that the temperature is 260 ℃, the pressure is 0.12Pa and the sputtering power is 200W, and then completing the manufacture of the transistor by stripping, wherein fig. 2(h) is a structural schematic diagram of the completed transistor.

Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the protection scope of the present invention, and although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims (7)

1. A ferroelectric field effect transistor, comprising:

a substrate;

a channel layer formed on the substrate;

a source region and a drain region formed on the channel layer, the source region and the drain region being symmetrically formed at both ends of the channel layer;

a buffer layer formed on the channel layer and between the source region and the drain region;

a ferroelectric gate dielectric layer formed on the buffer layer, the ferroelectric gate dielectric layer being made of Bi₄Ti₃O₁₂、SrBi₂Ta₂O₉、PbTiO₃、BaTiO₃、BiFeO₃At least one of La, Nd, Ce, Sr, Zr, Mn, W and Na, and Bi₄Ti₃O₁₂、SrBi₂Ta₂O₉、PbTiO₃、BaTiO₃、BiFeO₃Is doped with at least one of the formed substances, or Zr is doped with HfO₂Si doped HfO₂Al-doped HfO₂Y doped HfO₂At least one of;

a gate electrode formed on the ferroelectric gate dielectric layer;

a source electrode formed on the source region;

and

a drain electrode formed on the drain region;

the channel layer is formed of beta-Ga₂O₃Material composition; the channel layer is doped with tin or silicon, and the doping concentration of the tin or the silicon is 10¹⁵～10¹⁶cm^-3；

The preparation method of the ferroelectric field effect transistor comprises the following steps:

(1) forming a channel layer on a substrate;

(2) forming a source electrode layer and a drain electrode layer on the channel layer formed in the step (1);

(3) performing ion implantation on the source electrode layer and the drain electrode layer in the step (2) by adopting an ion implantation process to form a source electrode region and a drain electrode region; the conditions of the ion implantation process are as follows: in N⁺Source region and N⁺The implantation energy of the drain region is 20-25KeV, and the dosage is 10¹⁸-10¹⁹cm^-3Si of (2)⁺Ions;

(4) performing activation treatment on the source region and the drain region obtained in the step (3) to obtain a source electrode and a drain electrode;

(5) depositing a buffer layer on the channel layer processed in the step (4);

(6) depositing a ferroelectric gate dielectric layer on the buffer layer in the step (5);

(7) depositing gate metal on the ferroelectric gate dielectric layer in the step (6) to obtain a gate electrode;

(8) removing the buffer layer, the ferroelectric gate dielectric layer and the gate electrode on the source region and the drain region processed in the step (7);

(9) and (5) forming a source electrode and a drain electrode on the source electrode and the drain electrode which are processed in the step (8), and obtaining the ferroelectric field effect transistor.

2. A ferroelectric field effect transistor as in claim 1, wherein the channel layer has a thickness of 200nm to 300 nm.

3. The ferroelectric field effect transistor as claimed in claim 1, wherein the source electrode comprises a Ti source electrode and an Au source electrode, the Au source electrode being formed on the Ti source electrode; the drain electrode includes a Ti drain electrode and an Au drain electrode, and the Au drain electrode is formed on the Ti drain electrode.

4. A ferroelectric field effect transistor as in claim 1, wherein the substrate is comprised of a silicon material or a germanium material.

5. A ferroelectric field effect transistor according to claim 1, wherein the buffer layer is an insulating layer, or the buffer layer is a double-layer structure of an insulating layer and a metal layer.

6. A ferroelectric field effect transistor according to claim 1, wherein when the buffer layer has a double-layer structure of an insulating layer and a metal layer, the insulating layer has a thickness of 2nm to 10nm, and the metal layer has a thickness of 50nm to 80 nm.

7. A method of manufacturing a ferroelectric field effect transistor as claimed in any one of claims 1 to 6, comprising the steps of:

(1) forming a channel layer on a substrate;

(2) forming a source electrode layer and a drain electrode layer on the channel layer formed in the step (1);

(3) performing ion implantation on the source electrode layer and the drain electrode layer in the step (2) by adopting an ion implantation process to form a source electrode region and a drain electrode region; the conditions of the ion implantation process are as follows: in N⁺Source region and N⁺The implantation energy of the drain region is 20-25KeV, and the dosage is 10¹⁸-10¹⁹cm^-3Si of (2)⁺Ions;

(4) performing activation treatment on the source region and the drain region obtained in the step (3) to obtain a source electrode and a drain electrode;

(5) depositing a buffer layer on the channel layer processed in the step (4);

(6) depositing a ferroelectric gate dielectric layer on the buffer layer in the step (5);

(7) depositing gate metal on the ferroelectric gate dielectric layer in the step (6) to obtain a gate electrode;

(8) removing the buffer layer, the ferroelectric gate dielectric layer and the gate electrode on the source region and the drain region processed in the step (7);

(9) and (5) forming a source electrode and a drain electrode on the source electrode and the drain electrode which are processed in the step (8), and obtaining the ferroelectric field effect transistor.

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