CN107239376B - Automatic debugging method and device for server interconnection chip - Google Patents
Automatic debugging method and device for server interconnection chip Download PDFInfo
- Publication number
- CN107239376B CN107239376B CN201710485192.3A CN201710485192A CN107239376B CN 107239376 B CN107239376 B CN 107239376B CN 201710485192 A CN201710485192 A CN 201710485192A CN 107239376 B CN107239376 B CN 107239376B
- Authority
- CN
- China
- Prior art keywords
- cpu
- configuration parameter
- debugged
- chip
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004891 communication Methods 0.000 claims abstract description 26
- 238000012795 verification Methods 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 13
- 230000001960 triggered effect Effects 0.000 claims 2
- 238000012545 processing Methods 0.000 description 10
- 239000002184 metal Substances 0.000 description 8
- 230000002349 favourable effect Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention provides an automatic debugging method and device for a server interconnection chip, wherein the method comprises the following steps: presetting configuration parameters of at least one CPU; determining a CPU corresponding to an interconnection chip to be debugged; debugging the determined CPU according to the configuration parameters of the at least one CPU; controlling the debugged CPU to establish communication interconnection with the interconnection chip to be debugged; and adjusting the working mode of the interconnection chip to be debugged according to the configuration parameters corresponding to the debugged CPU. The scheme can improve the debugging efficiency of the interconnection chip.
Description
Technical Field
The invention relates to the technical field of computers, in particular to an automatic debugging method and device for a server interconnection chip.
Background
With the development of computer technology, people have higher and higher performance requirements on servers. The interconnection chip is increasingly widely used as a core chip of a shared main memory system of a multi-path processor. In order to ensure the service performance of the interconnection chip, the interconnection chip needs to be debugged and verified before use, wherein the correct establishment of the debugging environment is the guarantee for chip verification.
At present, when a debugging environment of an interconnection chip is built, a manual mode is mainly adopted, namely, a worker firstly adjusts configuration parameters of a CPU of a server to which the interconnection chip belongs, the CPU is debugged, and then the working mode of the interconnection chip is adjusted according to the configuration parameters of the CPU, so that the configuration parameters of the CPU are matched with the working mode of the interconnection chip, and the building of the debugging environment is completed.
Because the configuration parameters of the CPU and the types of the working modes of the interconnected chip are more, the efficiency of matching in a manual mode is lower, and the debugging efficiency of the interconnected chip is lower.
Disclosure of Invention
The embodiment of the invention provides an automatic debugging method and device for a server interconnection chip, which can improve the debugging efficiency of the interconnection chip.
In a first aspect, an embodiment of the present invention provides an automated debugging method for a server interconnection chip, including:
presetting configuration parameters of at least one CPU;
determining a CPU corresponding to an interconnection chip to be debugged;
debugging the determined CPU according to the configuration parameters of the at least one CPU;
controlling the debugged CPU to establish communication interconnection with the interconnection chip to be debugged;
and adjusting the working mode of the interconnection chip to be debugged according to the configuration parameters corresponding to the debugged CPU.
Preferably, the first and second electrodes are formed of a metal,
further comprising: presetting the working time length corresponding to the configuration parameter of each CPU;
then the process of the first step is carried out,
the debugging the determined CPU according to the configuration parameters of the at least one CPU comprises the following steps:
looping through S1-S3 until there are no unselected configuration parameters for the CPU;
s1: determining a current configuration parameter which is not selected from preset configuration parameters of the at least one CPU;
s2: controlling the running state of the CPU according to the current configuration parameters, and recording the running time of the CPU in the running state;
s3: when the operation time length reaches the operation time length corresponding to the current configuration parameter, S1 is executed.
Preferably, the first and second electrodes are formed of a metal,
the S1, S2, S3, and the controlling the CPU after debugging and the to-be-debugged interconnection chip establish communication interconnection, including:
determining a first configuration parameter as a current configuration parameter from the at least one CPU configuration parameter, controlling a quick interconnect channel QPI corresponding to the CPU to operate in a low-speed state according to the current configuration parameter, and recording a first operation duration of the QPI in the low-speed state;
when the first operation duration reaches a first working duration corresponding to the first configuration parameter, selecting a second configuration parameter as a current configuration parameter from the at least one CPU configuration parameter;
controlling the QPI to run in a high-speed state according to the current configuration parameters, and recording a second running time of the QPI in the high-speed state;
when the second operation duration reaches a second working duration corresponding to the second configuration parameter, selecting a third configuration parameter as a current configuration parameter from the at least one CPU configuration parameter;
and controlling the CPU and the interconnection chip to be debugged to establish communication interconnection according to the current configuration parameters.
Preferably, the first and second electrodes are formed of a metal,
the adjusting the working mode of the interconnection chip to be debugged according to the configuration parameters corresponding to the debugged CPU comprises:
adjusting the working parameters of the register of the interconnection chip to be debugged according to the third configuration parameters;
and determining the working mode of the interconnected chip to be debugged according to the working parameters of the register.
Preferably, the first and second electrodes are formed of a metal,
after the adjusting the working mode of the interconnection chip to be debugged according to the configuration parameters corresponding to the debugged CPU, the method further includes:
and determining a verification system corresponding to the interconnected chip to be debugged, and controlling the verification system to start.
In a second aspect, an embodiment of the present invention provides an automatic debugging apparatus for a server interconnection chip, including: the device comprises a setting unit, a CPU debugging unit and a chip debugging unit; wherein,
the setting unit is used for presetting configuration parameters of at least one CPU;
the CPU debugging unit is used for determining a CPU corresponding to the interconnected chip to be debugged and debugging the determined CPU according to the configuration parameters of at least one CPU set by the setting unit;
and the chip debugging unit is used for adjusting the working mode of the interconnected chip to be debugged according to the configuration parameters corresponding to the CPU debugged by the CPU debugging unit.
Preferably, the first and second electrodes are formed of a metal,
the setting unit is further configured to set a working duration corresponding to each configuration parameter of the CPU;
the CPU debugging unit includes: a determining subunit, a controlling subunit and a judging subunit; wherein,
the determining subunit is configured to determine, from the preset configuration parameters of the at least one CPU, a current configuration parameter that is not selected;
the control subunit is configured to control an operation state of the CPU according to the current configuration parameter determined by the determination subunit, and record an operation duration of the CPU in the operation state; when the running time reaches the working time corresponding to the current configuration parameter, triggering the judgment subunit;
and the judging subunit is used for judging whether the configuration parameters of the CPU which are not selected exist, if so, triggering the determining subunit, and otherwise, triggering the chip debugging unit.
Preferably, the first and second electrodes are formed of a metal,
the determining subunit is configured to determine, from the at least one CPU configuration parameter, that a first configuration parameter is a current configuration parameter; when the first trigger of the control subunit is received, taking a second configuration parameter as a current configuration parameter; when the second trigger of the control subunit is received, taking a third configuration parameter as a current configuration parameter, and triggering the chip debugging unit;
the control subunit is configured to, when the first configuration parameter is the current configuration parameter, control a quick interconnect channel QPI corresponding to the CPU to operate in a low-speed state, and record a first operation duration of the QPI in the low-speed state; triggering the determining subunit for the first time when the first operation duration reaches a first working duration corresponding to the first configuration parameter; when the second configuration parameter is taken as the current configuration parameter, controlling the QPI to operate in a high-speed state, and recording a second operation duration of the QPI in the high-speed state; when the second operation time length reaches a second working time length corresponding to the second configuration parameter, triggering the determining subunit for the second time;
and the chip debugging unit is used for controlling the CPU to establish communication interconnection with the interconnection chip to be debugged according to the current configuration parameters when the trigger of the determining subunit is received.
Preferably, the first and second electrodes are formed of a metal,
and the chip debugging unit is used for adjusting the working parameters of the register of the interconnection chip to be debugged according to the third configuration parameters and determining the working mode of the interconnection chip to be debugged according to the working parameters of the register.
Preferably, the first and second electrodes are formed of a metal,
the chip debugging unit is further used for determining a verification system corresponding to the interconnection chip to be debugged after the working mode of the interconnection chip to be debugged is adjusted, and controlling the verification system to be started.
The embodiment of the invention provides an automatic debugging method and device of a server interconnection chip. Therefore, automatic debugging of the interconnection chip is realized, and configuration parameters of the CPU and the working mode of the interconnection chip do not need to be matched in a manual mode, so that the debugging efficiency of the interconnection chip is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of an automated debugging method for a server interconnection chip according to an embodiment of the present invention;
FIG. 2 is a flowchart of an automated debugging method for a server interconnect chip according to another embodiment of the present invention;
fig. 3 is a schematic structural diagram of an automatic debugging apparatus for a server interconnection chip according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an automatic debugging apparatus for a server interconnection chip according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides an automated debugging method for a server interconnection chip, where the method may include the following steps:
step 101: presetting configuration parameters of at least one CPU;
step 102: determining a CPU corresponding to an interconnection chip to be debugged;
step 103: debugging the determined CPU according to the configuration parameters of the at least one CPU;
step 104: controlling the debugged CPU to establish communication interconnection with the interconnection chip to be debugged;
step 105: and adjusting the working mode of the interconnection chip to be debugged according to the configuration parameters corresponding to the debugged CPU.
In the above embodiment, after the CPU corresponding to the interconnection chip to be debugged is determined, the determined CPU is debugged according to the preset configuration parameter of at least one CPU, the debugged CPU and the interconnection chip to be debugged are controlled to establish communication interconnection, and then the operating mode of the interconnection chip to be debugged is adjusted according to the configuration parameter corresponding to the debugged CPU. Therefore, automatic debugging of the interconnection chip is realized, and configuration parameters of the CPU and the working mode of the interconnection chip do not need to be matched in a manual mode, so that the debugging efficiency of the interconnection chip is improved.
In an embodiment of the present invention, the method may further include: presetting the working time length corresponding to the configuration parameter of each CPU;
specific embodiments of step 103 may include:
looping through S1-S3 until there are no unselected configuration parameters for the CPU;
s1: determining a current configuration parameter which is not selected from preset configuration parameters of the at least one CPU;
s2: controlling the running state of the CPU according to the current configuration parameters, and recording the running time of the CPU in the running state;
s3: when the operation time length reaches the operation time length corresponding to the current configuration parameter, S1 is executed.
Selecting configuration parameters from at least one preset configuration parameter of the CPU, controlling the running state of the CPU according to the selected configuration parameters, recording the running time of the CPU in the running state, and when the running time of the CPU reaches the working time corresponding to the corresponding configuration parameter, reselecting an unselected configuration parameter from the preset configuration parameters so as to change the running state of the CPU until all the preset configuration parameters are selected. Therefore, the CPU can be controlled to run for a certain time in different states according to preset configuration parameters, automatic debugging of the CPU is achieved, workers do not need to debug the working states of the CPU one by one in a manual mode, and therefore debugging efficiency of the interconnection chip is improved.
Specifically, in an embodiment of the present invention, the specific implementation of step 103 and step 104 may include:
determining a first configuration parameter as a current configuration parameter from the at least one CPU configuration parameter, controlling a quick interconnect channel QPI corresponding to the CPU to operate in a low-speed state according to the current configuration parameter, and recording a first operation duration of the QPI in the low-speed state;
when the first operation duration reaches a first working duration corresponding to the first configuration parameter, selecting a second configuration parameter as a current configuration parameter from the at least one CPU configuration parameter;
controlling the QPI to run in a high-speed state according to the current configuration parameters, and recording a second running time of the QPI in the high-speed state;
when the second operation duration reaches a second working duration corresponding to the second configuration parameter, selecting a third configuration parameter as a current configuration parameter from the at least one CPU configuration parameter;
and controlling the CPU and the interconnection chip to be debugged to establish communication interconnection according to the current configuration parameters.
For example, when an interconnection chip is verified by using a Field-Programmable Gate Array (FPGA) prototype verification technology, a server is powered on, an FPGA bit stream is loaded, and then the operating rate of a CPU is set by using a first configuration parameter based on the requirement of an intel, so that the QPI of the CPU operates in a low-speed mode, and meanwhile, the first operating duration of the CPU is recorded. And when the first operation duration reaches the first working duration corresponding to the first configuration parameter, setting the operation rate of the CPU by using the second configuration parameter, so that the QPI operates in a high-speed mode. Specifically, when the CPU is debugged manually, the server input/output system outputs corresponding prompt information whenever the operating state needs to be switched, and at this time, a worker needs to change the CPU configuration according to the prompt information, and after multiple configurations, the worker can obtain an experience value of the operating time corresponding to each operating state, and can preset the experience value as the operating time corresponding to the configuration parameter.
In the process, the QPI corresponding to the CPU is switched from the low-speed state to the high-speed state, so that the starting state of the CPU is more stable, the CPU is also favorable for keeping stable operation in the verification process of the interconnected chip, and the accurate verification of the interconnected chip is further favorable. In addition, when the second operation duration of the QPI reaches the second operation duration, the CPU is configured by using the third configuration parameter, where the configuration parameter may include the number of processing cores, the storage capacity, and the like of the CPU, and after the configuration is completed, the CPU is controlled to establish communication interconnection with the interconnection chip to be debugged, and in this interconnection state, the operation mode of the interconnection chip to be debugged may be debugged according to the configuration parameters, such as the number of processing cores, the storage capacity, and the like, of the CPU. Therefore, the CPU can be in communication interconnection with the interconnection chip to be debugged in a stable running state, and accurate debugging of the interconnection chip is facilitated.
In an embodiment of the present invention, the step 105 may be implemented by:
adjusting the working parameters of the register of the interconnection chip to be debugged according to the third configuration parameters;
and determining the working mode of the interconnected chip to be debugged according to the working parameters of the register.
For example, if the number of processing cores of the CPU configured according to the third configuration parameter is 8 cores and the memory is 4096MB, the working parameters of the register of the interconnection chip to be debugged may be adjusted according to the third configuration parameter, that is, the working parameters of the register are also adjusted to correspond to the 8-core processor and the memory 4096MB, and then the interconnection chip to be debugged is adjusted to the working mode corresponding thereto according to the adjusted working parameters of the register, so as to implement automatic matching with the adjusted CPU, thereby improving the debugging efficiency of the interconnection chip.
In an embodiment of the present invention, after step 105, the method may further include:
and determining a verification system corresponding to the interconnected chip to be debugged, and controlling the verification system to start.
In this embodiment, after the interconnection chip to be debugged is adjusted, the verification system corresponding to the interconnection chip to be debugged is automatically controlled to start, and then the interconnection chip is automatically verified, so that the verification efficiency of the interconnection chip is improved.
As shown in fig. 2, an embodiment of the present invention provides an automated debugging method for a server interconnection chip, where the method may include the following steps:
step 201: the configuration parameters of 3 CPUs and the working time corresponding to each configuration parameter are preset.
For example, the configuration parameters of the 3 CPUs are a configuration parameter a, a configuration parameter B, and a configuration parameter C, respectively, where the configuration parameter a corresponds to a low-speed state, the configuration parameter B corresponds to a high-speed state, and the configuration parameter C corresponds to attribute information of the CPU, such as the number of processing cores and memory capacity.
Step 202: and determining the CPU corresponding to the interconnected chip to be debugged.
And determining the CPU which needs to establish communication interconnection with the interconnection chip to be debugged and verifying the interconnection chip according to the communication interconnection.
Step 203: selecting a configuration parameter A from 3 preset configuration parameters, controlling the QPI corresponding to the CPU to operate in a low-speed state according to the configuration parameter A, and recording a first operation time length of the QPI in the low-speed state.
For example, when an interconnection chip is verified by using an FPGA prototype verification technology, a server is powered on, an FPGA bit stream is loaded, and then the operating rate of a CPU is set by using a configuration parameter a based on the requirement of an intel, so that the QPI of the CPU operates in a low-speed mode, and the first operating duration of the CPU is recorded.
Step 204: and when the first operation time length reaches a first working time length corresponding to the configuration parameter A, selecting a configuration parameter B from 3 preset configuration parameters, controlling the QPI to operate in a high-speed state according to the configuration parameter B, and recording a second operation time of the QPI in the high-speed state.
Here, the QPI corresponding to the CPU is switched from the low-speed state to the high-speed state, so that the startup state of the CPU is more stable, which is also beneficial for the CPU to keep operating stably in the verification process of the interconnected chip.
Step 205: and when the second operation time reaches a second working time corresponding to the configuration parameter B, selecting a configuration parameter C from the preset 3 configuration parameters, and controlling the CPU to establish communication interconnection with the interconnection chip to be debugged according to the configuration parameter C.
And when the second operation time of the QPI reaches the second working time, configuring the CPU by using the configuration parameter C, wherein the configuration parameter C can comprise the processing core number, the storage capacity and the like of the CPU, controlling the CPU to establish communication interconnection with the interconnection chip to be debugged after the configuration is finished, and debugging the working mode of the interconnection chip to be debugged according to the configuration parameters of the processing core number, the storage capacity and the like of the CPU in the interconnection state.
Step 206: and adjusting the working parameters of the register of the interconnected chip to be debugged according to the configuration parameters C, and determining the working mode of the interconnected chip to be debugged according to the working parameters of the register.
For example, if the number of processing cores of the CPU configured according to the configuration parameter C is 8 cores and the memory is 4096MB, the operating parameter of the register may also be adjusted to correspond to the 8-core processor and the memory 4096MB according to the third configuration parameter, and then the interconnect chip to be debugged is adjusted to the operating mode corresponding thereto according to the adjusted operating parameter of the register, so as to implement automatic matching with the adjusted CPU.
Step 207: and determining a verification system corresponding to the interconnected chip to be debugged, and controlling the verification system to start.
After the interconnection chip to be debugged is adjusted, the verification system corresponding to the interconnection chip to be debugged is automatically controlled to be started, and then the interconnection chip is automatically verified, so that the verification efficiency of the interconnection chip is improved.
The method in this embodiment can be implemented by at least the following procedures:
########################################
echo"Boot Step1＝>BIOS_1:Begin"
first time # configure cpu script
./BIOS_1.txt
echo"Boot Step1＝>BIOS_1:Done and Wait 35s"
# latency value, which needs to be adjusted experimentally
sleep 35
########
echo"Boot Step2＝>BIOS_2:Begin"
Second configuration of cpu script #
./BIOS_2.txt
echo"Boot Step2＝>BIOS_2:Done and Wait 180s"
# latency value, which needs to be adjusted experimentally
sleep 180
########################################
echo"Boot Step3＝>QPI LINK:Begin"
# boot cpu and qpi interface of interconnection chip
./qpi_link.txt
echo"Boot Step3＝>QPI LINK:Done and check"
########################################
########################################
echo"Boot Step4＝>NC Config:Begin"
Register configuration of # interconnect chip
./nc_config.txt
echo"Boot Step4＝>NC Config:Done"
########################################
In the above embodiment, after the CPU corresponding to the interconnection chip to be debugged is determined, the determined CPU is debugged according to the preset configuration parameters of 3 CPUs, the debugged CPU and the interconnection chip to be debugged are controlled to establish communication interconnection, and then the operating mode of the interconnection chip to be debugged is adjusted according to the configuration parameters corresponding to the debugged CPU. Therefore, automatic debugging of the interconnection chip is realized, and configuration parameters of the CPU and the working mode of the interconnection chip do not need to be matched in a manual mode, so that the debugging efficiency of the interconnection chip is improved.
As shown in fig. 3, an embodiment of the present invention provides an automatic debugging apparatus for a server interconnection chip, including: a setting unit 301, a CPU debugging unit 302, and a chip debugging unit 303; wherein,
the setting unit 301 is configured to preset configuration parameters of at least one CPU;
the CPU debugging unit 302 is configured to determine a CPU corresponding to an interconnection chip to be debugged, and debug the determined CPU according to at least one configuration parameter of the CPU set by the setting unit 301;
the chip debugging unit 303 is configured to adjust a working mode of the interconnection chip to be debugged according to the configuration parameter corresponding to the CPU debugged by the CPU debugging unit 302.
In the above embodiment, after the CPU corresponding to the interconnection chip to be debugged is determined, the determined CPU is debugged according to the preset configuration parameter of at least one CPU, the debugged CPU and the interconnection chip to be debugged are controlled to establish communication interconnection, and then the operating mode of the interconnection chip to be debugged is adjusted according to the configuration parameter corresponding to the debugged CPU. Therefore, automatic debugging of the interconnection chip is realized, and configuration parameters of the CPU and the working mode of the interconnection chip do not need to be matched in a manual mode, so that the debugging efficiency of the interconnection chip is improved.
As shown in fig. 4, in an embodiment of the present invention, the setting unit 301 is further configured to set an operating time length corresponding to each configuration parameter of the CPU;
the CPU debug unit 302 includes: a determination subunit 401, a control subunit 402, and a judgment subunit 403; wherein,
the determining subunit 401 is configured to determine, from the preset configuration parameters of the at least one CPU, a current configuration parameter that is not selected;
the control subunit 402 is configured to control an operation state of the CPU according to the current configuration parameter determined by the determining subunit 401, and record an operation duration of the CPU in the operation state; when the operation duration reaches the working duration corresponding to the current configuration parameter, triggering the judgment subunit 403;
the determining subunit 403 is configured to determine whether there is a configuration parameter of the CPU that has not been selected, if yes, trigger the determining subunit 401, and otherwise trigger the chip debugging unit 303.
Selecting configuration parameters from at least one preset configuration parameter of the CPU, controlling the running state of the CPU according to the selected configuration parameters, recording the running time of the CPU in the running state, and when the running time of the CPU reaches the working time corresponding to the corresponding configuration parameter, reselecting an unselected configuration parameter from the preset configuration parameters so as to change the running state of the CPU until all the preset configuration parameters are selected. Therefore, the CPU can be controlled to run for a certain time in different states according to preset configuration parameters, automatic debugging of the CPU is achieved, workers do not need to debug the working states of the CPU one by one in a manual mode, and therefore debugging efficiency of the interconnection chip is improved.
Specifically, in an embodiment of the present invention, the determining subunit 401 is configured to determine, from the at least one CPU configuration parameter, that a first configuration parameter is a current configuration parameter; when the first trigger of the control subunit 402 is received, taking the second configuration parameter as the current configuration parameter; when the second trigger of the control subunit 402 is received, taking a third configuration parameter as a current configuration parameter, and triggering the chip debugging unit 303;
the control subunit 402 is configured to, when the first configuration parameter is the current configuration parameter, control a quick interconnect channel QPI corresponding to the CPU to operate in a low-speed state, and record a first operation duration of the QPI in the low-speed state; when the first operation duration reaches a first working duration corresponding to the first configuration parameter, triggering the determining subunit 401 for the first time; when the second configuration parameter is taken as the current configuration parameter, controlling the QPI to operate in a high-speed state, and recording a second operation duration of the QPI in the high-speed state; when the second operation duration reaches a second working duration corresponding to the second configuration parameter, triggering the determining subunit 401 for a second time;
the chip debugging unit 303 is configured to, when receiving the trigger of the determining subunit 401, control the CPU to establish communication interconnection with the interconnection chip to be debugged according to the current configuration parameter.
For example, when an interconnection chip is verified by using a Field-Programmable Gate Array (FPGA) prototype verification technology, a server is powered on, an FPGA bit stream is loaded, and then the operating rate of a CPU is set by using a first configuration parameter based on the requirement of an intel, so that the QPI of the CPU operates in a low-speed mode, and meanwhile, the first operating duration of the CPU is recorded. And when the first operation duration reaches the first working duration corresponding to the first configuration parameter, setting the operation rate of the CPU by using the second configuration parameter, so that the QPI operates in a high-speed mode. Specifically, when the CPU is debugged manually, the server input/output system outputs corresponding prompt information whenever the operating state needs to be switched, and at this time, a worker needs to change the CPU configuration according to the prompt information, and after multiple configurations, the worker can obtain an experience value of the operating time corresponding to each operating state, and can preset the experience value as the operating time corresponding to the configuration parameter.
In the process, the QPI corresponding to the CPU is switched from the low-speed state to the high-speed state, so that the starting state of the CPU is more stable, the CPU is also favorable for keeping stable operation in the verification process of the interconnected chip, and the accurate verification of the interconnected chip is further favorable. In addition, when the second operation duration of the QPI reaches the second operation duration, the CPU is configured by using the third configuration parameter, where the configuration parameter may include the number of processing cores, the storage capacity, and the like of the CPU, and after the configuration is completed, the CPU is controlled to establish communication interconnection with the interconnection chip to be debugged, and in this interconnection state, the operation mode of the interconnection chip to be debugged may be debugged according to the configuration parameters, such as the number of processing cores, the storage capacity, and the like, of the CPU. Therefore, the CPU can be in communication interconnection with the interconnection chip to be debugged in a stable running state, and accurate debugging of the interconnection chip is facilitated.
In an embodiment of the present invention, the chip debugging unit 303 is configured to adjust a working parameter of a register of the interconnection chip to be debugged according to the third configuration parameter, and determine a working mode of the interconnection chip to be debugged according to the working parameter of the register.
For example, if the number of processing cores of the CPU configured according to the third configuration parameter is 8 cores and the memory is 4096MB, the working parameters of the register of the interconnection chip to be debugged may be adjusted according to the third configuration parameter, that is, the working parameters of the register are also adjusted to correspond to the 8-core processor and the memory 4096MB, and then the interconnection chip to be debugged is adjusted to the working mode corresponding thereto according to the adjusted working parameters of the register, so as to implement automatic matching with the adjusted CPU, thereby improving the debugging efficiency of the interconnection chip.
In an embodiment of the present invention, the chip debugging unit 303 is further configured to determine a verification system corresponding to the interconnection chip to be debugged after adjusting the working mode of the interconnection chip to be debugged, and control the verification system to start.
In this embodiment, after the interconnection chip to be debugged is adjusted, the verification system corresponding to the interconnection chip to be debugged is automatically controlled to start, and then the interconnection chip is automatically verified, so that the verification efficiency of the interconnection chip is improved.
Because the information interaction, execution process, and other contents between the units in the device are based on the same concept as the method embodiment of the present invention, specific contents may refer to the description in the method embodiment of the present invention, and are not described herein again.
The invention also provides a readable medium comprising executable instructions which, when executed by a processor of a storage controller, cause the storage controller to perform a method as provided by any of the above-described embodiments of the invention.
In addition, the present invention also provides a memory controller comprising: a processor, a memory, and a bus; the memory is used for storing execution instructions, the processor is connected with the memory through the bus, and when the storage controller runs, the processor executes the execution instructions stored in the memory, so that the storage controller executes the method provided by any one of the above embodiments of the invention.
In summary, the embodiments of the present invention have at least the following advantages:
1. in the embodiment of the invention, after the CPU corresponding to the interconnection chip to be debugged is determined, the determined CPU is debugged according to the preset configuration parameter of at least one CPU, the debugged CPU and the interconnection chip to be debugged are controlled to establish communication interconnection, and then the working mode of the interconnection chip to be debugged is adjusted according to the configuration parameter corresponding to the debugged CPU. Therefore, automatic debugging of the interconnection chip is realized, and configuration parameters of the CPU and the working mode of the interconnection chip do not need to be matched in a manual mode, so that the debugging efficiency of the interconnection chip is improved.
2. In the embodiment of the invention, configuration parameters are selected from at least one preset configuration parameter of the CPU, the running state of the CPU is controlled according to the selected configuration parameters, the running time of the CPU in the running state is recorded, and when the running time of the CPU reaches the working time corresponding to the corresponding configuration parameter, an unselected configuration parameter is selected from the preset configuration parameters again, so that the running state of the CPU is changed until all the preset configuration parameters are selected. Therefore, the CPU can be controlled to run for a certain time in different states according to preset configuration parameters, automatic debugging of the CPU is achieved, workers do not need to debug the working states of the CPU one by one in a manual mode, and therefore debugging efficiency of the interconnection chip is improved.
3. In the embodiment of the invention, the running speed of the CPU is set by using the first configuration parameter, so that the QPI runs in the low-speed mode, and the first running time length of the QPI is recorded at the same time. And when the first operation duration reaches the first working duration corresponding to the first configuration parameter, setting the operation rate of the CPU by using the second configuration parameter, so that the QPI operates in a high-speed mode. In the process, the QPI corresponding to the CPU is switched from the low-speed state to the high-speed state, so that the starting state of the CPU is more stable, the CPU is also favorable for keeping stable operation in the verification process of the interconnected chip, and the accurate verification of the interconnected chip is further favorable.
4. In the embodiment of the invention, when the second operation time of the QPI reaches the second working time, the CPU is configured by using the third configuration parameter, the CPU is controlled to establish communication interconnection with the interconnection chip to be debugged after the configuration is finished, and the working mode of the interconnection chip to be debugged is debugged in the interconnection state. Therefore, the CPU can be in communication interconnection with the interconnection chip to be debugged in a stable running state, and accurate debugging of the interconnection chip is facilitated.
5. In the embodiment of the invention, the working parameters of the register of the interconnection chip to be debugged are adjusted according to the third configuration parameters corresponding to the CPU, and then the interconnection chip to be debugged is adjusted to the working mode corresponding to the adjusted working parameters of the register, so that the interconnection chip is automatically matched with the adjusted CPU, and the debugging efficiency of the interconnection chip is improved.
6. In the embodiment of the invention, after the interconnection chip to be debugged is adjusted, the verification system corresponding to the interconnection chip to be debugged is automatically controlled to start, and then the interconnection chip is automatically verified, so that the verification efficiency of the interconnection chip is improved.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of other similar elements in a process, method, article, or apparatus that comprises the element.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it is to be noted that: the above description is only a preferred embodiment of the present invention, and is only used to illustrate the technical solutions of the present invention, and not to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (2)
1. An automatic debugging method for a server interconnection chip is characterized by comprising the following steps:
presetting configuration parameters of at least one CPU;
determining a CPU corresponding to an interconnection chip to be debugged;
debugging the determined CPU according to the configuration parameters of the at least one CPU;
controlling the debugged CPU to establish communication interconnection with the interconnection chip to be debugged;
adjusting the working mode of the interconnection chip to be debugged according to the configuration parameters corresponding to the debugged CPU;
the method comprises the following steps:
further comprising: presetting the working time length corresponding to the configuration parameter of each CPU;
then the process of the first step is carried out,
the debugging the determined CPU according to the configuration parameters of the at least one CPU comprises the following steps:
looping through S1-S3 until there are no unselected configuration parameters for the CPU;
s1: determining a current configuration parameter which is not selected from preset configuration parameters of the at least one CPU;
s2: controlling the running state of the CPU according to the current configuration parameters, and recording the running time of the CPU in the running state;
s3: executing S1 when the operation duration reaches the working duration corresponding to the current configuration parameter;
the S1, S2, S3, and the controlling the CPU after debugging and the to-be-debugged interconnection chip establish communication interconnection, including:
determining a first configuration parameter as a current configuration parameter from the at least one CPU configuration parameter, controlling a quick interconnect channel QPI corresponding to the CPU to operate in a low-speed state according to the current configuration parameter, and recording a first operation duration of the QPI in the low-speed state;
when the first operation duration reaches a first working duration corresponding to the first configuration parameter, selecting a second configuration parameter as a current configuration parameter from the at least one CPU configuration parameter;
controlling the QPI to run in a high-speed state according to the current configuration parameters, and recording a second running time of the QPI in the high-speed state;
when the second operation duration reaches a second working duration corresponding to the second configuration parameter, selecting a third configuration parameter as a current configuration parameter from the at least one CPU configuration parameter;
controlling the CPU and the interconnection chip to be debugged to establish communication interconnection according to the current configuration parameters;
the adjusting the working mode of the interconnection chip to be debugged according to the configuration parameters corresponding to the debugged CPU comprises:
adjusting the working parameters of the register of the interconnection chip to be debugged according to the third configuration parameters;
determining the working mode of the interconnection chip to be debugged according to the working parameters of the register;
after the adjusting the working mode of the interconnection chip to be debugged according to the configuration parameters corresponding to the debugged CPU, the method further includes:
and determining a verification system corresponding to the interconnected chip to be debugged, and controlling the verification system to start.
2. The utility model provides an automatic debugging device of server interconnection chip which characterized in that includes: the device comprises a setting unit, a CPU debugging unit and a chip debugging unit; wherein,
the setting unit is used for presetting configuration parameters of at least one CPU;
the CPU debugging unit is used for determining a CPU corresponding to the interconnected chip to be debugged and debugging the determined CPU according to the configuration parameters of at least one CPU set by the setting unit;
the chip debugging unit is used for adjusting the working mode of the interconnected chip to be debugged according to the configuration parameters corresponding to the CPU debugged by the CPU debugging unit;
the setting unit is further configured to set a working duration corresponding to each configuration parameter of the CPU;
the CPU debugging unit includes: a determining subunit, a controlling subunit and a judging subunit; wherein,
the determining subunit is configured to determine, from the preset configuration parameters of the at least one CPU, a current configuration parameter that is not selected;
the control subunit is configured to control an operation state of the CPU according to the current configuration parameter determined by the determination subunit, and record an operation duration of the CPU in the operation state; when the running time reaches the working time corresponding to the current configuration parameter, triggering the judgment subunit;
the judging subunit is used for judging whether the configuration parameters of the CPU which are not selected exist, if so, the determining subunit is triggered, otherwise, the chip debugging unit is triggered;
the determining subunit is configured to determine, from the at least one CPU configuration parameter, that a first configuration parameter is a current configuration parameter; when the first trigger of the control subunit is received, taking a second configuration parameter as a current configuration parameter; when the second trigger of the control subunit is received, taking a third configuration parameter as a current configuration parameter, and triggering the chip debugging unit;
the control subunit is configured to, when the first configuration parameter is the current configuration parameter, control a quick interconnect channel QPI corresponding to the CPU to operate in a low-speed state, and record a first operation duration of the QPI in the low-speed state; triggering the determining subunit for the first time when the first operation duration reaches a first working duration corresponding to the first configuration parameter; when the second configuration parameter is taken as the current configuration parameter, controlling the QPI to operate in a high-speed state, and recording a second operation duration of the QPI in the high-speed state; when the second operation time length reaches a second working time length corresponding to the second configuration parameter, triggering the determining subunit for the second time;
the chip debugging unit is used for controlling the CPU to establish communication interconnection with the interconnection chip to be debugged according to the current configuration parameters when the trigger of the determining subunit is received;
the chip debugging unit is used for adjusting the working parameters of the register of the interconnection chip to be debugged according to the third configuration parameters and determining the working mode of the interconnection chip to be debugged according to the working parameters of the register;
the chip debugging unit is further used for determining a verification system corresponding to the interconnection chip to be debugged after the working mode of the interconnection chip to be debugged is adjusted, and controlling the verification system to be started.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710485192.3A CN107239376B (en) | 2017-06-23 | 2017-06-23 | Automatic debugging method and device for server interconnection chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710485192.3A CN107239376B (en) | 2017-06-23 | 2017-06-23 | Automatic debugging method and device for server interconnection chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107239376A CN107239376A (en) | 2017-10-10 |
| CN107239376B true CN107239376B (en) | 2020-12-01 |
Family
ID=59986719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710485192.3A Active CN107239376B (en) | 2017-06-23 | 2017-06-23 | Automatic debugging method and device for server interconnection chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107239376B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108052404A (en) * | 2017-12-07 | 2018-05-18 | 郑州云海信息技术有限公司 | A kind of data address error-detection mechanism in server interconnection chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102122259A (en) * | 2011-03-03 | 2011-07-13 | 浪潮(北京)电子信息产业有限公司 | Prototype verification system and method of high-end fault tolerant computer |
| CN104239173A (en) * | 2013-06-06 | 2014-12-24 | 鸿富锦精密工业（深圳）有限公司 | Bus testing device and method of CPU (Central Processing Unit) |
| CN105511992A (en) * | 2015-12-09 | 2016-04-20 | 浪潮电子信息产业股份有限公司 | Global detection module method for verifying node interconnection chip |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142050A (en) * | 2011-03-01 | 2011-08-03 | 浪潮(北京)电子信息产业有限公司 | Single node prototype verification system and method of high-end fault-tolerant computer |
| WO2012103712A1 (en) * | 2011-06-27 | 2012-08-09 | 华为技术有限公司 | Cpu interconnect device |
| CN104598350B (en) * | 2013-10-31 | 2016-08-17 | 上海华虹集成电路有限责任公司 | Contact type CPU chip production method of testing |
| CN104750581A (en) * | 2015-04-01 | 2015-07-01 | 浪潮电子信息产业股份有限公司 | Redundant interconnected memory sharing server system |
| CN105740117B (en) * | 2016-01-29 | 2018-05-25 | 硅谷数模半导体（北京）有限公司 | Chip adjustment method and device |
| CN105823978B (en) * | 2016-03-11 | 2018-09-14 | 福州瑞芯微电子股份有限公司 | A kind of general chip testing clock circuit and its test method |
-
2017
- 2017-06-23 CN CN201710485192.3A patent/CN107239376B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102122259A (en) * | 2011-03-03 | 2011-07-13 | 浪潮(北京)电子信息产业有限公司 | Prototype verification system and method of high-end fault tolerant computer |
| CN104239173A (en) * | 2013-06-06 | 2014-12-24 | 鸿富锦精密工业（深圳）有限公司 | Bus testing device and method of CPU (Central Processing Unit) |
| CN105511992A (en) * | 2015-12-09 | 2016-04-20 | 浪潮电子信息产业股份有限公司 | Global detection module method for verifying node interconnection chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107239376A (en) | 2017-10-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102683217B1 (en) | Method and apparatus for performing an erase-suspend operation on a memory device | |
| US9110669B2 (en) | Power management of a storage device including multiple processing cores | |
| EP3091434B1 (en) | Chip starting method, multi-core processor chip and storage medium | |
| JP6305976B2 (en) | Method, apparatus and system for delaying packets during execution of a network-driven wakeup operation on a computing device | |
| US11433718B2 (en) | Upgrading method and apparatus for tire pressure monitoring module and tire pressure sensor | |
| KR20170108788A (en) | User configurable passive background operation | |
| CN107704310B (en) | Method, device and equipment for realizing container cluster management | |
| US9529536B2 (en) | Semiconductor memory device, memory system including the same, and operating method thereof | |
| WO2017193964A1 (en) | Component upgrade method, apparatus and system | |
| WO2024077881A1 (en) | Scheduling method and system for neural network training, and computer-readable storage medium | |
| US10657022B2 (en) | Input and output recording device and method, CPU and data read and write operation method thereof | |
| US9824229B2 (en) | Controller with enhanced reliability | |
| US9377966B2 (en) | Method and apparatus for efficiently processing storage commands | |
| CN106293805A (en) | The method and device that program loads | |
| CN107239376B (en) | Automatic debugging method and device for server interconnection chip | |
| CN113687779B (en) | Data migration method, device, electronic equipment and readable storage medium | |
| CN103543982B (en) | A kind of clock frequency management method and mobile device | |
| CN113434467B (en) | Network file transmission method, device and computer readable storage medium | |
| EP2620876B1 (en) | Method and apparatus for data processing, pci-e bus system and server | |
| US20070005860A1 (en) | Interrupt control system and method | |
| CN106168932B (en) | Flash control method and device | |
| CN106980513A (en) | A kind of switching method and device of dual boot file | |
| CN115756322A (en) | Data storage method and device, electronic equipment and storage medium | |
| JP2023546903A (en) | Priority update of inactive memory devices | |
| CN104077156B (en) | The restarting systems and its method of programmable CPU |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20201110 Address after: 215100 No. 1 Guanpu Road, Guoxiang Street, Wuzhong Economic Development Zone, Suzhou City, Jiangsu Province Applicant after: SUZHOU LANGCHAO INTELLIGENT TECHNOLOGY Co.,Ltd. Address before: 450000 Henan province Zheng Dong New District of Zhengzhou City Xinyi Road No. 278 16 floor room 1601 Applicant before: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |