CN107204344B - Tft阵列基板结构 - Google Patents
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Abstract
本发明提供一种TFT阵列基板结构,在钝化绝缘层(8)上设置第一通孔(V1),在钝化绝缘层(8)与栅极绝缘层(3)上设置第二通孔(V2),且所述第一通孔(V1)与第二通孔(V2)沿横向间隔设置,在所述第一通孔(V1)内、第二通孔(V2)内、及第一通孔(V1)与第二通孔(V2)之间沉积用于连接第三漏极(D3)与公共电压线(Com)的导电薄膜(9),能够避免倒角问题,防范导电薄膜发生断裂及接触不良的风险,使放电TFT与公共电压线之间的连接可靠,提升TFT阵列基板的良率及其信赖性。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种TFT阵列基板结构。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,TFT-LCD)能够显示高清、连续、细腻的画面,越来越受消费者青睐。
现有市场上的TFT-LCD通常包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组。液晶面板由一彩色滤光片(Color Filter,CF)基板、一薄膜晶体管阵列基板(ThinFilm Transistor Array Substrate,TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成,其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转,将背光模组的光线折射出来产生画面。
TFT-LCD要显示连续、细腻的高清晰画面,需要像素(Pixel)间做亮暗连贯性变化。两个连续变化的像素可以通过不同的开关时间差异所形成的亮度差异实现,但是该方法驱动设计难以实现;另一种方法可以通过给像素在相同时间内充入不同电量来使得上下电极或驱动电极间压差不一致,从而使液晶偏转角度不一致,光透过率不一致,达到亮暗连续变化的要求。现有技术通常通过拉低不同像素的电位来实现在相同充电时间内不同像素的充电饱和度不同、充电电荷不同、电位不一致的效果。
如图1所示,以3个TFT为驱动单元的设计方式已经普遍应用于控制单个像素的充电饱和度,其中栅极线G用于开启第一充电TFT T1、第二充电TFT T2、与放电TFT T3,第一充电TFT T1与第二充电TFT T2这两个TFT主要将数据线D传输的数据信号写入对应的两个相邻像素进行充电,放电TFT T3直接电性连接第二充电TFT T2的漏极与电位较低的公共电压线Com,将与第二充电TFT T2电性连接的像素的电荷导出以拉低该像素的电位。这样设计的优点在于:可以在不牺牲开口率的前提下有效地拉低两相邻像素其中之一的电位。
请同时参阅图2与图3,结合图1,为了实现放电TFT T3的漏极D3与公共电压线Com之间的连接,现有的TFT阵列基板将贯穿该放电TFT T3的漏极D3及其下方半导体有源层400的通孔V1’、和贯穿设于放电TFT T3的漏极D3下方的半导体有源层400与公共电压线Com之间的栅极绝缘层200的公共过孔V2’设计成一体,通过在通孔V1’和公共过孔V2’内沉积导电薄膜如氧化铟锡(Indium Tin Oxide,ITO)来连接放电TFT T3的漏极D3与公共电压线Com。这种现有的TFT阵列基板在制作所述一体的通孔V1’与公共过孔V2’时采用化学刻蚀和物理刻蚀兼具的干法刻蚀,位于放电TFT T3的漏极D3下方的半导体有源层400和栅极绝缘层200在干法刻蚀气体六氟化硫(SF6)的作用下发生化学反应形成气体挥发,且由于半导体有源层400(材料成分为非晶硅(a-Si)与经过N型重掺杂的非晶硅(N+a-Si))和栅极绝缘层200(材料成分为氮化硅(SiNx))的材料成分不同,与SF6的刻蚀反应速率不同,加上放电TFT T3的漏极D3的金属断面与半导体有源层400的断面被通孔V1’及公共过孔V2’裸露,导致在TFTT3的漏极D3与半导体有源层400的界面处、及半导体有源层400与栅极绝缘层200的界面处形成如图3所示的倒角(Undercut)问题(用虚线椭圆圈出),容易造成ITO爬坡发生断裂及接触不良的风险,影响TFT阵列基板的良率及其信赖性。
发明内容
本发明的目的在于提供一种TFT阵列基板结构,能够避免倒角问题,防范导电薄膜发生断裂及接触不良的风险,使放电TFT与公共电压线之间的连接可靠,提升TFT阵列基板的良率及其信赖性。
为实现上述目的,本发明提供一种TFT阵列基板结构,包括自下至上依次层叠设置的第一金属层、栅极绝缘层、半导体有源层、第二金属层、及钝化绝缘层;
所述TFT阵列基板结构具有多个呈阵列式排布的像素区域,在纵向相邻的两像素区域内,所述第一金属层包括沿横向延伸的公共电压线、及栅极线,所述第二金属层包括沿纵向延伸的数据线、与所述数据线连接的第一源极、与所述数据线连接的第二源极、与所述第一源极相对设置的第一漏极、与所述第二源极相对设置的第二漏极、与所述第二漏极连接的第三源极、及与所述第三源极相对设置的第三漏极;所述钝化绝缘层覆盖第二金属层、半导体有源层、与栅极绝缘层;
所述钝化绝缘层上设有贯穿该钝化绝缘层的第一通孔,所述第一通孔暴露出第三漏极的部分表面;所述钝化绝缘层与栅极绝缘层上设有贯穿该钝化绝缘层与栅极绝缘层的第二通孔,所述第二通孔暴露出公共电压线的部分表面;所述第一通孔与第二通孔沿横向间隔设置;所述第一通孔内、第二通孔内、及第一通孔与第二通孔之间沉积有用于连接第三漏极与公共电压线的导电薄膜。
所述栅极线、第一源极、与第一漏极形成第一充电TFT,所述栅极线、第二源极、与第二漏极形成第二充电TFT,所述栅极线、第三源极、与第三漏极形成放电TFT;
所述第一漏极连接一像素电极,所述第二漏极连接另一像素电极。
所述第一通孔与第二通孔的开口形状均呈矩形或圆形。
所述第一通孔的开口尺寸大于5um。
所述第二通孔的开口尺寸大于5um。
所述第一通孔距第三漏极位于第一通孔与第二通孔之间的边界的距离大于4um。
所述第二通孔距第三漏极位于第一通孔与第二通孔之间的边界的距离大于4um。
所述栅极绝缘层与钝化绝缘层的材料均为氮化硅;所述导电薄膜的材料为氧化铟锡。
本发明的有益效果:本发明提供的一种TFT阵列基板结构,在钝化绝缘层上设置第一通孔,在钝化绝缘层与栅极绝缘层上设置第二通孔,且所述第一通孔与第二通孔沿横向间隔设置,在所述第一通孔内、第二通孔内、及第一通孔与第二通孔之间沉积用于连接第三漏极与公共电压线的导电薄膜;由于第三漏极的金属断面与半导体有源层的断面均被钝化绝缘层覆盖,在钝化绝缘层的保护作用下,第三漏极与半导体有源层界面处及半导体有源层与栅极绝缘层的界面处不会出现倒角,从而能够防范导电薄膜发生断裂及接触不良的风险,使放电TFT与公共电压线之间的连接可靠,提升TFT阵列基板的良率及其信赖性。
附图说明
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图中,
图1为现有的以3个TFT为驱动单元的电路结构图;
图2为现有的TFT阵列基板结构的主视图;
图3为对应于图2中A-A处的剖视图;
图4为本发明的TFT阵列基板结构的主视图;
图5为对应于图4中B-B处的剖视图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图4与图5,本发明提供一种TFT阵列基板结构,包括自下至上依次层叠设置的第一金属层、栅极绝缘层3、半导体有源层5、第二金属层、及钝化绝缘层8。
所述TFT阵列基板结构具有多个呈阵列式排布的像素区域,在纵向相邻的两像素区域内,所述第一金属层包括沿横向延伸的公共电压线Com、及栅极线G,所述第二金属层包括沿纵向延伸的数据线D、与所述数据线D连接的第一源极S1、与所述数据线D连接的第二源极S2、与所述第一源极S1相对设置的第一漏极D1、与所述第二源极S2相对设置的第二漏极D2、与所述第二漏极D2连接的第三源极S3、及与所述第三源极S3相对设置的第三漏极D3;所述钝化绝缘层8覆盖第二金属层、半导体有源层5、与栅极绝缘层3。所述半导体有源层5被各个源极与漏极覆盖,并对第一源极S1与第一漏极D1进行连接,对第二源极S2与第二漏极D2进行连接,对第三源极S3与第三漏极D3进行连接。
所述栅极线G、第一源极S1、与第一漏极D1形成第一充电TFT T1,所述栅极线G、第二源极S2、与第二漏极D2形成第二充电TFT T2,所述栅极线G、第三源极S3、与第三漏极D3形成放电TFT T3。所述第一漏极D1连接一像素电极P1,所述第二漏极D2连接另一像素电极P2。
具体地,所述栅极绝缘层3与钝化绝缘层8的材料均为SiNx。
与现有技术不同,在本发明的TFT阵列基板结构中,所述钝化绝缘层8上设有贯穿该钝化绝缘层8的第一通孔V1,所述第一通孔V1暴露出第三漏极D3的部分表面;所述钝化绝缘层8与栅极绝缘层3上设有贯穿该钝化绝缘层8与栅极绝缘层3的第二通孔V2,所述第二通孔V2暴露出公共电压线Com的部分表面;所述第一通孔V1与第二通孔V2沿横向间隔设置;所述第一通孔V1内、第二通孔V2内、及第一通孔V1与第二通孔V2之间沉积有用于连接第三漏极D3与公共电压线Com的导电薄膜9。
如图5所示,第三漏极D3的金属断面与半导体有源层5的断面均被钝化绝缘层8覆盖,由于钝化绝缘层8的保护作用,避免了第三漏极D3与半导体有源层5界面处及半导体有源层5与栅极绝缘层3的界面处出现倒角,且在制作所述第一通孔V1时仅需对以SiNx为材料的钝化绝缘层8进行刻蚀,在制作所述第二通孔V2时仅需对钝化绝缘层8及同样以SiNx为材料的栅极绝缘层3进行刻蚀,干法刻蚀气体与SiNx的反应速率均匀,从而制得的第一通孔V1与第二通孔V2的轮廓较平缓,能够防范导电薄膜9发生断裂及接触不良的风险,使放电TFTT3与公共电压线Com之间的连接可靠,提升TFT阵列基板的良率及其信赖性。
具体地,所述导电薄膜9的材料为ITO。
结合图1,所述栅极线G用于开启第一充电TFT T1、第二充电TFT T2、与放电TFTT3,第一充电TFT T1与第二充电TFT T2这两个TFT主要将数据线D传输的数据信号写入对应的两个相邻像素进行充电,放电TFT T3的源极S3、漏极D3分别电性连接第二充电TFT T2的漏极D2、与电位较低的公共电压线Com,将与第二充电TFT T2电性连接的像素的电荷导出以拉低该像素的电位,使得该两个相邻像素的电位不同。
进一步地,所述第一通孔V1与第二通孔V2的开口形状均呈矩形或圆形。所述第一通孔V1的开口尺寸a1大于5um;所述第二通孔V2的开口尺寸a2大于5um。
为了保证所述第二通孔V2与所述第一通V1之间具有足够的横向间距,阻挡对TFTT3的漏极D3下方的半导体有源层5进行刻蚀,优选所述第一通孔V1距第三漏极D3位于第一通孔V1与第二通孔V2之间的边界的距离b1大于4um;所述第二通孔V2距第三漏极D3位于第一通孔V1与第二通孔V2之间的边界的距离b2大于4um。
综上所述,本发明的TFT阵列基板结构,在钝化绝缘层上设置第一通孔,在钝化绝缘层与栅极绝缘层上设置第二通孔,且所述第一通孔与第二通孔沿横向间隔设置,在所述第一通孔内、第二通孔内、及第一通孔与第二通孔之间沉积用于连接第三漏极与公共电压线的导电薄膜;由于第三漏极的金属断面与半导体有源层的断面均被钝化绝缘层覆盖,在钝化绝缘层的保护作用下,第三漏极与半导体有源层界面处及半导体有源层与栅极绝缘层的界面处不会出现倒角,从而能够防范导电薄膜发生断裂及接触不良的风险,使放电TFT与公共电压线之间的连接可靠,提升TFT阵列基板的良率及其信赖性。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (5)
1.一种TFT阵列基板结构,其特征在于,包括自下至上依次层叠设置的第一金属层、栅极绝缘层(3)、半导体有源层(5)、第二金属层、及钝化绝缘层(8);
所述TFT阵列基板结构具有多个呈阵列式排布的像素区域,在纵向相邻的两像素区域内,所述第一金属层包括沿横向延伸的公共电压线(Com)、及栅极线(G),所述第二金属层包括沿纵向延伸的数据线(D)、与所述数据线(D)连接的第一源极(S1)、与所述数据线(D)连接的第二源极(S2)、与所述第一源极(S1)相对设置的第一漏极(D1)、与所述第二源极(S2)相对设置的第二漏极(D2)、与所述第二漏极(D2)连接的第三源极(S3)、及与所述第三源极(S3)相对设置的第三漏极(D3);所述钝化绝缘层(8)覆盖第二金属层、半导体有源层(5)、与栅极绝缘层(3);
所述钝化绝缘层(8)上设有贯穿该钝化绝缘层(8)的第一通孔(V1),所述第一通孔(V1)暴露出第三漏极(D3)的部分表面;所述钝化绝缘层(8)与栅极绝缘层(3)上设有贯穿该钝化绝缘层(8)与栅极绝缘层(3)的第二通孔(V2),所述第二通孔(V2)暴露出公共电压线(Com)的部分表面;所述第一通孔(V1)与第二通孔(V2)沿横向间隔设置;所述第一通孔(V1)内、第二通孔(V2)内、及第一通孔(V1)与第二通孔(V2)之间沉积有用于连接第三漏极(D3)与公共电压线(Com)的导电薄膜(9);
所述栅极线(G)、第一源极(S1)、与第一漏极(D1)形成第一充电TFT(T1),所述栅极线(G)、第二源极(S2)、与第二漏极(D2)形成第二充电TFT(T2),所述栅极线(G)、第三源极(S3)、与第三漏极(D3)形成放电TFT(T3);
所述第一漏极(D1)连接一像素电极(P1),所述第二漏极(D2)连接另一像素电极(P2);
所述第一通孔(V1)距第三漏极(D3)位于第一通孔(V1)与第二通孔(V2)之间的边界的距离(b1)大于4um;
所述第二通孔(V2)距第三漏极(D3)位于第一通孔(V1)与第二通孔(V2)之间的边界的距离(b2)大于4um。
2.如权利要求1所述的TFT阵列基板结构,其特征在于,所述第一通孔(V1)与第二通孔(V2)的开口形状均呈矩形或圆形。
3.如权利要求2所述的TFT阵列基板结构,其特征在于,所述第一通孔(V1)的开口尺寸(a1)大于5um。
4.如权利要求2所述的TFT阵列基板结构,其特征在于,所述第二通孔(V2)的开口尺寸(a2)大于5um。
5.如权利要求1所述的TFT阵列基板结构,其特征在于,所述栅极绝缘层(3)与钝化绝缘层(8)的材料均为氮化硅;所述导电薄膜(9)的材料为氧化铟锡。
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