CN107202977A - A kind of total system and software design approach based on VPX platforms - Google Patents
A kind of total system and software design approach based on VPX platforms Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4004—Means for monitoring or calibrating of parts of a radar system
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- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
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Abstract
The invention discloses a kind of total system and software design approach based on VPX platforms, including the backboard provided with multiple slots, the system is the primary and secondary type structure based on standard VPX buses, including motherboard and daughter board, wherein described motherboard is Fabric Interface plate, the daughter board is expansion interface plate, and motherboard and daughter board are attached by XMC connectors, and motherboard and daughter board pass through X4 SRIO bus communications；The multiple slot can patch a number of other boards, and the backboard realizes motherboard in the total system, the communication of daughter board and other boards；The motherboard, daughter board double-core ARM CortexTMA9 processors PS runs VxWorks real time operating system.The total system of the present invention possesses abundant extended capability, the application demand of different scenes can be met by changing the daughter board of difference in functionality, system has very strong flexibility, it is applied widely, i.e. module realizes " shelf ", can be according to total system of the application demand fast construction for specific guidance application background.
Description
Technical field
The invention belongs to digital signal processing technique field, and in particular to a kind of total system based on VPX platforms
And software design approach.
Background technology
With being continually changing for precise guidance aerocraft system task and working environment demand, to different guidance systems
Total system generalization, miniaturization, the requirement of scalability it is more and more urgent.
Realized more than traditional total system using DSP+FPGA framework, FPGA mainly completes interface and sequential control
System, DSP mainly completes the realization of Row control and complicated algorithm.The placement-and-routing of board main process task chip and data exchange process
It is relatively complicated.DSP is when carrying out multiple task management, it is necessary to set a large amount of interrupt registers, task scheduling dumb, real-time
Property is poor.Total system is often designed for the application demand of certain specific guidance system, the hardware cost phase of system architecture
To higher, application environment adaptability and expandability are poor.
VPX be by VITA organize to set up it is highly reliable under adverse circumstances to meet, high bandwidth requirement it is of future generation senior
Calculating platform standard, intermodule defines SRIO, PCI Express, Fobre Channel, InfiniBand, Hyper-
The high-speed serial bus such as transport, 10Gb Ethernet, transmission rate is up to 30Gb double-core ARM CortexTM- A9 processors
PS, and with superpower data-handling capacity, therefore the general ruggedized computer based on VPX frameworks is readily applicable to essence of new generation
The data handling system of true guided flight vehicle.
The content of the invention
For the shortcoming and defect technically faced, it is an object of the invention to provide a kind of synthesis based on VPX platforms
Processing system, including the backboard provided with multiple slots, it is characterised in that the system is the mother baby plate based on standard VPX buses
Framework, including motherboard and daughter board, wherein the motherboard is Fabric Interface plate, the daughter board is expansion interface plate, motherboard and daughter board
It is attached by XMC connectors, motherboard and daughter board pass through X4SRIO bus communications；The multiple slot can patch a number of other
Board, the backboard realizes the communication of motherboard in the total system, daughter board and other boards；
The Fabric Interface plate is based on motherboard ZYNQ-7000 processors, motherboard SOC and SRIO exchange chips and ether
Net exchange chip, is mainly used in realizing the data exchange and Comprehensive Control of whole system, and the motherboard ZYNQ-7000 processors are
FPGA+ARM frameworks, motherboard double-core ARM CortexTM- A9 processors PS and motherboard FPGA PL are integrated into an independent core
On piece, motherboard double-core ARM Cortex are realized by internal AXI busesTM- A9 processors PS and motherboard FPGA PL height
Fast data communication；The motherboard SOC be FPGA+ARM frameworks, primary interface include motherboard SRIO, MLVDS, SGMII,
JTAG, I2C, QSPI, PMBUS, CAN, motherboard RS422；
The expansion interface plate is the expansion interface daughter board of Switching Module, and the expansion interface plate is based on daughter board ZYNQ-
7000 processors and daughter board SOC, are mainly used in realizing to Switching Module progress Interface Expanding, the daughter board ZYNQ-7000
Processor is FPGA+ARM frameworks, daughter board double-core ARM CortexTM- A9 processors PS and daughter board FPGA PL are integrated into one
On individual independent chip, daughter board double-core ARM Cortex are realized by internal AXI busesTM- A9 processors PS and daughter board, which may be programmed, patrols
Collect PL high-speed data communication；The daughter board SOC be FPGA+ARM frameworks, primary interface include daughter board SRIO,
CameraLink, 1553B and daughter board RS422；
Motherboard, daughter board double-core ARM in motherboard ZYNQ-7000 processors and daughter board the ZYNQ-7000 processors
CortexTM- A9 processors PS and motherboard, the software of daughter board FPGA PL operations are carried out according to interface type and disposal ability
Task is divided, and can carry out multi-task scheduling and calculate node dynamically distributes；
The motherboard, daughter board double-core ARM CortexTM- A9 processors PS runs VxWorks real time operating system.
Preferably, the motherboard, daughter board double-core ARM CortexTM- A9 processors PS and motherboard, daughter board FPGA
The software of PL operations writes different content programming to realization in the system according to the interface type and disposal ability of the system
The system is reconstructed on demand.
Alternatively, the total system passes through institute also by many slot backboard connection universal signal-processing boards
The external optical detector of CameraLink interfaces is stated, optical navigation system is built, for the integrated treatment of optical guidance, has realized
The Row control and signal transacting of whole optical navigation system；
The general signal processing module uses the processing framework of the polycaryon processor of multi-DSP 6678.
Alternatively, the total system also passes through many slot backboard connecting multi-channel AD/DA plates and general letter
Number process plate, and by external antenna front end, build radar guidance system, realize the Row control of complete radar guidance system
And signal transacting；
The multichannel AD/DA plate integrated multi-channel AD/DA and FPGA processor.
Foregoing a kind of software design approach of the total system based on VPX platforms, it is characterised in that described
Total system software carries out task division according to the interface type and disposal ability of the total system and carried out many
Task scheduling and calculate node dynamically distributes, carry out complicated Row control, algorithm can the part of parallelization computing can combine
Motherboard, daughter board FPGA PL resource service condition and motherboard, daughter board double-core ARM CortexTM- A9 processors PS place
Algorithm is split into different submodules and cooperates with computing by both by reason ability, passes through motherboard, daughter board double-core ARM CortexTM-A9
Interacting for high-speed interface intermediate result between processor PS and motherboard, daughter board FPGA PL, meets the integrated treatment
The real-time of system simultaneously reduces the demand that algorithm realizes difficulty, lifts process performance.
Specifically, the total system software includes realizing and control system, antenna front ends, telemetry system, data
Communication between tape deck and the other boards of VPX platforms, in addition to realize command analysis and appointing that response, overall procedure are controlled
It is engaged in, correspondingly the total system software includes and control system communication module and antenna front ends communication module and remote measurement
System communication module and data recording equipment communication module and other board communication modules：
With control system communication module, total system software is led to control system by USB
Letter；Daughter board FPGA PL mainly realize EBI control task and with daughter board double-core ARM Cortex in pieceTM- A9 processing
Data interaction between device PS；Daughter board double-core ARM CortexTM- A9 processors PS mainly realize Data Format Transform and with piece
Daughter board FPGA PL data interactions, the SRIO message that the valid data received are packaged into agreement specific length is sent to mother
Through sub in piece after packet extraction in plate ZYNQ-7000 processors, the SRIO message that motherboard ZYNQ-7000 processors are sent
Plate FPGA PL control interface chips are sent to control system；Motherboard FPGA PL mainly realizes SRIO EBIs
Control task and motherboard FPGA PL and motherboard double-core ARM CortexTMData interaction between-A9 processors PS；Motherboard
Double-core ARM CortexTM- A9 processors PS mainly realizes instruction parsing and according to instruction analysis result, performs template data and adds
Carry, real-time parameter is resolved and distributed, communication process control, completes informix and repeat-back workflow；Motherboard double-core ARM
CortexTMData interaction in-A9 processors PS completions simultaneously and piece between motherboard FPGA PL, by command response information
The SRIO message for being packaged into agreement specific length is sent to daughter board ZYNQ-7000 processors through motherboard FPGA PL in piece；
With antenna front ends communication module, total system software uses universal serial bus communications with antenna front ends, adopted
Use HDLC communication protocols；Motherboard double-core ARM CortexTM- A9 processors PS is program control according to ensemble stream according to command analysis result
System and antenna front ends are communicated, and command frame are sent to antenna front ends by motherboard FPGA PL in piece, by what is received
Effective information is extracted in the command response frame that antenna front ends are returned, overall procedure control is completed according to antenna front ends work schedule,
Flow will be packaged into bus message and return to control system after informix after the completion of performing；Motherboard FPGA PL is realized and day
The HDLC protocol of line front end communication, by motherboard double-core ARM CortexTMThe command frame that-A9 processors PS is sent is according to HDLC protocol
Antenna front ends are sent to, it is double that the command response frame that antenna front ends are returned according to HDLC protocol is sent to motherboard by internal interface
Core ARM CortexTM- A9 processors PS carries out data frame Effective judgement and information extraction；
With telemetry system communication module, total system software is led to telemetry system by USB
Letter, using HDLC communication protocols；Daughter board FPGA PL realizes the HDLC protocol communicated with telemetry system, receives and parses through distant
The claim frame that examining system is sent according to HDLC protocol timing；Daughter board FPGA PL will pass through daughter board double-core ARM CortexTM-
The data that are passed down by remote measurement are stamped after time scale information and given according to HDLC protocol to distant the need for A9 processors PS processing is obtained
Examining system, if daughter board double-core ARM CortexTM- A9 processors PS processing then passes down telemetry frame without the data for needing to pass down
Only include complete zero frame of time scale information；
With data recording equipment communication module, total system software is led to data recording equipment by Ethernet
Letter, using UDP communication protocols；Motherboard ZYNQ-7000 processor RGMII interfaces realize that SGMII connects with RGMII by PHY chip
It is connected after mouth conversion with Ethernet switching chip；Motherboard double-core ARM CortexTM- A9 processors PS passes through Ethernet exchanging core
The communication with data recording equipment is realized after piece route；After the work of total system distribution, when receiving what other boards were sent
After DoorBell notifies that a frame recording data are sent completely, motherboard double-core ARM CortexTMDDR3 is delayed in-A9 processors PS controls
The order that record data and corresponding auxiliary information, the control system deposited are sent is sent to data recording equipment according to udp protocol；
With other board communication modules, the total system of total system running software passes through with other boards
VPX platforms backboard connection, between total system and other boards, and between other boards it is total by SRIO high speeds
Line completes communication；Motherboard double-core ARM CortexTM- A9 processors PS mainly completes SRIO bus data memory allocations, root
Data are read from DDR3 according to the SRIO addresses and DoorBell types that receive data and complete data forwarding and data processing；Motherboard
FPGA PL mainly complete SRIO Interface Controllers and with motherboard double-core ARM CortexTM- A9 processors PS data interaction,
According to motherboard double-core ARM CortexTMThe address space of-A9 processors PS distribution controls the plug-in of the data storage that will be received
In DDR3 memories；Motherboard double-core ARM CortexTM- A9 processors PS according to overall procedure control will need to be sent to it is corresponding its
The data of its board are sent to SRIO exchange chips via motherboard FPGA PL, and SRIO exchange chips are according to source ID and target
Pass through and sent by VPX platform back planes to corresponding other boards after ID routes.
Alternatively, the total system software also include image compression module, motherboard ZYNQ-7000 processors according to
The SRIO addresses and DoorBell types for receiving data judge to pass the view data for receiving other boards transmissions through SRIO buses
Deliver to daughter board ZYNQ-7000 processors；Daughter board double-core ARM CortexTM- A9 processors PS carries out the view data received
After the completion of piecemeal processing, image block, the interrupt requests sent according to daughter board FPGA PL in piece are according to this by view data
Block sends to daughter board FPGA PL and carries out second order Daubechies5/3 lifting wavelet transforms；The formation of single order wavelet transformation
LH1, HL1 subband and HH2, LH2, HL2, LL2 subband of second order wavelet transformation formation are carried out at quantization using different quantization steps
Daughter board double-core ARM Cortex in piece are sent to after reasonTM- A9 processors PS；Daughter board double-core ARM CortexTM- A9 processors PS
Each subband wavelet coefficient is encoded using spiht algorithm.
Alternatively, the total system software also includes data volume frame module, daughter board double-core ARM CortexTM-A9
Processor PS by compression of images bit stream data increase compressed bit stream frame head, image block number, spiht algorithm parameter, code stream length and
Bit stream data is packaged into compressed bit stream data frame；The inertial guidance data received during imaging is increased and packed after frame head and frame number information
Into inertial guidance data frame；The algorithm that the other boards received are sent runs intermediate result, system core status information, Qi Tafu
State-detection data frame is packaged as after the increase such as supplementary information frame head, data length information.
Alternatively, the total system software also includes BIT detection modules.
A kind of total system based on VPX platforms of the present invention, for female, daughter board framework based on standard VPX buses,
Motherboard be Fabric Interface plate, daughter board be expansion interface plate, motherboard be based on motherboard ZYNQ-7000 processors, motherboard SOC and
SRIO exchange chips and Ethernet switching chip, daughter board are based on daughter board ZYNQ-7000 processors and daughter board SOC；Motherboard, son
Plate ZYNQ-7000 processors are the SOC of Xilinx a new generations, double-core ARM CortexTM- A9 processors PS's and Xilinx
FPGA PL is integrated on an independent chip, and double-core ARM CORTEX are realized by internal AXI busesTM- A9 processors
PS and FPGA PL high-speed data communication, i.e. daughter board are the Interface Expanding of system, possess abundant extended capability, can be with
The application demand of different scenes is met by changing the daughter board of difference in functionality, while system can also be realized by programming different software
System reconstruct, system has very strong flexibility, applied widely, i.e., module realizes " shelf ", can be fast according to application demand
Speed builds the total system for specific guidance application background.For example, total system+general signal processing module is constituted
The Comprehensive Signal Processing system of optical guidance system, optical navigation system is constituted by the external optical detector of CameraLink interfaces
System, can meet the application demand of current optical guidance system precise guidance aircraft platforms.
The system and software design approach versatility of the present invention is good.General VPX platforms are relied on, using modularized design,
Specifically include with antenna front ends communication module, with control system communication module, with telemetry system communication module, filled with data record
Put communication module, frame module etc. is compiled with other board communication modules, image compression module, data, software function module can cut,
The portable strong, Function Extension of module is convenient, disclosure satisfy that precise guidance aircraft VPX platforms at present and follow-up function extension is comprehensive
Close the demand of information processing.
The system and software design approach operational efficiency of the present invention is high.Total system running software is in female, daughter board
On ZYNQ-7000 processors, ZYNQ-7000 processors use double-core ARM+FPGA frameworks, have gathered the advantage of two kinds of processors.
Double-core ARM scheduling and operational capability based on VxWorks real time operating system are strong, mainly complete command analysis, ensemble stream program control
System, image block and SPIHT encoding operations, data compile the functions such as frame.FPGA interface is controlled and real-time operation ability is strong, main complete
Into functions such as Interface Controller, Data Format Transform, HDLC protocol, second order Daubechies5/3 lifting wavelet transforms, give full play to
The advantage of processor cores framework, software can carry out collaborative design, and data are between female, daughter board or ZYNQ-7000 processor (cores
Piece) in interaction, software operation efficiency is high.
The system and software design approach reliability of the present invention is high.Running software is in Fabric Interface plate and expansion interface plate
On ZYNQ-7000 processors, software obtained by external interface after data completed in chip data parsings, data transfer, in
Between result interaction etc., female, daughter board be in same metal structure component and in board, between different boards, female, daughter board component with
The data interaction of other boards is relative to be reduced, and reduces the probability disturbed by electromagnetic environment, effectively improves the reliable of software execution
Property and antijamming capability.
The system and software design approach small volume of the present invention.Expansion interface plate and Fabric Interface plate are female, daughter board structure,
Female, daughter board is connected by XMC components, is loaded in mixture as same component.Motherboard and daughter board mainly enter row information by SRIO buses and handed over
Mutually, integrated information processing each functional module of software is separately operable in the ZYNQ-70000 processors (chip) of daughter board and motherboard,
Component hardware small volume, simple in construction, integrated level is high, be easy to safeguard.
The system and software design approach of the present invention provides a kind of image compression algorithm based on ZYNQ-7000 processors
Implementation method, carries out modularization segmentation, the submodule after segmentation is respectively in FPGA PL and double-core by image compression algorithm
ARM CORTEXTMPerformed in-A9 processors PS.FPGA PL realizes two grades of Daubechies5/3 lifting wavelet transforms, leads to
Prediction and update module multiplexing are crossed, row/column conversion module time-sharing multiplex completes multi-level wavelet transform, realizes software modularity and set
Meter, saves hardware resource.Double-core ARM CORTEXTM- A9 processors PS carries out image block and SPIHT encoding operations, will press
Contracting bit stream data and algorithm parameter are compiled after frame by being passed under telemetry system.Double-core ARM CORTEXTM- A9 processors PS and programmable
Logic PL collaboration computings are so as to the complexity of reduction algorithm realization while compression of images real-time demand is met.
There are polytype interface and and multiple systems in the Software for Design that the system and software design approach of the present invention is provided
Carry out data interaction, using VxWorks real time operating system efficiently in real time multitask kernel complete multitask Real-Time Scheduling from
And complicated overall procedure control is realized, by rationally setting the priority of task to ensure template data loading, real-time parameter solution
Calculation and distribution, high-capacity and high-speed data transfer, command analysis, control communicate with antenna front ends and the other boards of processor, information
The high efficiency of the multi-task schedulings such as comprehensive and command response and the promptness of response.
Brief description of the drawings
Fig. 1 is the hardware platform and interface schema of total system provided in an embodiment of the present invention；
Fig. 2 is motherboard provided in an embodiment of the present invention, daughter board ZYNQ-7000 processor system Organization Charts；
Fig. 3 is 1553B data provided in an embodiment of the present invention packing form；
Fig. 4 is 1553B command analysis flow chart provided in an embodiment of the present invention；
Fig. 5 is that HDLC protocol provided in an embodiment of the present invention realizes block diagram；
Fig. 6 is provided in an embodiment of the present invention and antenna front ends communication process sketch；
Fig. 7 is second order wavelet transformation schematic diagram provided in an embodiment of the present invention；
Fig. 8 is second order Daubechies5/3 wavelet transformation general flow charts provided in an embodiment of the present invention；
Embodiment
The embodiment to the present invention is described further below in conjunction with the accompanying drawings.Herein it should be noted that for
The explanation of these embodiments is used to help understand the present invention, but does not constitute limitation of the invention.
Embodiment one
Such as hardware platform and interface schema of the Fig. 1 for the total system of the present invention.General VPX platforms are relied on (i.e. at VPX
Reason machine), using motherboard Fabric Interface plate and daughter board expansion interface plate as carrier, two boards card respectively has ZYNQ-7000 series
Processor, motherboard, the system architecture of daughter board ZYNQ-7000 processors are shown in Fig. 2.The topmost characteristic of ZYNQ-7000 processors
It is by double-core ARM CortexTM- A9 processor PS and Xilinx7 FPGAs PL is integrated on an independent chip.So as to
Ideally it is combined together by ARM processing systems and with Xilinx7 series of programmable logic, creates user unique and strong
Big design.
ZYNQ-7000 processor system double-core ARM CORTEXTM- A9 processors PS parts are except the A9 kernels including double-core
Outside, on-chip memory, external memory interface and a series of abundant I/O peripheral hardwares be further comprises.These peripheral hardwares mainly include
DDR3 particles internal memory, jtag interface, UART interface, USB interface, CAN interface, I2C EBIs, spi bus interface,
XADC interfaces, TF card slots and Ethernet interface etc..And FPGA PL parts then there is provided more preferable flexibility and can
Autgmentability, the logic that it can be customized according to user completes real-time processing and the high-speed transfer of signal.
A kind of total system based on VPX platforms of the present embodiment, including the backboard provided with multiple slots, the system
Unite as female, daughter board framework based on standard VPX buses, including motherboard and daughter board, wherein the motherboard is Fabric Interface plate, it is described
Daughter board is expansion interface plate, and motherboard and daughter board are attached by XMC connectors, and motherboard and daughter board are logical by X4SRIO buses
Letter；The multiple slot can patch a number of other boards, the backboard realize motherboard in the total system, daughter board with
The communication of other boards；
Fabric Interface plate is based on motherboard ZYNQ-7000 processors, motherboard SOC and SRIO exchange chips and Ethernet is handed over
Chip is changed, is mainly used in realizing the data exchange and Comprehensive Control of whole system, the motherboard ZYNQ-7000 processors are FPGA
+ ARM frameworks, motherboard double-core ARM CortexTM- A9 processors PS and motherboard FPGA PL are integrated into an independent chip
On, motherboard double-core ARM Cortex are realized by internal AXI busesTM- A9 processors PS and motherboard FPGA PL high speed
Data communication；The motherboard SOC is the FPGA+ARM frameworks being internally integrated, primary interface include motherboard SRIO, MLVDS,
SGMII, JTAG, I2C, QSPI, PMBUS, CAN, motherboard RS422；
Expansion interface plate is the expansion interface daughter board of Switching Module, and the board is based on daughter board ZYNQ-7000 processors and son
Plate SOC, is mainly used in realizing to Switching Module progress Interface Expanding, the daughter board ZYNQ-7000 processors are FPGA+
ARM frameworks, daughter board double-core ARM CortexTM- A9 processors PS and Xilinx daughter board FPGA PL are integrated into a list
On only chip, daughter board double-core ARM Cortex are realized by internal AXI busesTM- A9 processors PS and daughter board FPGA PL
High-speed data communication；The daughter board SOC is the FPGA+ARM frameworks being internally integrated, primary interface include daughter board SRIO,
CameraLink, 1553B and daughter board RS422；
Motherboard ZYNQ-7000 processors and motherboard, daughter board double-core ARM Cortex in daughter board ZYNQ-7000 processorsTM-
A9 processors PS and Xilinx motherboard, the software of daughter board FPGA PL operations are carried out according to interface type and disposal ability
Task is divided, and can carry out multi-task scheduling and calculate node dynamically distributes；
Motherboard, daughter board double-core ARM CortexTM- A9 processors PS runs VxWorks real time operating system.
Motherboard, daughter board double-core ARM CortexTMIt is soft that-A9 processors PS and motherboard, daughter board FPGA PL are run
Part according to the interface type and disposal ability of the system write different content programming to realize in the system system by
Need reconstruct.
The total system of the present invention is also by many slot backboard connection universal signal-processing boards, by described
The external optical detector of CameraLink interfaces, builds optical navigation system, for the integrated treatment of optical guidance, realizes complete
Optical navigation system Row control and signal transacting.Current optical guidance system precise guidance aircraft platforms can be met
Application demand)
General signal processing module uses the processing framework of the polycaryon processor of multi-DSP 6678, meets at current high speed signal
The ability need of reason.
Total system also by many slot backboard connecting multi-channel AD/DA plates and general signal processing module, and
By external antenna front end, radar guidance system is built, the Row control and signal transacting of complete radar guidance system is realized,
The application demand of current radar guidance system precise guidance aircraft platforms can be met.Multichannel AD/DA plate integrated multi-channels AD/
DA and FPGA processor, meet the ability need of current igh-speed wire-rod production line.
Embodiment two
The software design approach of a kind of total system based on VPX platforms as described in preceding embodiment one, with this side
The total system software of method design carries out task division according to the interface type and disposal ability of the total system
And task management, and carry out multi-task scheduling and calculate node dynamically distributes, carry out complicated Row control, complicated algorithm
Can the part of parallelization computing can combine motherboard, daughter board FPGA PL resource service condition and motherboard, daughter board double-core ARM
CortexTMAlgorithm is split into different submodules and cooperates with computing by both by-A9 processors PS disposal ability, by motherboard,
Daughter board double-core ARM CortexTMHigh-speed interface intermediate result between-A9 processors PS and motherboard, daughter board FPGA PL
Interaction, meet the real-time of the total system and reduce the demand that algorithm realizes difficulty, lifted process performance.
The software of the total system of the present invention includes realizing that with control system, antenna front ends (be phase in the present embodiment
Control battle array front end), telemetry system, the communication between data recording equipment and the other boards of VPX processors, in addition to realize command analysis
With response, overall procedure control task, correspondingly the total system software include with control system communication module, with
Antenna front ends communication module, with telemetry system communication module, communicate mould with data recording equipment communication module, with other boards
Block：
With control system communication module, total system software is led to control system by USB
Letter；Daughter board FPGA PL mainly realize EBI control task and with daughter board double-core ARM Cortex in pieceTM- A9 processing
Data interaction between device PS；Daughter board double-core ARM CortexTM- A9 processors PS mainly realize Data Format Transform and with piece
Daughter board FPGA PL data interactions, the valid data received are packaged into agreement specific length, and (the present embodiment is 80 bytes
It is long) SRIO message be sent to motherboard ZYNQ-7000 processors, in the SRIO message that motherboard ZYNQ-7000 processors are sent
Packet extract after sent through daughter board FPGA PL control interface chips in piece to control system；Motherboard FPGA
PL mainly realizes SRIO EBIs control task and motherboard FPGA PL and motherboard double-core ARM CortexTM- A9 processing
Data interaction between device PS；Motherboard double-core ARM CortexTM- A9 processors PS mainly realizes instruction parsing and solved according to instruction
Result is analysed, template data loading, real-time parameter is performed and resolves and distribute, communication process control, completing informix should with instruction
Answer workflow；Motherboard double-core ARM CortexTMIn-A9 processors PS completions simultaneously and piece between motherboard FPGA PL
Data interaction, command response Information encapsulation is sent into the SRIO message of agreement specific length through motherboard FPGA PL in piece
To daughter board ZYNQ-7000 processors；
With antenna front ends communication module, total system software uses universal serial bus communications with antenna front ends, adopted
Use HDLC communication protocols；Motherboard double-core ARM CortexTM- A9 processors PS is program control according to ensemble stream according to command analysis result
System and antenna front ends are communicated, and command frame are sent to antenna front ends by motherboard FPGA PL in piece, by what is received
Effective information is extracted in the command response frame that antenna front ends are returned, overall procedure control is completed according to antenna front ends work schedule,
Flow will be packaged into bus message and return to control system after informix after the completion of performing；Motherboard FPGA PL is realized and day
The HDLC protocol of line front end communication, by motherboard double-core ARM CortexTMThe command frame that-A9 processors PS is sent is according to HDLC protocol
Antenna front ends are sent to, it is double that the command response frame that antenna front ends are returned according to HDLC protocol is sent to motherboard by internal interface
Core ARM CortexTM- A9 processors PS carries out data frame Effective judgement and information extraction；
With telemetry system communication module, total system software is led to telemetry system by USB
Letter, using HDLC communication protocols；Daughter board FPGA PL realizes the HDLC protocol communicated with telemetry system, receives and parses through distant
The claim frame that examining system is sent according to HDLC protocol timing；Daughter board FPGA PL will pass through daughter board double-core ARM CortexTM-
The data that are passed down by remote measurement are stamped after time scale information and given according to HDLC protocol to distant the need for A9 processors PS processing is obtained
Examining system, if daughter board double-core ARM CortexTM- A9 processors PS processing then passes down telemetry frame without the data for needing to pass down
Only include complete zero frame of time scale information；
With data recording equipment communication module, total system software is led to data recording equipment by Ethernet
Letter, using UDP communication protocols；(interface is intermediary interface to motherboard ZYNQ-7000 processor RGMII interfaces, is not that outside connects
Mouthful) realize SGMII with being connected after RGMII interface conversions with Ethernet switching chip by PHY chip；Motherboard double-core ARM
CortexTM- A9 processors PS realizes the communication with data recording equipment after being route by Ethernet switching chip；Integrated treatment system
After electricity work under unified central planning, after the DoorBell for receiving other boards transmissions notifies that a frame recording data are sent completely, motherboard double-core
ARM CortexTM- A9 processors PS controls send the DDR3 record datas cached and corresponding auxiliary information, control system
Order is sent to data recording equipment according to udp protocol；
With other board communication modules, the total system of total system running software passes through with other boards
VPX platforms backboard connection, between total system and other boards, and between other boards it is total by SRIO high speeds
Line completes communication；Motherboard double-core ARM CortexTM- A9 processors PS mainly completes SRIO bus data memory allocations, root
Data are read from DDR3 according to the SRIO addresses and DoorBell types that receive data and complete data forwarding and data processing；Motherboard
FPGA PL mainly complete SRIO Interface Controllers and with motherboard double-core ARM CortexTM- A9 processors PS data interaction,
According to motherboard double-core ARM CortexTMThe address space of-A9 processors PS distribution controls the plug-in of the data storage that will be received
In DDR3 memories；Motherboard double-core ARM CortexTM- A9 processors PS according to overall procedure control will need to be sent to it is corresponding its
The data of its board are sent to SRIO exchange chips via motherboard FPGA PL, and SRIO exchange chips are according to source ID and target
Pass through and sent by VPX platform back planes to corresponding other boards after ID routes.
Total system software also includes image compression module, and motherboard ZYNQ-7000 processors are according to reception data
SRIO addresses and DoorBell types judge that will receive view data that other boards send is sent to daughter board through SRIO buses
ZYNQ-7000 processors；Daughter board double-core ARM CortexTMThe view data received is carried out piecemeal processing by-A9 processors PS,
After the completion of image block, video data block is sent to son according to this according to the interrupt requests sent of daughter board FPGA PL in piece
Plate FPGA PL carries out second order Daubechies5/3 lifting wavelet transforms；LH1, HL1 subband of single order wavelet transformation formation
Piece is sent to after carrying out quantification treatment using different quantization steps with HH2, LH2, HL2, LL2 subband of second order wavelet transformation formation
Interior daughter board double-core ARM CortexTM- A9 processors PS；Daughter board double-core ARM CortexTM- A9 processors PS uses spiht algorithm
Each subband wavelet coefficient is encoded.
Total system software also includes data and compiles frame module, daughter board double-core ARM CortexTM- A9 processors PS will scheme
As compressed bit stream data increase compressed bit stream frame head, image block number, spiht algorithm parameter, code stream length and bit stream data packing
Into compressed bit stream data frame；Inertial guidance data is packaged into after the inertial guidance data received during imaging is increased into frame head and frame number information
Frame；Algorithm operation intermediate result, system core status information, other auxiliary informations that the other boards received are sent etc. increase
Plus state-detection data frame is packaged as after frame head, data length information.
Total system software also includes BIT detection modules.
During specifically used total system of the invention, first complete initialization after system electrification, each functional module according to
Aerocraft system WorkFlow Managerment works.In the present embodiment, total system is constituted, and BIT detects implementation process and comprehensive
With control system communication module and antenna front ends communication module and telemetry system communication module and its in conjunction processing system software
Its board communication module, with data recording equipment communication module, image compression module, data compile frame module realize that its function is held
Capable action (process) is described as follows.
1. total system is constituted
Total system includes Fabric Interface plate and expansion interface plate, and expansion interface plate and Fabric Interface plate are female, son
Hardened structure, is connected by XMC connectors, is mainly entered between female, daughter board and each (function) board of processor by X4SRIO buses
Row communication, traffic rate is 12.5Gb double-core ARM CortexTM- A9 processors PS.
The fpga chip of Fabric Interface plate selects ZYNQ-7000 family chip XC7Z015, the plug-in DDR3 memories of processor
And FLASH memory, 4 road MLVDS and 1 road LVDS interface are realized by interface chip, 1 road X4SRIO external interfaces use FPGA
GTP interfaces realize.SRIO exchange chips select the 80HC double-core ARM CORTEX of Integrated Device Technology, Inc.TM- A9 processors
PS1848CRMI, SRIO exchange chip can provide 7 road X4SRIO, wherein 4 roads from VPX connector P1 ports draw, 1 road from
VPX connector P2 ports are drawn, and 1 road is drawn from XMC connectors, and remaining 1 tunnel is communicated with FPGA.SOC processor can
Pass through I2C buses dynamically manage the SRIO nodes of exchange chip, and update routing table, and exchange chip completes external 7 road X4SRIO
Function of exchange.Ethernet switching chip selects the VSC7428XJG of Vitesse companies, using the teaching of the invention it is possible to provide 6 groups of SGMII interfaces, 4 groups
Medium Dependent Interface.5 groups in 6 groups of SGMII interfaces are connected by VPX connector P2 ports, and another group of SGMII interface can pass through PHY cores
Piece 88E1111 realizes SGMII and RGMII interface conversions, is connected to fpga chip.3 groups in 4 groups of Medium Dependent Interfaces pass through transformer
Carry out isolation and be connected to high speed mixed loading connector, remaining one group is connected to VPX connector P2 ports by transformer isolation.SOC
Chip processor can configure exchange chip VSC7428XJG relevant parameters by spi bus.
The fpga chip of expansion interface plate selects ZYNQ-7000 family chip XC7Z015, the plug-in DDR3 memories of processor
And FLASH memory, 1 road 1553B, 1 road CameraLink interfaces and 1 road RS422 interfaces, 1 tunnel are realized by interface chip
X4SRIO external interfaces are realized using FPGA GTP interfaces.1553B bus control units from 8357 HT-61843GB, core
Piece includes independent two channel 4M 1553B Communication Control logics；Internal 8K chaacter memories；Support MT/RT patterns simultaneously.
CameraLink interface chips select DS90CR286AMTD, using Base patterns.RS422 serial ports conversion chip is selected
LTM2881MPY realizes LVCMOS level and RS422 level conversions.Board, which leaves 1 road RS232 serial ports and 1 road Ethernet interface, to be used for
Debugging.
The SOC processor of Fabric Interface plate and expansion interface plate selects Microsemi A2F500M3G chips,
A2F500M3G-1FGG484 chip internals are integrated withCortexTM-M3、3 FPGA, memory, compare
The related functional circuits such as device, AD/DA, chip is divided into micro-controller subsystem, FPGA module, analog interface system and I/O and electricity
4, source part.SOC provides control platform for whole board, completes power supply management and control and system management function.
2.BIT detects implementation process
The Fabric Interface plate ZYNQ-7000 of total system double-core ARM CORTEXTM- A9 processors PS passes through SRIO
Bus receives and parses through the order of control system transmission, after judging the current command for BIT sense commands, ZYNQ-7000 double-core
ARM CORTEXTMBIT sense commands are sent to the SOC on plate by-A9 processors PS by SPI, and SOC passes through again
PMBUS is sent to other boards.SOC on the board of total system and other boards is received after BIT sense commands,
Start to carry out BIT detections to respective board, can obtain the software version of each board in BIT detection process, state of data link,
All kinds of interface communication states, FPGA, DSP, AD, DA, DDR3, FLASH, E2PROM, Ethernet switching chip, SRIO exchange chips
Working condition etc. main chip etc..After the completion of BIT detections, total system is by system BIT detection informations in itself and its
The BIT detection informations of its board are sent after collecting to control system.The status information of each unit passed down by control system, can
The condition managing and Analysis on Fault Diagnosis of carry out system.
3. with the control system communication module course of work
1553B order reception processing flows：
Step 1：The FPGA PL of daughter board ZYNQ-7000 processors receives the 1553B message of control system transmission, will
1553B message passes through FPGA PL and double-core ARM CORTEXTMInternal port between-A9 processors PS is transferred to double-core
ARM CORTEXTM- A9 processors PS.
Step 2：Double-core ARM CORTEXTM1553B message is filled into the SRIO message of 80 bytes by-A9 processors PS, its
Subaddressing " subaddr " that packet (frame) head " 7b8c ", 1553B packets are sent to, (i.e. effective byte is long for data length
Degree) " Len ", the packing such as 1553B packets, the remaining bit zero padding of data frame, data packing form is shown in Fig. 3, and this is encapsulation
Outer layer frame head, 1553B packets also have a frame head, and two frame heads all judge effectively to be only valid frame.Add receiving terminal SRIO
After the SRIO Message format informations such as port numbers uDestId, receiving terminal mailbox number MailBox, receiving terminal envelope letter
Send to FPGA PL, FPGA PL and sent by SRIO exchange chips route to motherboard ZYNQ-7000 processors.
Step:3：The FPGA PL of motherboard ZYNQ-7000 processors by after the SRIO message received by inside end
Mouth is sent to double-core ARM CORTEX in pieceTM- A9 processors PS.
Step 4：Double-core ARM CORTEXTM- A9 processors PS runs VxWorks real time operating system, registers SRIO message
Call back function Message.When receiving SRIO message, produce software interrupt and perform Message.Message responses are interrupted, and are read
SRIO interface data, is parsed to the instruction that control system is sent, and instruction process of analysis figure is shown in Fig. 4.Command analysis module is first
Semaphore is first obtained, whether the frame head for judging the command frame in order caching is agreement frame head, if agreement frame head is then from order
1553B command words are obtained in frame and CRC check is carried out, correct then performed according to command word content of verification operates and returned accordingly
Response；Bus check order is determined whether if check errors, if bus check order then returns to bus check verification
The corresponding error message of mistake BUSCHECK_CRCERROR, gSysErrorStatus assignment, if not bus check order is then
The corresponding error message of gSysErrorStatus assignment.
1553B command response handling processes：
Step 1：The double-core ARM CORTEX of motherboard ZYNQ-7000 processorsTM- A9 processors PS completes instruction and parses and hold
After row corresponding operating, command response is performed.Its by data packet head " 7b8c ", subaddressing (subaddr), data length (Len),
1553B packets etc. are packed, the remaining bit zero padding of data frame, and data packing form is shown in Fig. 3.Receiving terminal SRIO port numbers are added again
By interior after the SRIO Message format informations such as uDestId, receiving terminal mailbox number MailBox, receiving terminal envelope Letter
Portion port is sent to FPGA PL.
Step 2：FPGA PL sends SRIO message to daughter board ZYNQ-7000 by SRIO exchange chips route
Manage device.
Step:3：The FPGA PL of daughter board ZYNQ-7000 processors patrols the SRIO message received by programmable
Collect PL and double-core ARM CORTEXTMInternal port between-A9 processors PS is transferred to double-core ARM CORTEXTM- A9 processors
PS；
Step 4：Double-core ARM CORTEXTM- A9 processors PS runs VxWorks real time operating system, registers SRIO message
Call back function Message.When receiving SRIO message, produce software interrupt and perform Message.Message responses are interrupted, and are read
SRIO interface data, extracts 1553B message and its correspondence length and subaddressing from SRIO message, to 1553B message correspondence
Address sends order, is vector font form as ordered, then to vector font correspondence position 1.
4. with the antenna front ends communication module course of work
Communicate the driving of controlled system command with antenna front ends, when receiving 1553B orders and complete 1553B command analysis
Afterwards, communicated according to overall procedure control with antenna front ends, the 1553B orders of module reception and reply process flow and with
The handling process of control system communication module is identical, and this module is repeated no more.
HDLC protocol data frame format is banner word " 7E "+byte CRC check code+banner word of valid data+two " 7E ",
Global clock is the input service clock of module, and HDLC protocol realizes that block diagram is shown in Fig. 5, and HDLC protocol receiving processing module module is real
Existing flow is as follows：
Step 1：Software receives outside input clock RxCLk and serial data RxD, and shift register will according to serial clock
Sampling serial data feeding shift register constantly carries out shifting processing.
Step 2：Shift register will export parallel data feeding banner word detection and delete Z-operation module.Module is entered first
The detection of line flag position, when detecting banner word " 7E " and continuous two bytes are not all " 7E ", data frame is effective.Detection two
Data in the middle of individual banner word " 7E ", delete continuous 5 ' 1 ' 1 ' 0 ' inserted afterwards, recover original data content.
Step 3：HDLC protocol receiving processing module completes the synchronization process of the signal of serial and concurrent clock zone, CRC schools
Module is tested to delete completion the progress CRC check of the data after Z-operation and export corresponding check results.
Step 4：Data carry out serial/parallel conversion after CRC check module and send into order caching progress data buffer storage, defeated
Go out reception state signal and wait the enable signal that continues, HDLC protocol data are exported finally by DAT_O.
HDLC protocol transmission flow：
Step 1：Software writes parallel data by DAT_I to HDLC protocol module, and parallel data feeding sends caching mould
Block carries out data buffer storage.After the completion of data buffer storage, read according to the state control data of the other modules of transmission flow by byte
And complete parallel/serial conversion.
Step 2：HDLC protocol sends the synchronization of the signal of processing and the serial and concurrent clock zone of zero insertion operation module completion
Processing.Meanwhile, 1 ' 0 ' is inserted afterwards to continuous 5 ' 1 ' in serial data completes the operation of data zero insertion.
Step 3：The CRC check code that CRC generation module carries out two bytes of CRC check and generation to data is attached to after data
Send.
Step 4：Indicate that word generator controls frame head and postamble in data frame respectively to insert 1 banner word according to transmission flow
“7E”。
Step 5：Send selector according to the control signal of protocol module selection send valid data, CRC check code or
Banner word.
Step 6：Shift register is responsible for the serial data of input constantly shifting output data by shift register
TxD, while exporting serial clock TxCLK.
See Fig. 6 with antenna front ends communication process sketch, detailed process is as follows：
Step 1：Motherboard ZYNQ-7000 processor double-core ARM CORTEXTM- A9 processors PS receives 1553B orders and complete
Into after command analysis, when judging to need to be communicated with antenna front ends.Double-core ARM CORTEXTM- A9 processor PS function moulds
Block obtains semaphore first.The instruction sent according to the control system received and the work schedule of combination antenna front ends, according to logical
Believe that agreement sets antenna front ends to instruct, double-core ARM CORTEXTM- A9 processors PS sends command frame to can by internal port
Programmed logic PL simultaneously notifies FPGA PL to read the data in caching by register.
Step 2：FPGA PL reads the data in caching and sends a command to antenna front ends according to HDLC protocol.
Step 3：When motherboard ZYNQ-7000 processor FPGAs PL receives the command response of antenna front ends return,
The reception of HDLC protocol module gets out signal effectively, and FPGA PL controls will read number in the caching RAM of protocol module
According to deposit FPGA PL and double-core ARM CORTEXTM- A9 processors PS internal interface, which caches in RAM and sends interruption, to be led to
Know double-core ARM CORTEXTM- A9 processors PS reads data.
Step 4：Antenna front ends return to acknowledgement frame and sent by FPGA PL to double-core ARM CORTEXTM- A9 processing
Device PS, judges whether acknowledgement frame CRC check is correct if antenna front ends return to response, judges that antenna front ends response has if correct
Effect, buffering area correspondence position is inserted by antenna front ends command response, if CRC check mistake or not returning at the appointed time
Response, then judge whether to have sent three times, if unresponsive or check errors are determined as communication failure, buffering area phase continuous three times
Position is answered to insert corresponding error condition.
Step 5：Double-core ARM CORTEXTM- A9 processors PS judges antenna front ends state according to response, according to overall procedure
Control command communicates, and packing response message returns to control system after the completion of all instructions are performed.
5. with the telemetry system communication module course of work
Reception processing flow is asked in remote measurement：
After the FPGA PL of daughter board ZYNQ-7000 processors receives the claim frame of telemetry system transmission, from HDLC
Read requests frame data and judge claim frame validity in protocol module caching, after judgment frame is effective, triggering telemetry hair
Flow is sent to start working.
Telemetry sends handling process：
After remote measurement transmission flow starts, first determine whether that telemetry sends whether caching is empty, when caching is not read for space-time
Take the data in caching and increase communication protocol frame head, stamp after time scale information and to be sent to HDLC protocol module by byte, pass through
RS422 interfaces are sent to telemetry system.Meanwhile, constantly detection sends remaining byte number in caching, when remainder bytes in caching
Pass through interrupt notification double-core ARM CORTEX when number is less than the threshold value setTM- A9 processors PS retransmits a frame data；Work as transmission
Cache as space-time, down-transmitting data is complete zero frame comprising communication protocol frame head, time scale information.
6. with other board communication module courses of work
Data receiver handling process：
Step 1：The double-core ARM CORTEX of ZYNQ-7000 processorsTM- A9 processors PS and FPGA PL can be visited
Ask chip plug-in DDR3.The double-core ARM CORTEX of motherboard ZYNQ-7000 processorsTM- A9 processors PS sends out for other boards
The corresponding DDR3 memory address spaces of the different types of data distribution sent.Motherboard ZYNQ-7000 FPGA PL controls
The data buffer storage for the respective type that will be received is made into the corresponding address spaces of DDR3, respective plate card notifies double by DoorBell
Core ARM CORTEXTM- A9 processor PS data are sent completely.
Step 2：The double-core ARM CORTEX of motherboard ZYNQ-7000 processorsTM- A9 processors PS registration SRIO doorbell readjustments
Function, when receiving SRIO DoorBell, produces software interrupt；DoorBell interrupt service routines processing SRIO's
DoorBell is interrupted, and corresponding data processing is carried out according to the SRIO addresses uSrcID of interrupt source and DoorBell types.Work as judgement
During for view data, control to send SRIO bus of the view data between female, daughter board to daughter board ZYNQ-7000 processing
Device.
Data sending processing flow：
Step 1：The double-core ARM CORTEX of motherboard ZYNQ-7000 processorsTM- A9 processors PS is according to overall procedure control
The data for being sent to corresponding board will be needed to send to FPGA PL and notified by status register by internal port
FPGA PL data are sent completely.
Step 2：The FPGA PL of motherboard ZYNQ-7000 processors completes data buffer storage and data are total according to SRIO
Wire protocol is sent to SRIO exchange chips, and exchange chip is passed through after being route according to ID to be sent to corresponding (work(by VPX processor backboards
Can) board.
7. with the data recording equipment communication module course of work
The double-core ARM CORTEX of motherboard ZYNQ-7000 processorsTM- A9 processors PS registers SRIO doorbell call back functions,
When receiving SRIO DoorBell, software interrupt is produced；In DoorBell interrupt service routines processing SRIO DoorBell
It is disconnected, corresponding data processing is carried out according to the SRIO addresses uSrcID of interrupt source and DoorBell types.When being judged as record data
When, record data is read from DDR3 according to the address space of distribution and passes through gigabit Ethernet with the corresponding auxiliary information of caching
Send to data recording equipment, the 1553B orders that the control system of caching is sent are sent to data record by Ethernet and filled
Put.
8. the image compression module course of work
Step 1：Daughter board ZYNQ-7000 FPGA PL receives the picture number that other boards are sent by SRIO buses
According to rear, according to double-core ARM CORTEXTMThe outside DDR3 cachings of base address space write-in of-A9 processors PS distribution, (function)
Board notifies to be sent completely by DoorBell.
Step 2：Daughter board ZYNQ-7000 double-core ARM CORTEXTM- A9 processors PS registers SRIO doorbell call back functions,
When receiving SRIO DoorBell, software interrupt is produced；In DoorBell interrupt service routines processing SRIO DoorBell
It is disconnected, corresponding data processing is carried out according to the SRIO addresses uSrcID of interrupt source and DoorBell types；When being judged as view data
When being sent completely DoorBell, image block operation is performed, view data is resolved into the image block of 128 × 128 pixel sizes,
1st image block is sent to FPGA PL, data notify FPGA after being sent completely by writing buffer status
PL。
Step 3：FPGA PL detection double-core ARM CORTEXTMIt is effective that-A9 processors PS writes complete status register
Afterwards, read view data and data are completed into second order Daubechies5/3 Lifting Wavelets by byte input wavelet transformation module and become
Change.Second order Daubechies5/3 wavelet transformation schematic diagrames are shown in Fig. 7, and the image block of 128 × 128 pixel sizes carries out single order first
Wavelet transformation generates 4 64 × 64 pixel size subbands of HH1, HL1, LH1 and LL1.LL1 subbands carry out second order wavelet transformation, point
Solution is into 4 32 × 32 pixel size subbands of HH2, HL2, LH2 and LL2.Wavelet transformation module is mainly comprising prediction submodule and more
New submodule, prediction submodule calculates the high fdrequency component H of output image, and module transform realizes prediction submodule function；More
New submodule calculates the low frequency component L of output image, and module transform_L, which is realized, updates submodule function.Data are coordinated to delay
Deposit with address ram calculate, row/column conversion can time-sharing multiplex, so as to realize second order Daubechies5/3 wavelet transformations.Second order is small
Wave conversion and single order wavelet transformation can realize module reuse by row/column parameter configuration.Second order Daubechies5/3 wavelet transformations
General flow chart is shown in Fig. 8.1st step：Data are read by row, 3 row Data duplications is often read and reads 1 the 3rd row data.2nd step：By row use
Even sequence prediction odd sequence obtains high fdrequency component H1, and the function items use transform modules.3rd step：Update even with odd sequence
Sequence obtains low frequency component L1, and the function items use transform_L modules.4th step：Data are read by row to H1 components, often
3 column datas are read to repeat to read 1 the 3rd column data.Respectively HH1 and HL1 are obtained using transform and transform_L modules
Subband.5th step：Data are read by row to L1 components, 3 column datas is often read and repeats to read 1 the 3rd column data.Use respectively
Transform and transform_L modules obtain LH1 and LL1 subbands.6th step：Phase is used to two single order subbands LH1 and HL1
Same quantization step carries out being stored in RAM_h and RAM_v after quantification treatment respectively, and LL1 sub-band components carry out second order wavelet transformation.Two
Level wavelet transformation repeats the step 1-6 of single order wavelet transformation, obtains HH2, HL2, LH2 and LL2 subband.Not reduce picture quality
In the case of as far as possible improve compression ratio, high-frequency sub-band HH1 is not encoded, the quantified places of single order subband LH1 and HL1 of wavelet transformation
RAM_h and RAM_v are buffered into after reason respectively, RAM_a is stored in after the quantified processing of second order sub-band coefficients, wherein relatively being concentrated to energy
Low frequency sub-band use less quantization step, the high-frequency sub-band less to energy uses larger quantization step-length.Caching is completed
Pass through interrupt notification double-core ARM CORTEX afterwardsTM- A9 processors PS reads wavelet coefficient and sends next image block data
Row wavelet transformation.
Step 4：Double-core ARM CORTEXTM- A9 processors PS is received to respond after interruption and interrupted, and reads the coefficient of wavelet transformation
Send into SPIHT coding modules to be completed to encode according to predetermined refining number of times, each subband is encoded successively according to the important order of code stream
Wavelet coefficient, the bit stream data feeding data after compression compile frame module, judge whether coding is completed all image blocks, if not complete
Encoding operation is performed into the wavelet coefficient for then reading next piece of view data.
9. data compile the frame module course of work
Because the code stream length of compression of images is related to picture material, image compression rate is not fixed value.It is distant in order to adapt to
The transmission bandwidth of examining system, sets image minimum compression ratio as 4, excellent when detecting compressed bit stream length and being more than the threshold value of setting
Important code stream is first intercepted to be transmitted.Compression of images code stream addition frame head, image block number, spiht algorithm parameter, code stream length
Compressed bit stream data frame, the double-core ARM CORTEX of daughter board ZYNQ-7000 processors are packaged into bit stream dataTM- A9 processors
The data down transmission interrupt requests that PS is sent according to FPGA PL, are sent to FPGA PL by bit stream data according to this.
The double-core ARM CORTEX of daughter board ZYNQ-7000 processorsTMControl system timing during-A9 processors PS will be imaged
Inertial guidance data frame is packaged as after increase frame head, frame number information after inertial navigation information in the 1553B information of transmission is extracted, according to can compile
The data down transmission interrupt requests that journey logic PL is sent send the data to FPGA PL, by being passed under telemetry system.
The double-core ARM CORTEX of daughter board ZYNQ-7000 processorsTMThe algorithm that-A9 processors PS sends other boards
State is packaged as after the increase such as operation intermediate result, system core status information, other auxiliary informations frame head, data length information
Data frame is detected, FPGA PL is sent the data to according to the FPGA PL data down transmission interrupt requests sent, leads to
Cross and passed under telemetry system.
The present invention is not only limited to above-mentioned embodiment, and persons skilled in the art are according to disclosed by the invention interior
Hold, the present invention can be implemented using other a variety of embodiments, therefore, every design structure and think of using the present invention
Road, does some simple designs for changing or changing, both falls within the scope of protection of the invention.
Claims (10)
1. a kind of total system based on VPX platforms, including the backboard provided with multiple slots, it is characterised in that the system
Unite as the primary and secondary type structure based on standard VPX buses, including motherboard and daughter board, wherein the motherboard is Fabric Interface plate, it is described
Daughter board is expansion interface plate, and motherboard and daughter board are attached by XMC connectors, and motherboard and daughter board are logical by X4SRIO buses
Letter；The multiple slot can patch a number of other boards, the backboard realize motherboard in the total system, daughter board with
The communication of other boards；
The Fabric Interface plate is based on motherboard ZYNQ-7000 processors, motherboard SOC and SRIO exchange chips and Ethernet is handed over
Chip is changed, is mainly used in realizing the data exchange and Comprehensive Control of whole system, the motherboard ZYNQ-7000 processors are FPGA
+ ARM frameworks, motherboard double-core ARM CortexTM- A9 processors PS and motherboard FPGA PL are integrated into an independent chip
On, motherboard double-core ARM Cortex are realized by internal AXI busesTM- A9 processors PS and motherboard FPGA PL high speed
Data communication；The motherboard SOC be FPGA+ARM frameworks, primary interface include motherboard SRIO, MLVDS, SGMII, JTAG,
I2C, QSPI, PMBUS, CAN, motherboard RS422；
The expansion interface plate is the expansion interface daughter board of Switching Module, and the expansion interface plate is based at daughter board ZYNQ-7000
Device and daughter board SOC are managed, is mainly used in realizing to Switching Module progress Interface Expanding, the daughter board ZYNQ-7000 processors
For FPGA+ARM frameworks, daughter board double-core ARM CortexTM- A9 processors PS and daughter board FPGA PL are integrated into one individually
On chip, daughter board double-core ARM Cortex are realized by internal AXI busesTM- A9 processors PS's and daughter board FPGA PL
High-speed data communication；The daughter board SOC be FPGA+ARM frameworks, primary interface include daughter board SRIO, CameraLink,
1553B and daughter board RS422；
Motherboard, daughter board double-core ARM Cortex in motherboard ZYNQ-7000 processors and daughter board the ZYNQ-7000 processorsTM-
A9 processors PS and motherboard, the software of daughter board FPGA PL operations carry out task according to interface type and disposal ability and drawn
Point, multi-task scheduling and calculate node dynamically distributes can be carried out；
The motherboard, daughter board double-core ARM CortexTM- A9 processors PS runs VxWorks real time operating system.
2. the system as claimed in claim 1, it is characterised in that the motherboard, daughter board double-core ARM CortexTM- A9 processors
PS and motherboard, the software of daughter board FPGA PL operations write difference according to the interface type and disposal ability of the system
Content programming is to realizing that the system is reconstructed on demand in the system.
3. system as claimed in claim 1 or 2, it is characterised in that the total system is also carried on the back by many slots
Plate connection universal signal-processing board, by the external optical detector of CameraLink interfaces, builds optical navigation system, uses
In the integrated treatment of optical guidance, the Row control and signal transacting of complete optical navigation system are realized；
The general signal processing module uses the processing framework of the polycaryon processor of multi-DSP 6678.
4. system as claimed in claim 1 or 2, it is characterised in that the total system is also carried on the back by many slots
Plate connecting multi-channel AD/DA plates and general signal processing module, and by external antenna front end, radar guidance system is built, realize
The Row control and signal transacting of complete radar guidance system；
The multichannel AD/DA plate integrated multi-channel AD/DA and FPGA processor.
5. a kind of software design approach of the total system based on VPX platforms as claimed in claim 1, its feature exists
In the integrated treatment software carries out task division according to the interface type and disposal ability of the total system, goes forward side by side
Row multi-task scheduling and calculate node dynamically distributes, carry out complicated Row control, algorithm can the part of parallelization computing can
With reference to motherboard, daughter board FPGA PL resource service condition and motherboard, daughter board double-core ARM CortexTM- A9 processors PS
Disposal ability algorithm split into different submodules cooperate with computing by both, pass through motherboard, daughter board double-core ARM
CortexTMInteracting for high-speed interface intermediate result between-A9 processors PS and motherboard, daughter board FPGA PL, meets institute
State the real-time of total system and reduce the demand that algorithm realizes difficulty, lift process performance.
6. method as claimed in claim 5, it is characterised in that the integrated treatment software includes realizing and control system, day
Communication between line front end, telemetry system, data recording equipment and the other boards of VPX platforms, in addition to realize command analysis with answering
Answer, overall procedure control task, correspondingly the integrated treatment software include and control system communication module and antenna front ends
Communication module and telemetry system communication module and data recording equipment communication module and other board communication modules：
With control system communication module, integrated treatment software is communicated with control system by USB；Daughter board can
Programmed logic PL mainly realize EBI control task and with daughter board double-core ARM Cortex in pieceTMBetween-A9 processors PS
Data interaction；Daughter board double-core ARM CortexTM- A9 processors PS mainly realizes Data Format Transform and can compiled with daughter board in piece
Journey logic PL data interactions, the SRIO message that the valid data received are packaged into agreement specific length is sent to motherboard ZYNQ-
Packet in 7000 processors, the SRIO message that motherboard ZYNQ-7000 processors are sent can be compiled after extracting through daughter board in piece
Journey logic PL control interface chips are sent to control system；Motherboard FPGA PL mainly realizes that the control of SRIO EBIs is appointed
Business and motherboard FPGA PL and motherboard double-core ARM CortexTMData interaction between-A9 processors PS；Motherboard double-core
ARM CortexTM- A9 processors PS, which is mainly realized, instructs parsing and according to instruction analysis result, performs template data and loads, in fact
When parameter calculation and distribution, communication process control completes informix and repeat-back workflow；Motherboard double-core ARM
CortexTMData interaction in-A9 processors PS completions simultaneously and piece between motherboard FPGA PL, by command response information
The SRIO message for being packaged into agreement specific length is sent to daughter board ZYNQ-7000 processors through motherboard FPGA PL in piece；
With antenna front ends communication module, integrated treatment software uses universal serial bus communications with antenna front ends, logical using HDLC
Believe agreement；Motherboard double-core ARM CortexTM- A9 processors PS is according to command analysis result, according to overall procedure control and antenna
Front end is communicated, and command frame is sent to antenna front ends by motherboard FPGA PL in piece, by the antenna front ends received
Effective information is extracted in the command response frame of return, overall procedure control is completed according to antenna front ends work schedule, flow is performed
After the completion of will be packaged into after informix bus message return control system；Motherboard FPGA PL is realized to be led to antenna front ends
The HDLC protocol of letter, by motherboard double-core ARM CortexTMThe command frame that-A9 processors PS is sent is sent to day according to HDLC protocol
Line front end, the command response frame that antenna front ends are returned according to HDLC protocol is sent to motherboard double-core ARM by internal interface
CortexTM- A9 processors PS carries out data frame Effective judgement and information extraction；
With telemetry system communication module, integrated treatment software is communicated with telemetry system by USB, is used
HDLC communication protocols；Daughter board FPGA PL realizes the HDLC protocol communicated with telemetry system, receives and parses through telemetry system
The claim frame sent according to HDLC protocol timing；Daughter board FPGA PL will pass through daughter board double-core ARM CortexTM- A9 processing
The data that are passed down by remote measurement are stamped after time scale information and given according to HDLC protocol to telemetry system the need for device PS processing is obtained,
If daughter board double-core ARM CortexTM- A9 processors PS processing then passes down telemetry frame without the data for needing to pass down only to include
Complete zero frame of time scale information；
With data recording equipment communication module, integrated treatment software is communicated with data recording equipment by Ethernet, is used
UDP communication protocols；Motherboard ZYNQ-7000 processor RGMII interfaces are realized after SGMII and RGMII interface conversions by PHY chip
It is connected with Ethernet switching chip；Motherboard double-core ARM CortexTMAfter-A9 processors PS is route by Ethernet switching chip
Realize the communication with data recording equipment；After the work of total system distribution, as the DoorBell for receiving other boards transmissions
After notifying that a frame recording data are sent completely, motherboard double-core ARM CortexTMThe record that-A9 processors PS controls cache DDR3
The order that data and corresponding auxiliary information, control system are sent is sent to data recording equipment according to udp protocol；
With other board communication modules, the total system of integrated treatment running software passes through VPX platforms with other boards
Backboard is connected, between total system and other boards, and completes logical by SRIO high-speed buses between other boards
Letter；Motherboard double-core ARM CortexTM- A9 processors PS mainly completes SRIO bus data memory allocations, according to reception number
According to SRIO addresses and DoorBell types data read from DDR3 complete data forwarding and data processing；Motherboard is programmable to patrol
Volume PL mainly complete SRIO Interface Controllers and with motherboard double-core ARM CortexTM- A9 processors PS data interaction, according to motherboard
Double-core ARM CortexTMThe address space control of-A9 processors PS distribution stores the plug-in DDR3 of the data storage received
In device；Motherboard double-core ARM CortexTM- A9 processors PS controls to need to be sent to corresponding other boards according to overall procedure
Data are sent to SRIO exchange chips, after SRIO exchange chips are route according to source ID and Target id via motherboard FPGA PL
Sent via VPX platform back planes to corresponding other boards.
7. method as claimed in claim 6, it is characterised in that the integrated treatment software also includes image compression module, female
Plate ZYNQ-7000 processors judge to receive what other boards were sent according to the SRIO addresses and DoorBell types that receive data
View data is sent to daughter board ZYNQ-7000 processors through SRIO buses；Daughter board double-core ARM CortexTM- A9 processors PS will
The view data received is carried out after the completion of piecemeal processing, image block, in being sent according to daughter board FPGA PL in piece
Video data block is sent to daughter board FPGA PL carry out the change of second order Daubechies5/3 Lifting Wavelets according to this by disconnected request
Change；LH1, HL1 subband of single order wavelet transformation formation and HH2, LH2, HL2, LL2 subband of second order wavelet transformation formation be not using
Daughter board double-core ARM Cortex in piece are sent to after carrying out quantification treatment with quantization stepTM- A9 processors PS；Daughter board double-core ARM
CortexTM- A9 processors PS is encoded using spiht algorithm to each subband wavelet coefficient.
8. method as claimed in claims 6 or 7, it is characterised in that the integrated treatment software also includes data and compiles frame module,
Daughter board double-core ARM CortexTM- A9 processors PS by compression of images bit stream data increase compressed bit stream frame head, image block number,
Spiht algorithm parameter, code stream length and bit stream data are packaged into compressed bit stream data frame；The inertial guidance data that will be received during imaging
Inertial guidance data frame is packaged into after increase frame head and frame number information；Tied in the middle of the algorithm operation that the other boards received are sent
Really, state-detection data are packaged as after the increase such as system core status information, other auxiliary informations frame head, data length information
Frame.
9. the method as described in claim 5 or 6 or 7, it is characterised in that the integrated treatment software also includes BIT and detects mould
Block.
10. method as claimed in claim 8, it is characterised in that the integrated treatment software also includes BIT detection modules.
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