CN107197175A - A kind of high rail level battle array stares infrared camera imaging circuit system - Google Patents
A kind of high rail level battle array stares infrared camera imaging circuit system Download PDFInfo
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- CN107197175A CN107197175A CN201710401024.1A CN201710401024A CN107197175A CN 107197175 A CN107197175 A CN 107197175A CN 201710401024 A CN201710401024 A CN 201710401024A CN 107197175 A CN107197175 A CN 107197175A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
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Abstract
Infrared camera imaging circuit system, including area array infrared detector, biasing drive module, signal processing module, data memory module, locking current limliting monitoring module and high-frequency clock management module are stared the invention discloses a kind of high rail level battle array.In biasing drive module and signal processing module, using the device of high-performance highly anti-radiation ability, the required offset driving voltage of area array infrared detector work and sequential are produced；The large-scale Nonuniformity Correction coefficient of area array infrared detector is stored using the magnetic memory array that Read-write Catrol is flexible and single-particle inversion is immune in data memory module, the generation of Single event upset effecf is effectively prevented；The device sensitive to locking single particle in system, using locking Current limited Control technology, protects locked plug-in unit not burnt by high current, improves the anti-single particle locking ability of device；High-frequency clock management module provides high-quality clock for each module.The characteristics of present invention has high speed, high reliability, highly anti-radiation ability.
Description
Technical field
Infrared camera imaging is stared the invention belongs to infrared camera technical field of imaging, more particularly to a kind of high rail level battle array
Circuit system.
Background technology
In recent years, face battle array infrared camera is high with its sensitivity, and without optical mechaical scanning mechanism, small volume, lightweight etc. are excellent
Point, is widely used in military and civilian remote sensing fields.Battle array infrared camera is applied to geostationary orbit remote sensing satellite face to face
When upper, due to geostationary orbit remote sensing satellite and Geo-synchronous, relative to geostationary, face battle array infrared camera can be to mesh
Mark region is long-term " staring ", with minute level, or even high-frequency shooting, acquisition target area are carried out to target area with second level interval
Domain dynamic changing process data, with high temporal resolution.
Although geostationary orbit face battle array, which stares infrared camera, to be had many advantages, such as, track where it is apart from the earth
3.6 ten thousand kilometers of geostationary orbit, orbit altitude is higher by nearly 600 times, space radiation than the track where low rail remote sensing camera
Environment is also badly more many than low rail space environment, substantial amounts of charged particle and various rays can damage with aging electronic component,
Influence camera steady operation.High rail level battle array staring infrared imaging circuit system is the core electricity that high rail level battle array stares infrared camera
Road, its performance quality directly affects the image quality of camera, and its reliability height directly determines the success or failure of camera imaging task,
Therefore when designing high rail level battle array staring infrared imaging circuit system, except carrying out low noise, high accuracy, the design of low jitter
Outside, in addition it is also necessary to improve the Radiation hardness of circuit system.
The content of the invention
The technology of the present invention solves problem：The deficiencies in the prior art are overcome to stare infrared camera there is provided a kind of high rail level battle array
Imaging circuit system, with the actual demand of high speed, high reliability and highly anti-radiation ability.
In order to solve the above-mentioned technical problem, infrared camera imaging circuit system is stared the invention discloses a kind of high rail level battle array
System, including：Bias drive module, area array infrared detector, signal processing module, data memory module, locking current limliting monitoring mould
Block and high-frequency clock management module；
The biasing drive module, a variety of bias voltages required for producing area array infrared detector work；And,
The detector clock signal that signal processing module is exported is driven, the drive matched with area array infrared detector demand is obtained
Dynamic clock signal；
The area array infrared detector, for converting optical signals to simulation electricity in 4 tunnels under the driving of biasing drive module
Signal output；
The signal processing module, the 4 road analog electrical signals for being exported to area array infrared detector are handled, and are obtained
To 1 road high speed serialization view data, the 1 road high speed serialization view data is sent to image capture device；
The data memory module, for storing the large-scale pixel Photo-Response Non-Uniformity correction of area array infrared detector
Coefficient；
The locking current limliting monitoring module, for cutting off it when locking single particle occurs for locking single particle Sensitive Apparatus
Power supply, protects locked plug-in unit not burnt by high current；
The high-frequency clock management module, for provide high-quality clock.
Stared in above-mentioned high rail level battle array in infrared camera imaging circuit system, the biasing drive module, including：Biasing
Voltage produces submodule and Timing driver submodule；
The bias voltage produces submodule, a variety of bias voltages required for producing area array infrared detector work；
The Timing driver submodule, for being driven to the detector clock signal exported to signal processing module
Obtain the driver' s timing signal matched with planar array detector demand.
Stared in above-mentioned high rail level battle array in infrared camera imaging circuit system, the bias voltage produces submodule, is used for
According to driving current, noise and tolerances, a variety of bias voltages needed for area array infrared detector work are produced.
Stared in above-mentioned high rail level battle array in infrared camera imaging circuit system, the bias voltage produces submodule, uses
In：When noise and tolerances meet the first preset requirement and needs accurately adjustable photodiode bias, according to low
Noise, Low Drift Temperature, the voltage reference of highly anti-radiation ability produce high-precision reference voltage signal；Pass through resistor voltage divider network
Partial pressure is carried out to the quasi- voltage signal and obtains voltage division signal；By amplifier of the voltage division signal by high cmrr, low noise
Amplification is driven, bias voltage is obtained；
Wherein, the adjustable potentiometer of voltage-splitter resistance net route and precision resistance composition；
The adjustable potentiometer, for adjusting partial pressure resistance in real time, carries out partial pressure to reference voltage signal and obtains optimal
Photodiode bias；
The precision resistance, for determining that accurate partial pressure resistance obtains described according to the resistance of adjustable potentiometer adjustment
Bias voltage.
Stared in above-mentioned high rail level battle array in infrared camera imaging circuit system, the bias voltage produces submodule, uses
In：
When noise and tolerances meet the second preset requirement and driving current is more than or equal to 100mA, pass through low noise
Sound, the low pressure difference linear voltage regulator of highly anti-radiation ability produce high current, low noise voltage signal, pass through low-pass filter circuit
Supply voltage needed for producing.
Stared in above-mentioned high rail level battle array in infrared camera imaging circuit system, the signal processing module, including：Conditioning
Module, 14bits analog-digital converters, FPGA and high-speed serial data transmission circuit；
The conditioning module, the 4 road analog electrical signals for being exported to area array infrared detector are nursed one's health, and are obtained
Analog signal with 14bits analog-digital converter input interfaces；
The 14bits analog-digital converters, for carrying out analog-to-digital conversion to 4 tunnel analog signals after conditioning, obtain 4 tunnels
14bits numerical datas；
The FPGA, for 4 road 14bits numerical datas are carried out oversampled points selections, mean filter, data combining,
The correction of pixel Photo-Response Non-Uniformity, blind element are replaced and data layout, obtain 1 road high speed serialization view data；
The high-speed serial data transmission circuit, for sending the 1 road high speed serialization view data to IMAQ
Equipment.
Stared in above-mentioned high rail level battle array in infrared camera imaging circuit system, the high-frequency clock management module, including：
The synchronous debounce chip of reference clock, VCXO, clock and loop filter；The reference clock, VCXO, clock are same
Walk debounce chip and loop filter constitutes phase-locked loop circuit；
The reference clock, for producing reference clock signal；
The synchronous debounce chip of the clock, for being divided to the clock that VCXO is exported, phase demodulation and according to mirror
Phase result produces control electric current；
The loop filter, for control electric current to be converted into low noise control voltage signal；Wherein, the low noise
Acoustic control voltage signal is used for the output frequency for controlling VCXO；
The VCXO, under low noise control voltage signal control, output clock phase and when referring to
Clock PGC demodulation, and debounce.
Stared in above-mentioned high rail level battle array in infrared camera imaging circuit system, the synchronous debounce chip of the clock, including：
Phase discriminator, frequency divider and charge pump；
The frequency divider, for being divided to the clock signal that VCXO is exported；
The phase discriminator, clock signal and reference clock signal for being divided to the frequency divider are entered line phase and compared,
Obtain comparative result；
The charge pump, for the phase comparative result exported according to the phase discriminator, output control electric current；
The frequency divider, is additionally operable to divide the VCXO after locking debounce, 4 couples of 50MHz LVPECL of output are poor
Timesharing clock provides change over clock for No. 4 analog-digital converters, and output two-way 100MHz LVCMOS single ended clocks are FPGA and high speed
Serial transmission circuit provides master clock.
Stared in above-mentioned high rail level battle array in infrared camera imaging circuit system, the locking current limliting monitoring module is connected on
Between the power supply and device of locking single particle Sensitive Apparatus, for setting threshold value electricity according to the running current of device
Flow Ith, pass through current divider RshuntThe operating current I of locking single particle Sensitive Apparatus is monitored in real timew, when the in-orbit generation simple grain of device
During sub- locking-up effect, if the operating current I of devicewMore than the threshold current I of settingth, cut off the power supply of device, device
Locking single particle effect release；When meeting prefixed time interval TdWhen, power, protect for locking single particle Sensitive Apparatus again
Shield device occurs not burnt by high current during locking single particle effect.
The present invention has advantages below：
Infrared camera imaging circuit system is stared the invention discloses a kind of high rail level battle array, according to the in-orbit spatial loop of system
Border is severe, the long-life, the characteristics of power up for a long time, in biasing drive module and signal processing module, using the high anti-spoke of high-performance
According to the device of ability, the required offset driving voltage of area array infrared detector work and sequential, the mould exported to detector are produced
Intend signal nurse one's health obtaining 1 road high speed serialization view data.Wherein, data memory module using Read-write Catrol flexibly and
The immune magnetic memory array storage large-scale Nonuniformity Correction coefficient of area array infrared detector of single-particle inversion, effectively
Prevent the generation of Single event upset effecf；The device sensitive to locking single particle in system, using locking Current limited Control technology,
Its power supply is cut off when locking single particle occurs for device, protects locked plug-in unit not burnt by high current, the anti-simple grain of device is improved
Sub- locking ability；High-frequency clock management module provides high-quality clock for each module.Infrared phase is stared with traditional face battle array
The characteristics of machine imaging circuit system has high speed, high reliability, highly anti-radiation ability compared to the present invention.
Brief description of the drawings
Fig. 1 is the structured flowchart that a kind of high rail level battle array stares infrared camera imaging circuit system in the embodiment of the present invention；
Fig. 2 is a kind of structured flowchart for biasing drive module in the embodiment of the present invention；
Fig. 3 is a kind of fundamental diagram of bias voltage generation submodule in the embodiment of the present invention；
Fig. 4 is a kind of bias voltage Gpol generations schematic diagram in the embodiment of the present invention；
Fig. 5 is a kind of structured flowchart of signal processing module in the embodiment of the present invention；
Fig. 6 is a kind of area array infrared detector analog signal over-sampling schematic diagram in the embodiment of the present invention；
Fig. 7 is that a kind of pixel Photo-Response Non-Uniformity correction coefficient is shown in the packet of magnetic storage array in the embodiment of the present invention
It is intended to；
Fig. 8 is a kind of structured flowchart for locking current limliting monitoring module in the embodiment of the present invention.
Embodiment
It is public to the present invention below in conjunction with accompanying drawing to make the object, technical solutions and advantages of the present invention clearer
Embodiment is described in further detail.
Reference picture 1, shows that a kind of high rail level battle array in the embodiment of the present invention stares the knot of infrared camera imaging circuit system
Structure block diagram.In the present embodiment, the high rail level battle array stares infrared camera imaging circuit system, including：Bias drive module
100th, area array infrared detector 200, signal processing module 300, data memory module 400, the and of locking current limliting monitoring module 500
High-frequency clock management module 600.
The biasing drive module 100, a variety of bias voltages required for producing area array infrared detector work；With
And, the detector clock signal that signal processing module is exported is driven, obtains what is matched with area array infrared detector demand
Driver' s timing signal.
The area array infrared detector 200, for converting optical signals to 4 road moulds under the driving of biasing drive module
Intend electric signal output.
The signal processing module 300, the 4 road analog electrical signals for being exported to area array infrared detector are handled,
1 road high speed serialization view data is obtained, the 1 road high speed serialization view data is sent to image capture device.
The data memory module 400, for storing the large-scale pixel Photo-Response Non-Uniformity school of area array infrared detector
Positive coefficient.
The locking current limliting monitoring module 500, for being cut off when locking single particle occurs for locking single particle Sensitive Apparatus
Its power supply, protects locked plug-in unit not burnt by high current.
The high-frequency clock management module 600, for provide high-quality clock.
(1) drive module is biased
Reference picture 2, shows a kind of structured flowchart for biasing drive module in the embodiment of the present invention.In the present embodiment,
The biasing drive module 100 can specifically include：Bias voltage produces submodule 101 and Timing driver submodule 102.
In the present embodiment, the bias voltage produces submodule 101, for producing area array infrared detector work institute
The a variety of bias voltages needed；The Timing driver submodule 102, for the detector sequential to being exported to signal processing module
Signal is driven the driver' s timing signal for obtaining matching with planar array detector demand.
Wherein, the bias voltage, which produces submodule 101, to produce face according to driving current, noise and tolerances
A variety of bias voltages needed for array infrared detector work：
When noise and tolerances meet the first preset requirement (high, occurrence can be determined according to actual conditions) and need
When wanting accurate adjustable photodiode bias, produced according to the voltage reference of low noise, Low Drift Temperature, highly anti-radiation ability high
The reference voltage signal of precision；Partial pressure is carried out to the reference voltage signal by resistor voltage divider network and obtains voltage division signal；Will
Voltage division signal is driven amplification by the amplifier of high cmrr, low noise, obtains bias voltage；Wherein, the partial pressure
Resistor network is made up of adjustable potentiometer and precision resistance；The adjustable potentiometer, for adjusting partial pressure resistance in real time,
Partial pressure is carried out to reference voltage signal and obtains optimal photodiode bias；The precision resistance, for according to adjustable nodal potential
The resistance of device adjustment determines that accurate partial pressure resistance obtains the bias voltage.
When noise and tolerances meet the second preset requirement (low) and driving current is more than or equal to 100mA, pass through
Low noise, the low pressure difference linear voltage regulator of highly anti-radiation ability produce high current, low noise voltage signal, pass through LPF
Supply voltage needed for circuit is produced.
Specifically, in the present embodiment, it is infrared that the bias voltage generation submodule 101 can produce 1k × 1k faces battle array
3 required road bias voltages of detector work (it is required that：Noise ＜ 5mV, tolerance ＜ ± 50mV, driving current≤100mA),
VDDD (it is required that：Noise ＜ 5mV, tolerance ＜ ± 50mV, driving current≤100mA) and Gpol (it is required that：Noise ＜ 100uV, hold
Poor ＜ ± 5mV, driving current≤5mA).
Such as Fig. 3, a kind of fundamental diagram of bias voltage generation submodule in the embodiment of the present invention is shown.In this reality
Apply in example, bias voltage produces submodule 101 and requires different according to driving current, noise, tolerance etc., can be using difference
Method produce bias.Specifically：The analog power VDDA of high current and digital power vd DD, passes through the linear steady of low noise
Depressor is produced, and the linear voltage regulator Flouride-resistani acid phesphatase accumulated dose is 300kradSi, and locking single particle is immunized, can meet high rail and use
It is required that；The linear voltage regulator fixes output 5V, and output driving current maximum can reach 2A, and root mean square noise is 40uV, output
Precision 1% (± 50mV), electrical property meets the demand of detector.Adjustable bias voltage Gpol is the light of area array infrared detector
Electric diode bias voltage, each detector has each optimal Gpol values, and its noise size and precision, stability are direct
Influence the performance of detector.For Gpol the system using high-precision band gap voltage stabilizing benchmark+Low Drift Temperature divider resistance+low noise,
The method of Low Drift Temperature amplifier is produced.
Such as Fig. 4, show that a kind of bias voltage Gpol produces schematic diagram in the embodiment of the present invention.In the present embodiment, it is high
Accuracy bandgap voltage stabilizing benchmark fixes output 5V, R1, Rc, R2, R3 and constitutes electric resistance partial pressure networking, and Rc is adjustable potentiometer, is divided first
Pressure network network is connected to path 1, and regulation potentiometer Rc obtains optimal bias, and then potential-divider network disconnection path 1 is connected to path 2,
Determine that divider resistance R2, R3's is worth to required bias according to potentiometer Rc resistance；Resistance Ro is output current limiting resistance, when
During Gpol shorted to earths, limit the short circuit current flow of amplifier 201, protect it from being damaged, at the same Ro and polarized tantalum electric capacity C1 and
Ceramic disc capacitor C2 constitutes LPF networking, filters out the noise of Gpol biass；R4 is feedback resistance, one end connection amplifier 201
Reverse input end, one end connection Ro, when the Gpol pin impedances of detector end change, Gpol bias can stablize defeated
Go out, do not influenceed by load change；Cf is feedback compensation electric capacity, it is ensured that self-oscillation does not occur for amplifier 201.
It is further preferred that the Timing driver submodule 102, for the FPGA (Field- under signal processing module
Programmable Gate Array, field programmable gate array) clock signal that produces, carry out Timing driver and level and turn
Change, to meet the timing requirements of area array infrared detector.
(2) signal processing module
Reference picture 5, shows a kind of structured flowchart of signal processing module in the embodiment of the present invention.In the present embodiment,
The signal processing module 300 can specifically include：Conditioning module 301,14bits analog-digital converters 302, FPGA303 and height
Fast serial data transmission circuit 304.
In the present embodiment, the conditioning module 301, for the 4 road analog electrical signals exported to area array infrared detector
Nursed one's health, obtain matching the analog signal of 14bits analog-digital converter input interfaces；The 14bits analog-digital converters 302,
For carrying out analog-to-digital conversion to 4 tunnel analog signals after conditioning, 4 road 14bits numerical datas are obtained；The FPGA303, is used for
4 road 14bits numerical datas progress oversampled points selections, mean filter, data combining, pixel Photo-Response Non-Uniformity are corrected,
Blind element is replaced and data layout, obtains 1 road high speed serialization view data；The high-speed serial data transmission circuit 304, is used for
Send the 1 road high speed serialization view data to image capture device.
Wherein, area array infrared detector analog signal over-sampling flow is referred to Fig. 6, shows the embodiment of the present invention
A kind of middle area array infrared detector analog signal over-sampling schematic diagram.The pixel read frequency of area array infrared detector is 5MHz,
The Minimum sample rate of selected 14bits aerospace level analog-digital converter is 30MHz, if each pixel is sampled 1 time, pixel reads frequency
Rate can not be matched with the sample frequency of analog-digital converter, and the system is defeated according to each pixel of 1k × 1k area array infrared detectors
Go out the characteristics of signal keeps a level value after quick set up, design analog-digital converter sample frequency is 50MHz, at one
In pixel readout interval, analog-digital converter can adopt the data to 10 pixels；10 of each pixel are adopted in FPGA
Sample data are chosen, and remove 6 (1,2,3,8,9,10) unstable data during analog signal is set up, and retain stable
4 (4,5,6,7) sample point datas, the mean filter processing of cumulative averaging is carried out to it, the amount of analog-digital converter is reduced
Change noise and circuit thermal noise, improve the signal to noise ratio of system, while also solving the problem of selecting of aerospace level analog-digital converter.
It is further preferred that in the present embodiment, signal processing module 300 specifically can be according to area array infrared detector
The characteristics of output signal of each pixel keeps a level value after quick set up, using over-sampling scheme to analog signal
Carry out sampling processing.Specifically, setting the pixel read frequency of area array infrared detector as Fr, 14bits analog-digital converters are to every
The sample frequency of individual pixel analog signal is N × Fr, in a pixel readout interval, and analog-digital converter can adopt N number of be somebody's turn to do
The data of pixel；FPGA chooses to N number of sampled data of each pixel, removes N-M during analog signal is set up
Unstable data, retain M stably sample point data, to M sample point data according toFormula (Xi is
I-th sampled data) mean filter processing is carried out, the quantizing noise and circuit thermal noise of analog-digital converter are reduced, system is improved
The signal to noise ratio of system.
(3) data memory module
In the present embodiment, described pixel Photo-Response Non-Uniformity correction, is prestored multigroup correction coefficient using ground,
The real time correction scheme of the adaptively selected correction coefficient of rail is realized.The scale of area array infrared detector is 1K × 1K pixels, height
Two grades of adjustable gains, four sections of the time of integration point is adjustable, and each pixel needs gain correction coefficient K, bias correction coefficient B two
16bits correction coefficient；The pixel Photo-Response Non-Uniformity of area array infrared detector can change with the time of integration and gain, this hair
The two grades of gains of bright design height prestore the changes of 4 groups of correction coefficient, four sections of times of integration of correspondence respectively, and prestore 8 groups of pixel schools altogether
Positive coefficient, pre-stored data amount is immunized for 8M × 32bits data memory module using 16 single-particle inversions and power down is not lost
2M × 8bits magnetic memories constitute storage array and prestore 8 groups of pixel Photo-Response Non-Uniformity correction coefficient；16 2M × 8bits
Magnetic memory divides 4 groups of carry out Depth Expansions to constitute 4 8M × 8bits storage groups first, then again stores 4 8M × 8bits
Group carries out bit wide extension, forms 8M × 32bits magnetic storage array, realizes the storage of extensive pixel correction coefficient.It is described
Signal processing module in FPGA, when ground sends gain and during time of integration adjust instruction, FPGA according to gain parameter and
Time of integration parameter adaptive judges to choose 1 group of correction coefficient in 8 groups, non-to current image date progress pixel response
Even property correction, realizes the real time correction scheme of in-orbit adaptively selected correction coefficient.
In other words, in the present embodiment, area array infrared detector is because pixel scale is big, complex process, and its pixel rings
Answer heterogeneity big, and uniformity can change with the change of detector gain or the time of integration.And face battle array stares infrared phase
Machine is in-orbit when being imaged over the ground, it usually needs according to the difference of observed object, adjustment detector gain and the time of integration.Therefore it is comprehensive
Close consider it is in-orbit realize complexity and the aspect of calibration result two, the present invention is prestored multigroup correction coefficient using ground, it is in-orbit from
Adapt to the real-time pixel Photo-Response Non-Uniformity correcting scheme of selection correction coefficient.
Correction coefficient is by ground fixed detector gain and the time of integration, gathering the black matrix image of multiple temperature spots
To obtain the coefficient under the gain and the time of integration.Two grades of detector gain used of the invention, time of integration 0.1ms~20ms
(stepping 2us) is adjustable, and one group of correction coefficient if each stepping prestores is, it is necessary to very big memory space, therefore consider hardware
Easily realize, and according to area array infrared detector export response curve, will be divided into the time of integration 0.1ms~1ms, 1.002ms~
Tetra- sections of 5ms, 5.002ms~10ms, 10.002ms~20ms, every grade of gain obtains 4 groups of correction systems changed with the time of integration
Number.When in-orbit adjust gain and the time of integration, FPGA chooses corresponding correction according to the order parameter adaptive judgement received
Coefficient.
The scale of area array infrared detector is 1K × 1K pixels, each pixel designing gain correction coefficient K, bias correction
Two 16bits correction coefficient of coefficient B, 8 groups of pixel correction coefficient, pre-stored data amount is 8M × 32bits.
Traditional remote sensing camera prestores more than correction coefficient, and using PROM, (Programmable Read Only Memory, can
Program read-only memory) storage, but PROM zero-address lines, data, and reading speed can only be read according to timeticks order
Slowly, it is necessary to which adapted SRAM (Static Random Access Memory, static RAM) is carried out further
Coefficient caching process, this not only increases PCB (Printed Circuit Board, printed circuit board) area, and SRAM is easily sent out
Raw single-particle inversion makes the reduction of camera reliability.The data memory module of the present invention is immunized and fallen using 16 single-particle inversions
2M × 8bits magnetic memories that electricity does not lose constitute storage array and store 8 groups of correction coefficient.Storage array packet schematic diagram is as schemed
7, show packet schematic diagram of a kind of pixel Photo-Response Non-Uniformity correction coefficient in magnetic storage array in the embodiment of the present invention.
16 4 groups of magnetic memories point, the chip selection signal CS1 of every 4 2M × 8bits magnetic memories progress, 4 memories of Depth Expansion,
CS2, CS3 and CS4 read to enable signal RE, write enable signal WE and 8bits data wire as the high four of 25bits address wires
Share, obtain 4 groups of 8M × 8bits storage group；The 8bits data wires of 4 groups of 8M × 8bits storage groups carry out bit wide extension again,
32bits data widths are expanded to, the 25bits address wires of 4 groups of storage groups, reading enable signal RE, write enable signal WE and shared.
24bits address wires are addressed according to CS4＆CS3＆CS2＆CS1＆A20~A0 in storage array, and 0200000H~02FFFFFH is deposited
Store up the correction coefficient under low gain time of integration 0.1ms~1ms states, 0300000H~03FFFFFH storage low gain integrations
Correction coefficient under time 1.002ms~5ms states, 0400000H~04FFFFFH storage low gains time of integration 5.002ms
Correction coefficient under~10ms states, 0500000H~05FFFFFH storage low gains time of integration 10.002ms~20ms shapes
Correction system under correction coefficient under state, 0800000H~08FFFFFH storage high-gains time of integration 0.1ms~1ms states
Correction coefficient under number, 0900000H~09FFFFFH storage high-gains time of integration 1.002ms~5ms states, 1000000H
Correction coefficient under~10FFFFFH storage high-gains time of integration 5.002ms~10ms states, 1100000H~11FFFFFH
Store the correction coefficient under high-gain time of integration 10.002ms~20ms states.When in-orbit adjust gain and the time of integration,
FPGA reads the correction coefficient in appropriate address space according to the order parameter adaptive judgement received.
(4) current limliting monitoring module is locked
Reference picture 8, shows a kind of structured flowchart for locking current limliting monitoring module in the embodiment of the present invention.In this implementation
In example, the locking current limliting monitoring module is connected between the power supply of locking single particle Sensitive Apparatus and device, for root
According to the running current of device, threshold current I is setth, pass through current divider RshuntLocking single particle Sensitive Apparatus is monitored in real time
Operating current Iw, when device is in-orbit occurs locking single particle effect, if the operating current I of devicewMore than the threshold value of setting
Electric current Ith, the power supply of device is cut off, the locking single particle effect of device is released；When meeting prefixed time interval TdWhen, weight
Newly powered for locking single particle Sensitive Apparatus, protection device occurs not burnt by high current during locking single particle effect.
Wherein, each parameter setting of locking current limliting monitoring module is as follows：
1) the threshold current I of current limliting monitoring module is lockedth, stand-by operation threshold current I can be setth_rWith threshold value electricity
Flow Ith_sTwo kinds, locking single particle Sensitive Apparatus is set to be protected under different working condition；
2) by controlling MODE_IthSignal, selects threshold current, MODE_IthFor high level during ' 1 ', locking current limliting prison
Control module selection threshold current Ith_r；MODE_IthFor high level during ' 0 ', locking current limliting monitoring module selection threshold current
Ith_s；
3)Ith_1And Ith_2By setting the resistance R between the LIM_s and ground of locking current limliting monitoring modulesAnd locking current limliting
Resistance R between the LIM_s and LIM_r of monitoring modulerTo realize, specific formula is：
4) power-off restarting time interval TdDeferred telegram between the ADJ_RESTART and ground of locking current limliting monitoring module
Hold CdDetermine, TdAnd CdRelation be：
Cd=26*Td
Wherein, TdUnit is ms, CdUnit is nF.
(5) high-frequency clock management module
In the present embodiment, the high-frequency clock management module can specifically include：Reference clock, VCXO, clock
Synchronous debounce chip and loop filter.The synchronous debounce chip of the reference clock, VCXO, clock and loop filter
Constitute phase-locked loop circuit.
Wherein, the reference clock 601, for producing reference clock signal；The synchronous debounce chip 602 of the clock, is used
In being divided to the clock that VCXO is exported, phase demodulation and control electric current is produced according to identified result；The loop filtering
Device 603, for control electric current to be converted into low noise control voltage signal；Wherein, the low noise control voltage signal is used for
Control the output frequency of VCXO；The VCXO 604, it is defeated under low noise control voltage signal control
Go out clock phase and reference clock PGC demodulation, and debounce.
It is preferred that, the synchronous debounce chip of the clock can specifically include：Phase discriminator, frequency divider and charge pump.
The frequency divider, for being divided to the clock signal that VCXO is exported；The phase discriminator, for institute
The clock signal and reference clock signal for stating frequency divider frequency dividing are entered line phase and compared, and obtain comparative result；The charge pump, is used
In the phase comparative result exported according to the phase discriminator, output control electric current；The frequency divider, is additionally operable to locking debounce
VCXO afterwards is divided, and 4 pairs of 50MHz LVPECL differential clocks of output provide change over clock for No. 4 analog-digital converters,
It is that FPGA and high speed serial transmission circuit provide master clock to export two-way 100MHz LVCMOS single ended clocks.Empirical tests, the height
The shake of 4 pairs of 50MHz LVPECL differential clocks of fast Clock management module output is only 60ps, greatly reduces analog-to-digital conversion
The Aperture Jitter and conversion noise of device；Two-way 100MHz LVCMOS single ended clocks are dithered as 100ps, improve FPGA and height
Job stability when fast serial data transmission chip is powered up for a long time.
In summary, a kind of high rail level battle array stares infrared camera imaging circuit system, including area array infrared detector, partially
Put drive module, signal processing module, data memory module, locking current limliting monitoring module and high-frequency clock management module.According to
The in-orbit space environment of system is severe, the long-life, the characteristics of power up for a long time, in biasing drive module and signal processing module, adopt
With the device of high-performance highly anti-radiation ability, the required offset driving voltage of area array infrared detector work and sequential are produced, it is right
The analog signal of detector output is nursed one's health, 14bits analog-to-digital conversions, while being carried out to the multi-channel data after analog-to-digital conversion
Oversampled points selection, mean filter, data combining, the correction of pixel Photo-Response Non-Uniformity, blind element are replaced and data layout, and led to
High speed serial data transmission circuit is crossed, image capture device is transferred data to；Read-write Catrol is used in data memory module
The immune large-scale Nonuniformity Correction system of magnetic memory array storage area array infrared detector of flexible and single-particle inversion
Number, effectively prevents the generation of Single event upset effecf；The device sensitive to locking single particle in system, using locking current limliting control
Technology processed, cuts off its power supply when locking single particle occurs for device, protects locked plug-in unit not burnt by high current, improves device
Anti-single particle locking ability；High-frequency clock management module is using the synchronous debounce chip of clock and VCXO, loop filter
Phase-locked loop circuit is constituted, the reference clock and VCC voltage controlled clock to input are carried out after clock jitter removing, frequency dividing, phase modulation, are FPGA, mould
Number converter and high-speed serial data transmission chip provide high-quality clock.Infrared camera imaging is stared with traditional face battle array
The characteristics of circuit system has high speed, high reliability, highly anti-radiation ability compared to the present invention.
Each embodiment in this explanation is described by the way of progressive, what each embodiment was stressed be with
Between the difference of other embodiment, each embodiment identical similar part mutually referring to.
It is described above, it is only the optimal embodiment of the present invention, but protection scope of the present invention is not limited to
This, any one skilled in the art the invention discloses technical scope in, the change that can readily occur in or replace
Change, should all be included within the scope of the present invention.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (9)
1. a kind of high rail level battle array stares infrared camera imaging circuit system, it is characterised in that including：Bias drive module, face battle array
Infrared detector, signal processing module, data memory module, locking current limliting monitoring module and high-frequency clock management module；
The biasing drive module, a variety of bias voltages required for producing area array infrared detector work；And, to signal
The detector clock signal of processing module output is driven, and obtains the driver' s timing letter matched with area array infrared detector demand
Number；
The area array infrared detector, for converting optical signals to 4 road analog electrical signals under the driving of biasing drive module
Output；
The signal processing module, the 4 road analog electrical signals for being exported to area array infrared detector are handled, and obtain 1 tunnel
High speed serialization view data, sends the 1 road high speed serialization view data to image capture device；
The data memory module, for storing the large-scale pixel Photo-Response Non-Uniformity correction coefficient of area array infrared detector；
The locking current limliting monitoring module, for cutting off its power supply when locking single particle occurs for locking single particle Sensitive Apparatus,
Locked plug-in unit is protected not burnt by high current；
The high-frequency clock management module, for provide high-quality clock.
2. system according to claim 1, it is characterised in that the biasing drive module, including：Bias voltage produces son
Module and Timing driver submodule；
The bias voltage produces submodule, a variety of bias voltages required for producing area array infrared detector work；
The Timing driver submodule, the detector clock signal for being exported to signal processing module, which is driven, to be obtained and face
The driver' s timing signal of array detector demand matching.
3. system according to claim 2, it is characterised in that the bias voltage produces submodule, for according to driving
Electric current, noise and tolerances, produce a variety of bias voltages needed for area array infrared detector work.
4. system according to claim 3, it is characterised in that the bias voltage produces submodule, is used for：When noise and
Tolerances meet the first preset requirement and needs accurately adjustable photodiode bias when, according to low noise, Low Drift Temperature,
The voltage reference of highly anti-radiation ability produces high-precision reference voltage signal；The quasi- voltage is believed by resistor voltage divider network
Number carry out partial pressure obtain voltage division signal；Voltage division signal is driven amplification by the amplifier of high cmrr, low noise, obtained
To bias voltage；
Wherein, the adjustable potentiometer of voltage-splitter resistance net route and precision resistance composition；
The adjustable potentiometer, for adjusting partial pressure resistance in real time, carries out partial pressure to reference voltage signal and obtains optimal photoelectricity
Diode biasing；
The precision resistance, for determining that accurate partial pressure resistance obtains the biased electrical according to the resistance of adjustable potentiometer adjustment
Pressure.
5. system according to claim 3, it is characterised in that the bias voltage produces submodule, is used for：
When noise and tolerances meet the second preset requirement and driving current is more than or equal to 100mA, pass through low noise, height
The low pressure difference linear voltage regulator of Radiation hardness produces high current, low noise voltage signal, and institute is produced by low-pass filter circuit
Need supply voltage.
6. system according to claim 1, it is characterised in that the signal processing module, including：Conditioning module,
14bits analog-digital converters, FPGA and high-speed serial data transmission circuit；
The conditioning module, the 4 road analog electrical signals for being exported to area array infrared detector are nursed one's health, and are matched
The analog signal of 14bits analog-digital converter input interfaces；
The 14bits analog-digital converters, for carrying out analog-to-digital conversion to 4 tunnel analog signals after conditioning, obtain 4 road 14bits
Numerical data；
The FPGA, for 4 road 14bits numerical datas to be carried out with oversampled points selection, mean filter, data combining, pixel sound
Answer Nonuniformity Correction, blind element to replace and data layout, obtain 1 road high speed serialization view data；
The high-speed serial data transmission circuit, for sending the 1 road high speed serialization view data to image capture device.
7. system according to claim 1, it is characterised in that the high-frequency clock management module, including：Reference clock,
The synchronous debounce chip of VCXO, clock and loop filter；The synchronous debounce chip of the reference clock, VCXO, clock
Phase-locked loop circuit is constituted with loop filter；
The reference clock, for producing reference clock signal；
The synchronous debounce chip of the clock, for being divided to the clock that VCXO is exported, phase demodulation and according to identified result
Produce control electric current；
The loop filter, for control electric current to be converted into low noise control voltage signal；Wherein, the low noise acoustic control
Voltage signal is used for the output frequency for controlling VCXO；
The VCXO, under being controlled in the low noise control voltage signal, output clock phase and reference clock phase
Position locking, and debounce.
8. system according to claim 7, it is characterised in that the synchronous debounce chip of the clock, including：Phase discriminator, point
Frequency device and charge pump；
The frequency divider, for being divided to the clock signal that VCXO is exported；
The phase discriminator, clock signal and reference clock signal for being divided to the frequency divider are entered line phase and compared, and obtain
Comparative result；
The charge pump, for the phase comparative result exported according to the phase discriminator, output control electric current；
The frequency divider, is additionally operable to divide the VCXO after locking debounce, during 4 pairs of 50MHzLVPECL difference of output
Clock provides change over clock for No. 4 analog-digital converters, and output two-way 100MHz LVCMOS single ended clocks are FPGA and high speed serialization is passed
Transmission of electricity road provides master clock.
9. system according to claim 1, it is characterised in that the locking current limliting monitoring module is connected on locking single particle
Between the power supply and device of Sensitive Apparatus, for setting threshold current I according to the running current of deviceth, by dividing
Flow device RshuntThe operating current I of locking single particle Sensitive Apparatus is monitored in real timew, occur locking single particle effect when device is in-orbit
When, if the operating current I of devicewMore than the threshold current I of settingth, cut off the power supply of device, the locking single particle of device
Effect is released；When meeting prefixed time interval TdWhen, powered again for locking single particle Sensitive Apparatus, simple grain occurs for protection device
Do not burnt during sub- locking-up effect by high current.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109374138A (en) * | 2018-09-18 | 2019-02-22 | 北京遥感设备研究所 | A kind of infrared imaging circuit and noise-reduction method |
| CN109977062A (en) * | 2019-03-14 | 2019-07-05 | 建荣半导体（深圳）有限公司 | A kind of method, apparatus and electronic equipment of software realization Serial data receiving |
| CN110350905A (en) * | 2018-04-03 | 2019-10-18 | 中国科学院声学研究所 | A kind of MEMS capacitive accelerometer interface circuit |
| CN111141397A (en) * | 2019-11-15 | 2020-05-12 | 西安电子科技大学 | Nonuniformity correction circuit for APD detector array |
| CN112787668A (en) * | 2020-12-28 | 2021-05-11 | 中国科学院长春光学精密机械与物理研究所 | Medium wave infrared detector imaging driving device |
| CN113377143A (en) * | 2021-04-25 | 2021-09-10 | 北京控制工程研究所 | Deep space exploration color camera self-recovery anti-single particle locking system and method |
| CN113727148A (en) * | 2021-07-22 | 2021-11-30 | 北京控制工程研究所 | Large-scale image high-speed transmission circuit |
| CN115371822A (en) * | 2022-10-24 | 2022-11-22 | 南京智谱科技有限公司 | Calibration method of infrared camera |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102252759A (en) * | 2011-03-16 | 2011-11-23 | 中国科学院上海技术物理研究所 | Infrared focal plane readout integrated circuit with digital output |
| CN205352557U (en) * | 2015-12-29 | 2016-06-29 | 中国电子科技集团公司第十一研究所 | Two take place ofs area array infrared detector subassembly pixel spectral response conformance testing devices |
| CN106595869A (en) * | 2016-11-28 | 2017-04-26 | 中国航空工业集团公司洛阳电光设备研究所 | High-resolution refrigeration-type infrared thermal imager |
-
2017
- 2017-05-31 CN CN201710401024.1A patent/CN107197175B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102252759A (en) * | 2011-03-16 | 2011-11-23 | 中国科学院上海技术物理研究所 | Infrared focal plane readout integrated circuit with digital output |
| CN205352557U (en) * | 2015-12-29 | 2016-06-29 | 中国电子科技集团公司第十一研究所 | Two take place ofs area array infrared detector subassembly pixel spectral response conformance testing devices |
| CN106595869A (en) * | 2016-11-28 | 2017-04-26 | 中国航空工业集团公司洛阳电光设备研究所 | High-resolution refrigeration-type infrared thermal imager |
Non-Patent Citations (4)
| Title |
|---|
| 吴和然等: ""非制冷红外探测器低噪声驱动和处理电路的设计研究"", 《红外技术》 * |
| 杨世宇等: ""空间单粒子锁定及防护技术研究"", 《核电子学与探测技术》 * |
| 程甘霖等: ""新型时钟管理电路模型分析与参数设计"", 《电子测量技术》 * |
| 薄姝等: ""320×256长波面阵红外探测器焦面电路设计"", 《电子测量技术》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110350905A (en) * | 2018-04-03 | 2019-10-18 | 中国科学院声学研究所 | A kind of MEMS capacitive accelerometer interface circuit |
| CN110350905B (en) * | 2018-04-03 | 2024-04-19 | 中国科学院声学研究所 | MEMS capacitive accelerometer interface circuit |
| CN109374138A (en) * | 2018-09-18 | 2019-02-22 | 北京遥感设备研究所 | A kind of infrared imaging circuit and noise-reduction method |
| CN109977062A (en) * | 2019-03-14 | 2019-07-05 | 建荣半导体（深圳）有限公司 | A kind of method, apparatus and electronic equipment of software realization Serial data receiving |
| CN111141397A (en) * | 2019-11-15 | 2020-05-12 | 西安电子科技大学 | Nonuniformity correction circuit for APD detector array |
| CN112787668A (en) * | 2020-12-28 | 2021-05-11 | 中国科学院长春光学精密机械与物理研究所 | Medium wave infrared detector imaging driving device |
| CN113377143A (en) * | 2021-04-25 | 2021-09-10 | 北京控制工程研究所 | Deep space exploration color camera self-recovery anti-single particle locking system and method |
| CN113727148A (en) * | 2021-07-22 | 2021-11-30 | 北京控制工程研究所 | Large-scale image high-speed transmission circuit |
| CN115371822A (en) * | 2022-10-24 | 2022-11-22 | 南京智谱科技有限公司 | Calibration method of infrared camera |
| CN115371822B (en) * | 2022-10-24 | 2023-01-24 | 南京智谱科技有限公司 | Calibration method of infrared camera |
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