CN107195549B - Thin film transistor, manufacturing method thereof, array substrate and display device - Google Patents
Thin film transistor, manufacturing method thereof, array substrate and display device Download PDFInfo
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- CN107195549B CN107195549B CN201710339635.8A CN201710339635A CN107195549B CN 107195549 B CN107195549 B CN 107195549B CN 201710339635 A CN201710339635 A CN 201710339635A CN 107195549 B CN107195549 B CN 107195549B
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- 239000010409 thin film Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 239000000758 substrate Substances 0.000 title claims abstract description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 146
- 238000005530 etching Methods 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims description 66
- 238000001312 dry etching Methods 0.000 claims description 19
- 238000004380 ashing Methods 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 9
- 230000014759 maintenance of location Effects 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 31
- 229910052751 metal Inorganic materials 0.000 description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 229910004205 SiNX Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000009616 inductively coupled plasma Methods 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract
The invention discloses a manufacturing method of a thin film transistor, wherein the thin film transistor comprises a source electrode and an active region, and the manufacturing method of the active region comprises the following steps: forming an active layer; forming a photoresist mask layer on the active layer, wherein the photoresist mask layer comprises a photoresist semi-reserved region and a photoresist completely-reserved region, and the photoresist semi-reserved region is formed on two sides of the photoresist completely-reserved region, which are vertical to the axis of the source electrode; etching the active layer by taking the photoresist mask layer as an anti-etching layer to obtain a preformed active region; removing the photoresist semi-reserved area; and etching the preformed active region by taking the photoresist complete reserved region as an anti-etching layer to obtain the active region. The invention also discloses a thin film transistor, an array substrate and a display device.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a manufacturing method thereof, an array substrate and a display device.
Background
At present, a thin film transistor liquid crystal display (TFT-LCD) occupies an absolutely dominant position in the field of display devices due to its excellent performance, but with the improvement of living standard of people, the requirement for display devices is higher and higher, high resolution displays are more and more popular in the market, and accordingly, the pressure faced by manufacturers of display devices is also higher and higher.
One important aspect in the fabrication of TFT array substrates is the fabrication of the active region. The active region is usually formed by etching using a photoresist as a mask. However, in the process of implementing the present invention, the inventors found that the conventional TFT manufacturing method has the following problems:
due to the existence of the edge step difference ramp of the active region pattern obtained by etching, after the source drain metal layer is formed on the active region pattern, when photoresist is coated on the upper surface of the source drain metal layer, the photoresist in the region corresponding to the edge step difference ramp is often thicker than other regions, and the thickness of the photoresist in the vertical direction is much larger than that of the region without the step difference, so that ultraviolet light in an exposure machine is difficult to penetrate through the photoresist film layer at the middle step difference ramp of the region corresponding to the edge step difference ramp, and photoresist residue is generated in the region after development, so that metal residue is also generated when the source drain metal layer is etched, and short circuit is generated at the channel of a TFT (thin film transistor), and poor display is caused.
Disclosure of Invention
In view of the above, the present invention provides a thin film transistor, a method for manufacturing the thin film transistor, an array substrate, and a display device, which can prevent a source/drain metal layer from being remained when a source/drain metal layer is etched due to insufficient exposure caused by an excessively thick photoresist at the bottom of an edge ramp of an active region, thereby preventing a short circuit of a source/drain at a channel of the thin film transistor.
Based on the above object, the present invention provides a method for manufacturing a thin film transistor, where the thin film transistor includes a source electrode and an active region, and the method for manufacturing the active region includes:
forming an active layer;
forming a photoresist mask layer on the active layer, wherein the photoresist mask layer comprises a photoresist semi-reserved region and a photoresist completely-reserved region, and the photoresist semi-reserved region is formed on two sides of the photoresist completely-reserved region, which are vertical to the axis of the source electrode;
etching the active layer by taking the photoresist mask layer as an anti-etching layer to obtain a preformed active region;
removing the photoresist semi-reserved area;
and etching the preformed active region by taking the photoresist complete reserved region as an anti-etching layer to obtain the active region.
Optionally, the slope angle of the active region is smaller than the slope angle of the pre-formed active region.
Optionally, the photoresist semi-reserved region surrounds the photoresist full-reserved region.
Optionally, the forming a photoresist mask layer on the active layer includes:
forming a photoresist layer on the active layer;
exposing the photoresist layer by adopting a half-tone mask;
and developing to obtain the photoresist mask layer.
Optionally, the active layer is etched and/or the pre-formed active region is etched by using a dry etching process; and/or, the photoresist semi-reserved area is removed by adopting an ashing process.
Optionally, before the forming the active layer, the method further includes:
and sequentially forming a grid electrode and a grid electrode insulating layer on the substrate.
Optionally, after obtaining the active region, the method further includes:
forming a source electrode and a drain electrode;
forming a passivation layer;
forming a via in the passivation layer;
and forming a pixel electrode which is electrically connected with the drain electrode through the through hole.
In a second aspect of the embodiments of the present invention, there is provided a thin film transistor, which is manufactured by the method for manufacturing a thin film transistor as described in any one of the preceding paragraphs.
Alternatively, the thin film transistor is suitable for a thin line technology.
In a third aspect of the embodiments of the present invention, there is provided an array substrate, including an array of thin film transistors as described in any one of the preceding claims.
In a fourth aspect of the embodiments of the present invention, there is provided a display device, including the array substrate as described above.
From the above, the thin film transistor, the manufacturing method thereof, the array substrate and the display device provided by the invention control the steepness of the ramp at the edge step difference position of the corresponding position of the active region by controlling the position and the width of the photoresist semi-reserved region, so as to slow down the steepness of the edge of the corresponding position of the active region, increase the length of the ramp, and prevent the source and drain metal layers from generating residue when being etched due to the fact that the photoresist at the bottom of the ramp at the corresponding position is too thick and cannot be fully exposed, thereby avoiding the short circuit of the source and drain at the TFT channel.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a thin film transistor according to a first embodiment of the present invention;
fig. 2a is a schematic structural diagram of a semi-finished thin film transistor after an active layer is formed in an embodiment of a method for manufacturing a thin film transistor according to the present invention;
fig. 2b is a schematic structural diagram of a semi-finished thin film transistor after a photoresist mask layer is formed in an embodiment of a method for manufacturing a thin film transistor provided by the present invention;
fig. 2c is a schematic structural diagram of a semi-finished thin film transistor after a pre-formed active region is obtained in an embodiment of a method for manufacturing a thin film transistor according to the present invention;
FIG. 2d is a schematic structural diagram of a semi-finished TFT after a photoresist semi-reserved region is removed in an embodiment of a method for fabricating a TFT according to the present invention;
fig. 2e is a schematic structural diagram of a semi-finished thin film transistor after an active region is obtained in an embodiment of a method for manufacturing a thin film transistor provided by the present invention;
fig. 2f is a schematic diagram illustrating a comparison of a slope angle between a preformed active region and an active region in an embodiment of a method for manufacturing a thin film transistor according to the present invention;
FIG. 2g is a schematic structural diagram of a semi-finished TFT after a photoresist complete retention region is stripped in an embodiment of a method for manufacturing a TFT according to the present invention;
fig. 2h is a schematic structural diagram of a thin film transistor after other layers are formed in the embodiment of the method for manufacturing a thin film transistor according to the present invention;
FIG. 3 is a schematic diagram of a prior art and/or exemplary thin line technology array substrate;
FIG. 4 is a schematic cross-sectional view of an active silicon island of one TFT of a prior art fine-line technology array substrate during a manufacturing process;
FIG. 5 is an enlarged structural diagram of one TFT of the prior art fine line technology array substrate after an active layer silicon island is formed;
fig. 6 is a schematic flow chart of a manufacturing method of a thin film transistor according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings. The dimensions and shapes in the drawings are not intended to reflect the true scale of the proposed apparatus and are merely intended to illustrate the invention.
Based on the above object, a first aspect of the embodiments of the present invention provides a first embodiment of a method for manufacturing a thin film transistor, which can prevent a source/drain metal layer from being remained when being etched due to insufficient exposure caused by an excessively large thickness of a photoresist at the bottom of an edge ramp of an active region, thereby avoiding a short circuit of a source/drain at a channel of the thin film transistor. Fig. 1 is a schematic flow chart of a method for manufacturing a thin film transistor according to a first embodiment of the present invention.
The manufacturing method of the thin film transistor comprises a source electrode and an active region, and the manufacturing method of the active region comprises the following steps (the cross-sectional views shown in figures 2 a-2 g can refer to the cross-section in the direction B-B in figure 3, and the cross-sectional view shown in figure 2h can refer to the cross-section in the direction C-C in figure 3):
step 101: as shown in fig. 2a, an active layer 40 is formed; optionally, as shown in fig. 2a, the active layer 40 is formed on a partially completed array substrate on which other layers have been deposited, the partially completed array substrate includes, from bottom to top, the substrate 10, the gate electrode 20, the gate insulating layer 30, and the active layer 40, wherein: the gate 20 may be a metal layer of Cr, Al, Cu, Ti, Ta, or Mo, or an alloy layer formed of at least two of Cr, Al, Cu, Ti, Ta, or Mo, and may have a thickness of about 300 nm; the gate insulating layer 30 may be a SiNx layer, a SiOx layer, or a composite layer of SiNx and SiOx, and may have a thickness of about 500 to 600 nm; the active layer 40 may be made of amorphous silicon, polysilicon, etc., and the thickness of the active layer may be about 400-600 nm.
Step 102: as shown in fig. 2b, a photoresist mask layer 50 is formed on the active layer 40, the photoresist mask layer 50 includes a photoresist semi-reserved region 51 and a photoresist complete-reserved region 52, and the photoresist semi-reserved region 51 is formed on two sides of the photoresist complete-reserved region 52, which are perpendicular to the axis of the source electrode 61; referring to fig. 3, two sides of the photoresist full reserved region 52 perpendicular to the axis of the source 61 may refer to two sides D1 and D2 between the corresponding position of the source 61 and the corresponding position of the drain 62, perpendicular to the axis of the source 61 (i.e., the center line of the source 61), and corresponding to the active region 42; referring also to FIG. 5, the locations of region A1 and region A2 are framed; therefore, after subsequent processing, the steepness of the slopes at the two sides of the active region 42 corresponding to the position will be reduced, so as to avoid the source-drain short circuit problem caused by the excessive thickness of the photoresist film layer at the position.
Alternatively, the photoresist mask layer 50 may be fabricated above the active layer 40 by using a half-tone mask (Halftone mask) technique. Specifically, the photoresist mask layer 50 may be fabricated by the following method: forming a photoresist layer on the active layer 40; exposing the photoresist layer by adopting a half-tone mask; and developing to obtain the photoresist mask layer 50. Thus, the photoresist mask layer 50 can be formed at one time by using the halftone mask, thereby saving the process and improving the manufacturing efficiency. Preferably, the photoresist half-reserved region 51 surrounds the photoresist full-reserved region for one circle, and the width of the photoresist half-reserved region 51 is L, so that the slope angles around the finally formed active region can be kept consistent, the consistency around the active region is increased, and the manufacturing process is simplified. The width L may be designed according to an actually required slope angle, and is not limited herein.
Step 103: as shown in fig. 2c, the active layer 40 is etched by using the photoresist mask layer 50 as an anti-etching layer, so as to obtain a preformed active region 41;
optionally, an ICP (Inductively Coupled Plasma) etching apparatus is used, and SF is used6And for etching gas, the photoresist mask layer 50 is used as an anti-etching layer, and the preformed active region 41 is manufactured through a first dry etching process, so that the preformed active region 41 with a better edge shape can be obtained. As shown in fig. 2c, the preformed active region 41 has a relatively steep slope at its edge as the active region produced in the conventional process, and theoretically, the slope angle of the slope can be reduced by controlling the etching parameters, but the adjustment degree of reducing the slope angle of the slope by controlling the etching parameters is limited.
Step 104: as shown in fig. 2d, the photoresist semi-reserved region 51 is removed;
optionally, an ashing process is used to remove the photoresist semi-reserved region 51, and only the photoresist complete-reserved region 52 is reserved, so that the photoresist semi-reserved region 51 can be better removed. Theoretically, ashing of the photoresist means etching away the photoresist as an etching target, and therefore, as can be seen from fig. 2d, the photoresist complete reserve region 52 is reduced in thickness after the ashing process.
Step 105: as shown in fig. 2e, the photoresist complete remaining region 52 is used as an anti-etching layer to etch the preformed active region 41, so as to obtain the active region 42;
as shown in fig. 2d, after removing the photoresist semi-reserved region 51, the region with the edge width L of the preformed active region 41 is exposed, optionally, a second dry etching process is performed on the region with the edge width L of the preformed active region 41 which has a certain slope, so as to further form a slope with a smaller slope angle on the slope which has been formed, by dry etching, thereby reducing the steepness at the edge step difference, after the etching is completed, as shown in fig. 2e, the upper edge portion of the active region 42 is recessed inward by a distance L compared to the upper edge portion of the preformed active region 41, thereby preparing the active region 42 with a smaller steepness at the edge step difference compared to the preformed active region 41, i.e., the slope angle β of the source and drain active regions 42 is smaller than the slope angle α of the preformed active region 41, thus, when other layers are continuously fabricated on the active region 42, preventing the occurrence of residual metal layer (TFT) at the time of the transistor which is not sufficiently exposed due to the excessive thickness of the photoresist at the bottom slope, thereby avoiding short-circuit etching of the TFT.
Specifically, as shown in fig. 2f, the slope angle at the edge step of the preformed active region 41 before the second dry etching is not performed is α, the slope angle at the edge step of the active region 42 after the second dry etching is β, the distance that the upper portion of the edge of the active region 42 retracts inward after the second dry etching is L, the retraction distance of the lower portion of the edge of the active region 42 is significantly less than L, and β is less than α after the second dry etching is completed, so that the slope angle at the edge step of the active region 42 can be reduced.
It should be noted that, the steps of the first dry etching and the second dry etching may be selected from a combination of physical dry etching and chemical dry etching, that is, a mixed etching process of physical dry etching and chemical dry etching may be adopted; optionally, during the second dry etching, in order to achieve a better effect of controlling the slope angle, the lower electrode power of the ICP apparatus may be appropriately reduced, that is, the effect of physical bombardment is reduced, so that the chemical etching reaction etching is dominant, and thus the bombardment on the sidewall can be weakened, thereby further reducing the slope angle.
Optionally, after the above steps are completed, the method further includes step 106: the photoresist fully remaining region 52 is stripped away, as shown in fig. 2g, to produce an active region 42 with a controlled degree of slope angle reduction. Therefore, the gradient of the ramp at the edge step difference of the active region 42 can be controlled by controlling the width of the photoresist semi-reserved region 51, so that the gradient of the edge of the active region 42 is reduced, the length of the ramp is increased, the phenomenon that a source/drain metal layer is remained when being etched due to the fact that the photoresist at the bottom of the ramp is too thick and cannot be fully exposed is avoided, the short circuit of a source/drain at the position of a TFT channel is avoided, and the yield is improved.
Further, the method can further include step 107: other layers were prepared to obtain a thin film transistor as shown in fig. 2 h.
It can be seen from the foregoing embodiments that, in the manufacturing method of the thin film transistor provided in the embodiments of the present invention, the steepness of the ramp at the edge step at the corresponding position of the active region is controlled by controlling the position and the width of the photoresist semi-reserved region, so as to slow down the steepness of the edge at the corresponding position of the active region, increase the length of the ramp, and prevent the source/drain metal layer from being left when being etched due to insufficient exposure caused by too large thickness of the photoresist at the bottom of the ramp at the corresponding position, thereby avoiding short circuit of the source/drain at the TFT channel.
Preferably, the method for manufacturing the thin film transistor can be applied to the manufacturing of an array substrate by a line thinning technology. The corresponding description is made below.
High PPI (Pixels Per Inch) displays have gradually become the mainstream of the market, but since the price of an exposure machine is expensive and the updating is slow, a line thinning technology is developed, and by means of the line thinning technology, the limit of the exposure machine which is widely used at present can be broken through, a fine photoresist mask pattern can be manufactured, and the resolution of the product is improved. However, in the thinning technique, there are many problems, and in order to increase the aperture ratio in the array substrate shown in fig. 3, in general, the active layer silicon island 42/42 ' (which may correspond to the active region 42) is directly formed on the scan line 20/20 ' (which may correspond to the gate electrode 20), the data line 61/61 ' (which may correspond to the source electrode 61) is directly formed on the active layer silicon island 42/42 ' as the source electrode 61/61 ' of the TFT, and the active layer between the data line 61/61 ' and the drain electrode 62/62 ' is used as the channel of the TFT. As shown in fig. 4, in the prior art, due to the existence of the edge step of the active layer silicon island 42 ', when the upper surface of the source/drain metal layer 60' is coated with the photoresist 50 ', the photoresist of the area a is often thicker than other areas, and the thickness of the photoresist in the vertical direction is much larger than that of the area without the step, so that the ultraviolet light in the exposure machine is difficult to penetrate through the photoresist film layer at the step ramp in the area a, thereby causing the photoresist residue in the area a after development, and thus, when the source/drain metal layer 60' is etched, the metal residue is also caused, thereby causing the short circuit at the channel of the TFT and causing the poor display. As shown in fig. 5, which is an enlarged structural diagram of a TFT region in an array substrate in the prior art, a source/drain metal layer 60 '(refer to fig. 4) at a level difference of an active layer silicon island 42' in fig. 5 remains after etching (refer to a metal remaining region formed between a data line 61 'and a drain electrode 62' in fig. 5, see locations outlined by a region a1 and a region a2 in fig. 5). There are many methods to solve the problem of insufficient exposure of the photoresist at the step, such as increasing the exposure dose or reducing the steepness of the ramp at the step, but simply increasing the exposure dose will increase the distance between the source and drain electrodes (when using a positive photoresist), so that the width of the channel deviates from the preset value, resulting in the performance degradation of the thin film transistor.
In view of the above problems, the method for manufacturing a thin film transistor provided in the foregoing embodiments of the present invention can be used as a method for manufacturing a thin film transistor suitable for an array substrate in a thinning technique. By adopting the manufacturing method of the thin film transistor provided by the embodiment, when the active layer silicon island pattern is manufactured, the half-reserved photoresist area is manufactured at the edge position corresponding to the active layer silicon island by using the halftone mask technology, after the preformed active layer silicon island pattern is manufactured, the half-reserved photoresist area is removed by using the ashing process, and the edge of the preformed active layer silicon island pattern is etched again, so that the straightness of the ramp at the edge section difference position of the corresponding position of the active layer silicon island can be controlled by controlling the position and the width of the half-reserved photoresist area, the straightness of the edge at the corresponding position of the active layer silicon island can be reduced, the length of the ramp can be increased, the situation that a source drain metal layer is remained when being etched due to the fact that the photoresist at the bottom of the ramp at the corresponding position is too thick and cannot be fully exposed can be prevented, and the short circuit of a thin line source drain electrode at the channel position of a TFT (thin film transistor) can be, the yield is improved.
Of course, the method for manufacturing a thin film transistor according to the embodiment of the present invention is not limited to the thinned array substrate described above, and may be any array substrate as long as it can use an active layer silicon island manufactured by the method for manufacturing a thin film transistor according to the embodiment of the present invention.
The invention also provides a second embodiment of the manufacturing method of the thin film transistor, which can prevent the source and drain metal layers from generating residues when being etched because the photoresist at the bottom of the edge ramp of the active region is too thick and cannot be fully exposed, thereby avoiding the short circuit of the source and drain at the channel of the thin film transistor. Fig. 6 is a schematic flow chart of a manufacturing method of a thin film transistor according to a second embodiment of the present invention.
The manufacturing method of the thin film transistor comprises the following steps:
step 201: referring to fig. 2a, a gate electrode 20 and a gate insulating layer 30 are sequentially formed on a substrate 10; the gate 20 may be a metal layer of Cr, Al, Cu, Ti, Ta, or Mo, or an alloy layer formed of at least two of Cr, Al, Cu, Ti, Ta, or Mo, and may have a thickness of about 300 nm; the gate insulating layer 30 may be a SiNx layer, a SiOx layer, or a composite layer of SiNx and SiOx, and may have a thickness of about 500 to 600 nm.
Step 202: as shown in fig. 2a, an active layer 40 is formed on the gate insulating layer 30; the active layer 40 may be made of amorphous silicon, polysilicon, etc., and the thickness of the active layer may be about 400-600 nm.
Step 203: as shown in fig. 2b, a photoresist mask layer 50 is formed on the active layer 40, the photoresist mask layer 50 includes a photoresist semi-reserved region 51 and a photoresist complete-reserved region 52, and the photoresist semi-reserved region 51 is formed on two sides of the photoresist complete-reserved region 52, which are perpendicular to the axis of the source electrode 61;
alternatively, the photoresist mask layer 50 may be fabricated above the active layer 40 by using a half-tone mask (Halftone mask) technique. Specifically, the photoresist mask layer 50 may be fabricated by the following method: forming a photoresist layer on the active layer 40; exposing the photoresist layer by adopting a half-tone mask; and developing to obtain the photoresist mask layer 50. Thus, the photoresist mask layer 50 can be formed at one time by using the halftone mask, thereby saving the process and improving the manufacturing efficiency. Preferably, the photoresist half-reserved region 51 surrounds the photoresist full-reserved region for one circle, and the width of the photoresist half-reserved region 51 is L, so that the slope angles around the finally formed active region can be kept consistent, the consistency around the active region is increased, and the manufacturing process is simplified. The width L may be designed according to an actually required slope angle, and is not limited herein.
Step 204: as shown in fig. 2c, the active layer 40 is etched by using the photoresist mask layer 50 as an anti-etching layer, so as to obtain a preformed active region 41;
optionally, an ICP (Inductively Coupled Plasma) etching apparatus is used, and SF is used6And for etching gas, the photoresist mask layer 50 is used as an anti-etching layer, and the preformed active region 41 is manufactured through a first dry etching process, so that the preformed active region 41 with a better edge shape can be obtained. As shown in fig. 2c, the preformed active region 41 has a relatively steep slope at its edge as the active region produced in the conventional process, and theoretically, the slope angle of the slope can be reduced by controlling the etching parameters, but the adjustment degree of reducing the slope angle of the slope by controlling the etching parameters is limited.
Step 205: as shown in fig. 2d, the photoresist semi-reserved region 51 is removed;
optionally, an ashing process is used to remove the photoresist semi-reserved region 51, and only the photoresist complete-reserved region 52 is reserved, so that the photoresist semi-reserved region 51 can be better removed. Theoretically, ashing of the photoresist means etching away the photoresist as an etching target, and therefore, as can be seen from fig. 2d, the photoresist complete reserve region 52 is reduced in thickness after the ashing process.
Step 206: as shown in fig. 2e, the photoresist complete remaining region 52 is used as an anti-etching layer to etch the preformed active region 41, so as to obtain the active region 42;
as shown in fig. 2d, after removing the photoresist semi-reserved region 51, the region with the edge width L of the preformed active region 41 is exposed, optionally, a second dry etching process is performed on the region with the edge width L of the preformed active region 41 which has a certain slope, so as to further form a slope with a smaller slope angle on the slope which has been formed, by dry etching, thereby reducing the steepness at the edge step difference, after the etching is completed, as shown in fig. 2e, the upper edge portion of the active region 42 is recessed inward by a distance L compared to the upper edge portion of the preformed active region 41, thereby preparing the active region 42 with a smaller steepness at the edge step difference compared to the preformed active region 41, i.e., the slope angle β of the source and drain active regions 42 is smaller than the slope angle α of the preformed active region 41, thus, when other layers are continuously fabricated on the active region 42, preventing the occurrence of residual metal layer (TFT) at the time of the transistor which is not sufficiently exposed due to the excessive thickness of the photoresist at the bottom slope, thereby avoiding short-circuit etching of the TFT.
Step 207: the photoresist full reserve region 52 is stripped away, thereby producing the active region 42 with a controlled degree of slope angle reduction.
Step 208: referring to fig. 2h, a source electrode 61 and a drain electrode 62 are formed; optionally, a source/drain metal layer is deposited and grown, and then a source (data line) 61 and a drain 62 are prepared by a patterning process.
Step 209: referring to fig. 2h, a passivation layer 70 is formed, and the passivation layer 70 may protect a back channel of the TFT; alternatively, the passivation layer 70 may be a SiNx layer, a SiOx layer, or a composite layer of SiNx and SiOx.
Step 210: referring to fig. 2h, a via hole 71 is formed in the passivation layer 70; optionally, the via hole 71 is manufactured by a passivation layer patterning process.
Step 211: referring to fig. 2h, forming a pixel electrode 80, wherein the pixel electrode 80 is electrically connected with the drain electrode 62 through the via hole 71; optionally, a transparent ITO pixel electrode layer is grown by sputtering, and then the ITO pixel electrode 80 is manufactured by an ITO pixel electrode layer patterning process.
Through the manufacturing method of the thin film transistor, the finally manufactured TFT can prevent the source and drain metal layer from being remained when being etched due to the fact that the photoresist at the bottom of the ramp is too thick and cannot be fully exposed, and therefore short circuit of the source and drain at the position of a TFT channel is avoided.
Based on the above object, a second aspect of the embodiments of the present invention provides an embodiment of a thin film transistor manufactured by using the above manufacturing method of a thin film transistor, which can prevent a source/drain metal layer from being remained when being etched due to insufficient exposure caused by too large thickness of a photoresist at the bottom of an edge ramp of an active region, thereby avoiding short circuit of a source/drain at a channel of the thin film transistor.
Referring to fig. 2h, the thin film transistor is manufactured by using the method for manufacturing a thin film transistor according to any of the previous embodiments.
It can be seen from the foregoing embodiments that, in the thin film transistor provided in the embodiments of the present invention, the steepness of the ramp at the edge step at the corresponding position of the active region is controlled by controlling the position and the width of the photoresist half-reserved region, so as to slow down the steepness of the edge at the corresponding position of the active region, increase the length of the ramp, and prevent the source and drain metal layers from being remained when being etched due to insufficient exposure caused by the excessively large thickness of the photoresist at the bottom of the ramp at the corresponding position, thereby avoiding the short circuit of the source and drain at the TFT channel.
Preferably, the thin film transistor is suitable for a fine line technology. Therefore, when the thin film transistor is applied to the fine line technology, the thin film transistor can better prevent the source and drain metal layer from being remained when being etched due to the fact that the photoresist at the bottom of the ramp is too thick and cannot be fully exposed, so that the short circuit of the source and drain at the TFT channel of the array substrate of the fine line technology is avoided, and the yield of the array substrate is improved.
Based on the above object, a third aspect of the embodiments of the present invention provides an embodiment of an array substrate, which can prevent a source/drain metal layer from being remained when being etched due to insufficient exposure caused by an excessively large thickness of a photoresist at the bottom of an edge ramp of an active region, thereby avoiding a short circuit of a source/drain at a channel of a thin film transistor of the array substrate.
The array substrate comprises an array of thin film transistors as described in any of the previous embodiments.
It can be seen from the foregoing embodiment that, in the array substrate provided in the embodiment of the present invention, the steepness of the ramp at the edge step at the corresponding position of the active region is controlled by controlling the position and the width of the photoresist half-reserved region, so as to slow down the steepness of the edge at the corresponding position of the active region, increase the length of the ramp, and prevent the source and drain metal layers from being remained when being etched due to insufficient exposure caused by the excessively large thickness of the photoresist at the bottom of the ramp at the corresponding position, thereby avoiding the short circuit of the source and drain at the TFT channel.
Preferably, the array substrate is suitable for a fine line technology. Thus, when applied to the thinning technique, the half-tone mask technique is used to pattern the active silicon islands of the thin film transistors of the array substrate, a circle of photoresist semi-reserved area is manufactured at the edge position corresponding to the active layer silicon island, after the active layer silicon island pattern is manufactured, removing the photoresist semi-reserved region by ashing process, etching the preformed active layer silicon island edge again, the gradient straightness of the ramp at the edge step of the active layer silicon island can be controlled by controlling the width of the photoresist semi-reserved area, so as to reduce the steepness of the edge of the active layer silicon island, increase the length of the ramp, prevent the source and drain metal layers from being remained when being etched because the photoresist at the bottom of the ramp is too thick and cannot be fully exposed, therefore, the short circuit of the source and the drain at the TFT channel of the array substrate adopting the fine line technology is avoided, and the yield of the array substrate is improved.
Based on the above object, a fourth aspect of the embodiments of the present invention provides an embodiment of a display device, which can prevent a source/drain metal layer from being remained when being etched due to insufficient exposure caused by an excessively large thickness of a photoresist at a bottom of an edge ramp of an active region, thereby avoiding a short circuit of a source/drain at a channel of a thin film transistor of an array substrate of the display device.
The display device comprises the array substrate according to any one of the previous embodiments. The display device may be: the OLED display panel comprises any product or component with a display function, such as an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It can be seen from the foregoing embodiments that, in the display device provided in the embodiments of the present invention, the steepness of the ramp at the edge step at the corresponding position of the active region is controlled by controlling the position and the width of the photoresist half-reserved region, so as to slow down the steepness of the edge at the corresponding position of the active region, increase the length of the ramp, and prevent the source and drain metal layers from being remained when being etched due to insufficient exposure caused by the excessively large thickness of the photoresist at the bottom of the ramp at the corresponding position, thereby avoiding the short circuit of the source and drain at the TFT channel of the array substrate of the display device.
Those of ordinary skill in the art will understand that: the invention is not to be considered as limited to the specific embodiments thereof, but is to be understood as being modified in all respects, all changes and equivalents that come within the spirit and scope of the invention.
Claims (10)
1. A method for manufacturing a thin film transistor, the thin film transistor comprising a source electrode and an active region, the method for manufacturing the active region comprising:
forming an active layer;
forming a photoresist mask layer on the active layer, wherein the photoresist mask layer comprises a photoresist semi-reserved region and a photoresist complete-reserved region, and the photoresist semi-reserved region is formed on two sides of the photoresist complete-reserved region; the two sides of the photoresist complete retention region, on which the photoresist semi-retention region is formed, are two sides perpendicular to the axis of the source electrode;
etching the active layer by taking the photoresist mask layer as an anti-etching layer to obtain a preformed active region;
removing the photoresist semi-reserved area;
and etching the preformed active region by taking the photoresist complete reserved region as an anti-etching layer to obtain the active region, wherein the slope angle of the active region is smaller than that of the preformed active region.
2. The method of claim 1, wherein the semi-reserved photoresist region surrounds the fully reserved photoresist region.
3. The method of claim 1, wherein forming a photoresist mask layer on the active layer comprises:
forming a photoresist layer on the active layer;
exposing the photoresist layer by adopting a half-tone mask;
and developing to obtain the photoresist mask layer.
4. The method according to claim 1, wherein the etching the active layer and/or the etching the pre-formed active region is performed by a dry etching process; and/or, the photoresist semi-reserved area is removed by adopting an ashing process.
5. The method of claim 1, wherein before the forming the active layer, further comprising:
a gate electrode and a gate insulating layer are sequentially formed on a substrate.
6. The method of claim 1, wherein after obtaining the active region, further comprising:
forming a source electrode and a drain electrode;
forming a passivation layer;
forming a via in the passivation layer;
and forming a pixel electrode which is electrically connected with the drain electrode through the through hole.
7. A thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of claims 1 to 6.
8. The thin film transistor according to claim 7, wherein the thin film transistor is applied to a thinning technique.
9. An array substrate comprising an array of thin film transistors according to claim 7 or 8.
10. A display device comprising the array substrate according to claim 9.
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| CN112310273B (en) * | 2019-07-29 | 2023-04-07 | 中电海康集团有限公司 | Magnetic tunnel junction and preparation method thereof |
| CN110636420B (en) * | 2019-09-25 | 2021-02-09 | 京东方科技集团股份有限公司 | Film loudspeaker, preparation method of film loudspeaker and electronic equipment |
| CN111462615B (en) * | 2020-04-27 | 2022-04-08 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
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