CN107194044A - A kind of FIR filter fault filling method operated based on input and output data - Google Patents
A kind of FIR filter fault filling method operated based on input and output data Download PDFInfo
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Abstract
The present invention relates to a kind of FIR filter fault filling method operated based on input and output data, if the tap of FIR filter is L, fault filling method is：Original FIR processing logic is replicated, the FIR filter parallel processing structure of two branch roads is formed, is referred to as the first FIR filter and the second FIR filter, and lengthens produced input traffic as far as possible；Input data is just changed into an input data every L length, direct fault location is carried out to the first wave filter, and the input data of the second FIR filter keeps constant, and the output of two-way FIR filter is carried out into cross-combining.
Description
Technical field
The invention belongs to field of signal processing, it is related to the fault-tolerant design of signal transacting, more particularly, to for FIR filter
Direct fault location and fault-tolerant design application.
Background technology
Embedded system (including digital signal processor DSP s, FPGA FPGAs etc.) rely on its powerful calculating
Ability and repeatable programing function, are considered in the environment of some high reliability more and more, wherein spaceborne number
Word signal processing platform is a critically important application scenarios[1].But exactly it can configure, programmable characteristic, make this kind of phase
Between it is more sensitive for Space Particle irradiation effect, and most important effect is exactly single-particle inversion (SEU) among these, and it is to make
Into the main cause of DSP and FPGA failures[1].Therefore, design high reliability SEU fault-tolerance approaches are by DSP and FPGA successful applications
In the key of payload on star.Because system failure behavior can not be fully described in mathematical modeling[2], in order to which critical appraisal is fault-tolerant
Method validity using means such as ground irradiation or fault injection experiments, it is necessary to carry out the influence that simulated failure is caused.Due to ground
Irradiation experiment cost is higher, and easily causes the irreversible damage to device, platform, thus it is general only in system development most
The stage uses afterwards.Comparatively, fault filling method cost is relatively low, and operation is flexible, is especially suitable for system development and is directed to initial stage
The fault freedom checking of key modules.
For being usually embedded formula system, direct fault location can be divided into hardware fault injection, software fault injection and simulated failure
Inject three classes[2][5][9]。
(1) " hardware fault injection "：By physical means directly by the hardware of direct fault location to goal systems.It is specific next
Say, it is necessary to attach probe to some pins of system, using force by some logics in system as or memory cell be set to
The value specified.Because not all SEU sensitive nodes can be directly or indirectly connected to probe, this method
It is very limited [9] using scope.Especially for the FPGA (SRAM-FPGA) based on SRAM, most of SEU sensitive nodes all make
Sram cell, it is impossible to be attached by probe, so hardware fault injection method is unsuitable for noting for SRAM-FPGA failure
Enter.
(2) " software fault injection "：Realized by the instruction set of calling system and memory or content of registers are repaiied
Change, and logic function change, so as to simulate SEU effects.This modification process needs to use the instruction set of system, therefore claims
It is software approach.The advantage of this method is that development process is relatively easy, without complex appts, has the disadvantage that instruction set can only be changed
Part in opereating specification.The FERRARI systems that document [10] is proposed just belong to this kind of.For SRAM-FPGA systems, it is exactly
Insertion modification memory or the sentence of content of registers among original VHDL is designed, to reach simulation SEU purpose.For
It is exactly insertion modification memory or the language of content of registers in original C code or assembly code design for dsp system
Sentence, to reach simulation SEU purpose.Although this method is simple, compiling is re-started every time and comprehensive, compare consumption
When.
(3) " simulated fault injection "：It is that test system sets up hardware simulation model using hardware description language, then in mould
Direct fault location unit is inserted inside type to realize the injection of failure.The advantage of this method is that controllability is good, has the disadvantage to set up imitative
True mode is relatively difficult.Document [11] and [12] are all the examples of this kind of method.For the system based on FPGA, institute is active
Originally it can be set up, therefore can be classified as in the FPGA methods for developing each stage injection failure with hardware description language
Simulated fault method for implanting.And " software fault injection " method above-mentioned simply carries out failure in VHDL model design phases
Injection, therefore also can be considered a kind of mode of simulated fault injection.
In summary, hardware fault injection mode is the most direct, but cost and complexity highest, and can inject failure
Region is limited；The complexity relative reduction of software and simulated fault injection mode, it is also relatively more flexible, but be due to that direct fault location is patrolled
Collecting need to be embedded among original logic, therefore be required for redesigning original signal processing logic, and this is multiple for some
Enforcement difficulty is larger for miscellaneous processing logic.
FIR filter is a kind of typical convolutional coding structure, is widely applied in various types of signal processing and communication system, including
On Space-borne, therefore the important object [13] [14] [15] [16] [17] as fault-tolerant signal transacting.FIR filtering process is allusion quotation
The multiply-add logic of type, wherein being shift register [18] for the most sensitive region of space radiation, therefore is to carry out failure note
The main target entered.Fault type mainly considers soft error, i.e. register physical device is not damaged, simply wherein stores
Data are changed due to SEU, and this wrong data will be displaced in next register with filtering process, and star is moved
The data entered are still correct.Furthermore, it is contemplated that space radiation is openness, does not have two registers typically and occur simultaneously
Failure.
For the efficient fault filling method of FIR filter research, by effective fault-tolerant design accelerated for FIR filter
Work, promotes the innovation of related direction.
Bibliography
[1]Kastensmidt FL,Carro L,Reis R.Fault-tolerance Techniques for SRAM-
based FPGAs[M].New Haven:Springer 2006.
[2]Benso A,Prinetto P.Fault Injection Techniques and Tools for
Embedded System Reliability Evaluation[M],Kluwer Academic Publishers,2003.
Present Research [J] aerospace journals of the such as [3] Sun Junchao, Wang Jianying, Yang Xiaozong fault filling methods and instrument,
2001,22(1):99~103.
[4] Li Huawang, Haitao Liu, poplar root celebrating Aerospace SEP Fault Injection System research [J] quantum electronicses
Report, 2002,19 (1):57~60.
[5] fault injection system research [D] the Xi'an of Wu sage pottery .SRAM type FPGA single particle reversal effects:Xi'an electronics
University of Science and Technology, 2011.
[6] Sun Peng anti-single particles upset SRAM-based FPGA Research on Testing System and design [D] Shanghai:Fudan University is big
Learn, 2010.
[7] Xing Ke flies the detection of Spaceborne signal processing platforms single particle effect and reinforcement technique research [D] Changsha:National defence section
Skill university, 2007.
[8] the embedded Modern Small Satellites software fault-tolerant design of the prosperous space flight of Li Hua and Research on Testing System [D] Shanghai:China
Shanghai Metallurgical Industry research institute of the academy of sciences, 2001.
[9]LIMAF,REZGUI S,CARRO L,et al.On the use of VHDL simulation and
emulation to derive error rates[C].Proc.of RADECS 2001.
[10]Kanawati G A,Kanawati N A,Abraham J A.FERRARI:A Flexible
Software-Based Fault and Error Injection System[J].IEEE Trans.on Computers,
1995,44(2):248-260.
[11]Jenn E,Arlat J,Rimen M,et al.Fault Injection into VHDL Models:the
MEFISTO Tool[C],Proc.24th FTCS,1994,pp.66-75.
[12]Delong T A,Johnson B W,Profeta J A.A fault injection technique
for VHDL behavioral-level models[C].IEEE Design&Test of Computers,New York,
1996.
[13]P.Reviriego,C.J.Bleakley,and J.A.Maestro,“Structural DMR:A
technique for implementation of soft-error-tolerant FIR filters,”IEEE
Trans.Circuits Syst.II,Exp.Briefs,vol.58,no.8,pp.512–516,Aug.2011.
[14]T.Hitana and A.K.Deb,“Bridging concurrent and non-concurrent
error detection in FIR filters,”in Proc.Norchip Conf.,2004,pp.75–78.
[15]S.Pontarelli,G.C.Cardarilli,M.Re,andA.Salsano,“Totally fault
tolerant RNS based FIR filters,”in Proc.IEEE IOLTS,2008,pp.192–194.
[16]Z.Gao,P.Reviriego,W.Pan,Z.Xu,M.Zhao,J.Wang.Efficient Arithmetic
Residue Based SEU-tolerant FIR Filter Design,IEEE Transaction on Circuit and
System II,Vol.60,No.8,Aug.2013.
[17]Z.Gao,P.Reviriego,Z.Xu,X.Su,J.Wang,and J.A.Maestro.Efficient
Coding Schemes for Fault-Tolerant Parallel Filters,IEEE Transaction on
Circuit and System II,Vol.62,No.7,Feb.2015.
[18]Z.Gao,W.Yang,X.Chen,M.Zhao,and J.Wang,“Fault missing rate
analysis of the arithmetic residue codes based fault-tolerant FIR Filter
design,”in Proc.IEEE IOLTS,2012,pp.130–133.
The content of the invention
It is contemplated that proposing a kind of direct fault location side operated based on input data and output data for FIR filter
Method, in the case where not redesigned to original processing logic, completes the direct fault location to FIR filtering operations.By institute
The method of design is relevant only with the length of FIR filter, and unrelated with specific filter factor, therefore relative to original logic phase
To independence, can in the case where not influenceing original design neatly design error failure injection circuit, so as to increase substantially failure
The efficiency of injection.Technical scheme is as follows：
A kind of FIR filter fault filling method operated based on input and output data, if the tap of FIR filter is
L, fault filling method is：
(1) original FIR processing logic is replicated, forms the FIR filter parallel processing structure of two branch roads, point
It is also known as the first FIR filter and the second FIR filter, and lengthens produced input traffic as far as possible；
(2) input data is just changed into an input data every L length, carries out direct fault location to the first wave filter, and the
The input data of two FIR filters keeps constant；If input data length is NL, output data length is also NL, by the first FIR
Filtering output data caused by wave filter, the second FIR filter and final direct fault location is all divided into N sections, is L per segment length,
The output data of two-way filter and desired direct fault location simulation output are expressed asAnd On(l), wherein
N=0,1,2 ..., N-1 represent the position of data segment, and l=0,1,2 ..., L-1 represents the position of the data in every section, for n-th
For segment data, if l-th of shift register breaks down, On(l) L data in this paragraph can be obtained by the following method
：
1) the preceding l data in the n-th segment data of the second FIR filter are taken out；
2) the front and rear L-l data in the n-th segment data of the first FIR filter are taken out；
3) it two end datas will splice above, and form L data, be expressed as
This method constructs the FIR filter structure of two branch roads, and the input number of a path filter thereto first
According to direct fault location has been carried out, then selected and spliced by the output data to two-way FIR filter, complete to filter FIR
The direct fault location simulation of shift register in ripple device.This method is only operated to input and output data, it is not necessary to FIR
The realization of wave filter is modified, therefore is well suited for being used for carrying out fault injection experiment to existing filtering logic.In addition, based on one
Result obtained by secondary input data modification, two-way FIR filter is used directly for a variety of different shift registers and occurs event
The simulation of barrier, it is no longer necessary to re-start FIR filtering process.This method is simple and easy to apply, is greatly improved the failure mould of correlation
Intend the execution efficiency verified with fault-tolerant design.Simulating, verifying shows that the fault filling method proposed can be with the accurate mould in 100% ground
Intend the effect of the direct fault location for FIR filter, execution efficiency is high and simple to operate.
Brief description of the drawings
The structure of Fig. 1 Direct-type FIR Filters
The FIR filter fault filling method that Fig. 2 is operated based on input data and output data
Fig. 3 shift registers D5The effect that 0th bit is overturn
Fig. 4 shift registers D5The effect in latter sampling period of upset occurs for the 0th bit
Fig. 5 shift registers D5The effect for overturning latter two sampling period occurs for the 0th bit
Fig. 6 shift registers D5The effect in three sampling periods after 0th bit is overturn
Embodiment
The present invention provides a kind of fault filling method operated based on input data and output data for FIR filter.
This method constructs the FIR filter structure of two branch roads first, and inputs identical data, and then one of FIR is filtered
The input of device is periodically changed, and most the output of two-way FIR filter is merged at last, the filter formed after direct fault location
Ripple device result.Comprise the following steps that：
First, the FIR filter parallel processing structure of two branch roads is constructed
In order to carry out direct fault location to FIR filter, original FIR processing logic is replicated first, one two is formed
The FIR filter parallel processing structure of branch road, is referred to as FIR filter 1 and FIR filter 2.
The input of two FIR filter branch is identical when initial.In order to travel through the event under the conditions of different input datas
Barrier injection result, can lengthen produced input traffic as far as possible according to experiment condition.
2nd, the input to FIR filter all the way carries out periodicity modification
In actual FIR filter operating process, the mistake output caused by shift register failure is with breaking down
Shift register positions it is relevant.For having the FIR filter of L tap, if in sometime i, l-th of shift LD
Device breaks down, then L-l mistake after this moment will be caused to export.And after L-l sampling period, failure shift LD
The value of device has moved out FIR filter, will not reproduce into mistake output.Therefore, broken down for l-th of shift register
Simulation, it is important to produce this L-l mistake output.
FIR filter 1, will some input data move into wave filter before just changed (fault simulation), then it will be
There is the L data cycle (L bats) in FIR filtering process, L mistake output is produced altogether.For simulating l-th of shift register
Situation about breaking down, as long as the rear L-l output among then intercepting this L mistake output.And the data of preceding l cycle output
Should be correct, this partial data can be provided by the normal output data of FIR filter 2.
In order to travel through different shift registers under the conditions of different input datas break down caused by mistake output, can be by
Input data just changes an input data every L length., can be by first data (rope of input traffic for the ease of description
Be cited as the starting point 0) as direct fault location, that is, the Data Position changed be 0, L, 2L ... nL ....So, to carry out N
Secondary direct fault location, then total input data length is NL.
3rd, the output of two-way FIR filter is subjected to cross-combining
From the analysis in second step, FIR filter 1 and FIR filter 2 have identical input traffic first,
Wherein the input data of FIR filter 1 is periodically changed (direct fault location), and modification is at intervals of L data, and FIR is filtered
The input data of device 2 keeps constant.So, the output data of FIR filter 1 is wrong, and the output of FIR filter 2 entirely
Data are really correct.For the FIR filter that tap is L, if input data length is NL, output data length is also
NL.Filtering output data caused by FIR filter 1, FIR filter 2 and final direct fault location can be all divided into N sections, often
Segment length is L, and the output data of such two-way filter and desired direct fault location simulation output are represented byAnd On(l), wherein n=0,1,2 ..., N-1 represent the position of data segment, and l=0,1,2 ..., L-1 represents every
The position of data in section.For the n-th segment data, if l-th of shift register breaks down, On(l) in this paragraph
L data can obtain by the following method：
4) the preceding l data in the n-th segment data of FIR filter 2 are taken out；
5) the front and rear L-l data in the n-th segment data of FIR filter 1 are taken out；
6) it two end datas will splice above, and form L data, be expressed as
As seen from the above description, the position of the targeted fault register of each direct fault location can be different.At this
During individual, the modification operation of input data is identical, and the position of fault register is simply embodied in interception and anabolic process
Put.
Fig. 1 is the structure of typical Direct-type FIR Filter, and wherein D is shift register, h0~hL-1For wave filter system
Number.It can be seen that after l-th of shift register failure, its wrong data stored will also retain L-l in wave filter
The individual sampling period, therefore cause the filtering output of L-l mistake.What the present invention was simulated is exactly that event occurs for this shift register
Hinder the influence caused to output data.
Fig. 2 illustrates FIR filter fault filling method structure and flow based on input and output data operation.Total
For, whole fault injection system includes three parts, is that two branch road FIR filter parallel processing modules, input data are repaiied respectively
Change module and output data selection and concatenation module.The effect of three modules is described as follows：
1) two branch road FIR filter parallel processing module
Original FIR filter device is realized that logic copy is two, and makes the two FIR filter synchronization process two defeated
Enter data flow.The output data of two FIR filters together sends into data selection and concatenation module, the final failure for being formed
Inject result.
2) input data modified module
Original input data is passed directly into FIR filter 2, and the input of FIR filter 1 is then changed by original input data
Form.Alteration ruler is that, per the L number of data modification one, modification mode can be carried out according to single-particle inversion SEU effects, will
Some bit of this number binary representation, which is overturn, (to be become 1 by 0, or becomes the bit position that 0), overturns every time by 1
Can be different.
3) output data selection and concatenation module
The position of the shift register of injection failure, selects the difference in two FIR filter output datas as needed
Part, and both are spliced, ultimately form the error filtering output result caused by current failure injection.
Here illustrated how with an example based on the input and output operating method proposed come analog fir filter event
Hinder mistake output caused by register.
1. fault scenes are described
If need simulation is a 9 rank FIR filters (L=9), altogether comprising 9 shift register (D0~D8) and 9
Filter factor (h0~h8).As shown in figure 3, filter coefficient is set in advance as
[- 6 ,-13 50 262 400 262 50-13-6],
Preceding 9 data of input traffic are
X=[208 231 32 233 161 24 71 140 40 36]
These data sequentially enter the shift register of FIR filter, and when first data enters D5, single-particle is turned over
Turning effect is overturn its lowest bit.Because the D5 current datas stored are 208,11010000 are represented in binary as,
Therefore the result of lowest bit upset is 11010001, that is, becomes 209 (as shown in Figure 3).Before this, 5 filtering output
All it is correct, is respectively
[-1248 -4090 7205 64232 141327]
And the output of the 6th sampling instant should be 164693, but now become for 164955.Hereafter, error number
According to still being stopped in FIR filter three sampling periods, and generate three 152130,152036 and of mistake output
130567, respectively as shown in Figure 4, Figure 5 and Figure 6.Finally, since D5Generation single-particle inversion failure, caused preceding 9 filtering is defeated
Go out for
Y=[- 1248-4,090 7,205 64,232 141,327 164,955 152,130 152,036 130567]
2. the direct fault location simulation operated based on inputoutput data
Scheme proposed by the present invention is only operated to input and output data, so as to reach and preset failure scene above
Same effect (i.e. in the 5th sampling period D50th bit of register is overturn), export same filter result.
The first step, constructs two identical FIR filters (FIR filter 1 and FIR filter 2), coefficient is ibid；
Second step, the 0th bit of former first data of input data is overturn, amended input data is obtained
X '=[209 231 32 233 161 24 71 140 40 36]
Then input data x feeding FIR filters 2 are handled, obtaining preceding 9 output results is：
Y2=[- 1248-4,090 7,205 64,232 141,327 164,693 152,080 152,049 130573]
Amended input data x ' feeding FIR filters 1 are handled, obtaining preceding 9 output results is：
Y1=[- 1254-4,103 7,255 64,494 141,727 164,955 152,130 152,036 130567]
3rd step, as requested, need to simulate D5The failure effect of shift register, therefore preceding the 5 of selection FIR filter 2
Individual filter result
y2[0:4]=[- 1248-4,090 7,205 64,232 141327]
With rear 4 filter results of FIR filter 1
y1[5:8]=[164,955 152,130 152,036 130567]
Then both are spliced and obtains final analog result
Y=[- 1248-4,090 7,205 64,232 141,327 164,955 152,130 152,036 130567]
This result and result in " fault scenes description " are completely the same, so as to demonstrate failure simulation method
Correctness.
Operation completes primary fault injection above, and more failed operations periodically should modify to input data
(the 10th, the 19th, the 28th ...).
In fact, based on above description it can be found that situation about being broken down for different shift registers, input data
Modification operation be identical, simply the position of the data segment selected in output data operation is different.Therefore, based on once
After input data modification, the result obtained by two-way FIR filter is used directly for a variety of different shift registers and occurs event
The simulation of barrier, it is no longer necessary to re-start FIR filtering process.
Claims (1)
1. a kind of FIR filter fault filling method operated based on input and output data, if the tap of FIR filter is L,
Fault filling method is：
(1) original FIR processing logic is replicated, forms the FIR filter parallel processing structure of two branch roads, claim respectively
For the first FIR filter and the second FIR filter, and produced input traffic is lengthened as far as possible；
(2) input data is just changed into an input data every L length, direct fault location, and the 2nd FIR is carried out to the first wave filter
The input data of wave filter keeps constant；If input data length is NL, output data length is also NL, and the first FIR is filtered
Filtering output data caused by device, the second FIR filter and final direct fault location is all divided into N sections, is L, two-way per segment length
The output data of wave filter and desired direct fault location simulation output are expressed asAnd On(l), wherein n=
0,1,2 ..., N-1 represent the position of data segment, and l=0,1,2 ..., L-1 represents the position of the data in every section, for n-th section
For data, if l-th of shift register breaks down, On(l) L data in this paragraph can be obtained by the following method：
1) the preceding l data in the n-th segment data of the second FIR filter are taken out；
2) the front and rear L-l data in the n-th segment data of the first FIR filter are taken out；
3) it two end datas will splice above, and form L data, be expressed as
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| 郭勇 等: "基于IP核FIR滤波器的设计与FPGA实现", 《专题技术与工程应用》 * |
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