CN107193680A - A kind of heartbeat detecting method, equipment and system - Google Patents
A kind of heartbeat detecting method, equipment and system Download PDFInfo
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- CN107193680A CN107193680A CN201710353015.XA CN201710353015A CN107193680A CN 107193680 A CN107193680 A CN 107193680A CN 201710353015 A CN201710353015 A CN 201710353015A CN 107193680 A CN107193680 A CN 107193680A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
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Abstract
The present invention provides a kind of heartbeat detecting method, equipment and system, and the above method comprises the following steps：At least one validation value is write to the register of on-site programmable gate array FPGA；By the validation value for comparing the validation value read from the register with writing the register, comparative result is obtained；According to the comparative result, respective handling is carried out to the FPGA；FPGA working condition can be monitored in real time by realizing.
Description
Technical field
The invention belongs to detection field, more particularly to a kind of heartbeat detecting method, equipment and system.
Background technology
FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, it be PAL,
The product further developed on the basis of the programming devices such as GAL, CPLD.It is as in application specific integrated circuit (ASIC) field
A kind of semi-custom circuit and occur, both solved the deficiency of custom circuit, original programming device gate circuit overcome again
The limited shortcomings of number, nowadays FPGA and play in server core part important angle in server field using extensive
Color, decide with the connectedness of substrate manager BMC communication links etc..
But, if FPGA working conditions can not be checked effectively in real time, larger hidden danger can be brought to server work,
Server is such as caused to be delayed machine or operation irregularity.
Therefore, FPGA working condition is monitored in the urgent need to a kind of simple and effective way
The content of the invention
The present invention provides a kind of heartbeat detecting method, equipment and system, to solve the above problems.
The embodiment of the present invention provides a kind of heartbeat detecting method.The above method comprises the following steps：
At least one validation value is write to the register of on-site programmable gate array FPGA；
By the validation value for comparing the validation value read from the register with writing the register, knot is compared in acquisition
Really；
According to the comparative result, respective handling is carried out to the FPGA.
The embodiment of the present invention also provides a kind of heartbeat detection apparatus, including writing module, comparison module, processing module；Its
In, said write module is connected by the comparison module with the processing module；
Said write module, for writing at least one validation value to the register of on-site programmable gate array FPGA；
The comparison module, for by comparing the validation value read from the register with writing the register
Validation value, obtains comparative result；
The processing module, according to the comparative result, respective handling is carried out to the FPGA.
The present invention also provides a kind of palmus detection system, including above-mentioned heartbeat detection apparatus.
Pass through following scheme：At least one validation value is write to the register of on-site programmable gate array FPGA；By than
Compared with the validation value read from the register and the validation value for writing the register, comparative result is obtained；According to the ratio
Relatively result, respective handling is carried out to the FPGA；FPGA working condition can be monitored in real time by realizing.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this hair
Bright schematic description and description is used to explain the present invention, does not constitute inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 show the flow chart of according to embodiments of the present invention 1 heartbeat detecting method provided；
Fig. 2 show the according to embodiments of the present invention 2 heartbeat detection apparatus schematic diagrames provided；
Fig. 3 show the according to embodiments of the present invention 3 palmus detection system schematic diagrames provided.
Embodiment
Describe the present invention in detail below with reference to accompanying drawing and in conjunction with the embodiments.It should be noted that not conflicting
In the case of, the feature in embodiment and embodiment in the application can be mutually combined.
Fig. 1 show the flow chart of according to embodiments of the present invention 1 heartbeat detecting method provided, comprises the following steps：
Step 101：At least one validation value is write to the register of on-site programmable gate array FPGA；
Further, substrate manager be BMC by regular alternate mode to register write fixed value 0xAA with
0x55。
For example：10 points of registers to FPGA of substrate manager write fixed value 0xAA；10: 30 to FPGA register
Write fixed value 0x55；11 points of registers to FPGA write fixed value 0xAA；11 points of 30 minutes registers to FPGA write solid
Definite value 0x55.
Regular fixed value 0xAA and 0x55 so is write to FPGA register in an alternating fashion every half an hour,
To compare before and after reading and writing.
Step 102：By the validation value for comparing the validation value read from the register with writing the register, obtain
Take comparative result；
Step 103：According to the comparative result, respective handling is carried out to the FPGA.
Further, substrate manager compares the validation value read from the register with writing testing for the register
Card value；
If inconsistent, the inconsistent number of times obtained in statistics preset period of time；
If the inconsistent number of times is more than preset value, judge that the FPGA is in anomalous operating mode, restart described
FPGA。
Further, the preset period of time can flexibly be set as needed, for example：1 hour；The preset value can
Flexibly to be set as needed, for example：6 times.
Substrate manager BMC is provided avoids certain one-time detection from causing to restart DPGA i.e. FPGA extremely by increasing fault tolerant mechanism
Reset, further lifting detection accuracy.
Substrate manager is compared by the value of the read-write in the register by FPGA, if inconsequent, by many
Secondary to confirm, if still inconsistent, then it is assumed that FPGA comes into anomalous operating mode, BMC is responsible for restarting DPGA i.e. FPGA
Reset, to recover its normal work.
Further, substrate manager compares the validation value read from the register with writing testing for the register
Card value；
If inconsistent, judge that the FPGA is in anomalous operating mode, restart the FPGA.
If the characteristics of such scheme is that judgement is inconsistent, judge that the FPGA is in anomalous operating mode, restart described
FPGA, improves response speed, is easy to solve a problem promptly, safeguards system safety.
Further, the substrate manager is that GPIO directly restarts the FPGA by universal input/output interface.
Further, substrate manager compares the validation value read from the register with writing testing for the register
Card value；
If consistent, judge that the FPGA is in normal mode of operation, continue to read and write the register.
Fig. 2 show the according to embodiments of the present invention 2 heartbeat detection apparatus schematic diagrames provided, including writing module 201, ratio
Compared with module 202, processing module 203；Wherein, said write module 201 passes through the comparison module 202 and the processing module
203 connections；
Said write module 201, for writing at least one validation value to the register of on-site programmable gate array FPGA；
The comparison module 202, for by comparing the validation value read from the register with writing the deposit
The validation value of device, obtains comparative result；
The processing module 203, according to the comparative result, respective handling is carried out to the FPGA.
Further,
Said write module, be additionally operable to by regular alternate mode to the register write fixed value 0xAA with
0x55。
Further,
The comparison module, is additionally operable to compare the validation value read from the register with writing testing for the register
Card value, obtains inconsistent comparative result；
The processing module, is additionally operable to count the inconsistent number of times obtained in preset period of time；If being additionally operable to described inconsistent
Number of times is more than preset value, then judges that the FPGA is in anomalous operating mode, restart the FPGA.
Fig. 3 show the according to embodiments of the present invention 3 palmus detection system schematic diagrames provided, including above-mentioned heartbeat detection is set
It is standby.
Pass through following scheme：At least one validation value is write to the register of on-site programmable gate array FPGA；By than
Compared with the validation value read from the register and the validation value for writing the register, comparative result is obtained；According to the ratio
Relatively result, respective handling is carried out to the FPGA；FPGA working condition can be monitored in real time by realizing.
Pass through following scheme：Substrate manager compares the validation value read from the register with writing the register
Validation value；If inconsistent, the inconsistent number of times obtained in statistics preset period of time；If the inconsistent number of times is more than default
Value, then judge that the FPGA is in anomalous operating mode, restart the FPGA；The program is corresponding for abnormal operation increase
Fault tolerant mechanism and force FPGA reset to recover normal work, then can also improve server to a certain extent and work in itself
Stability and fault freedom.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (10)
1. a kind of heartbeat detecting method, it is characterised in that comprise the following steps：
At least one validation value is write to the register of on-site programmable gate array FPGA；
By the validation value for comparing the validation value read from the register with writing the register, comparative result is obtained；
According to the comparative result, respective handling is carried out to the FPGA.
2. heartbeat detecting method according to claim 1, it is characterised in that substrate manager is BMC by periodically replacing
Mode write fixed value 0xAA and 0x55 to the register.
3. heartbeat detecting method according to claim 1, it is characterised in that substrate manager compares from the register
The validation value of reading and the validation value for writing the register；
If inconsistent, the inconsistent number of times obtained in statistics preset period of time；
If the inconsistent number of times is more than preset value, judges that the FPGA is in anomalous operating mode, restart the FPGA.
4. heartbeat detecting method according to claim 1, it is characterised in that substrate manager compares from the register
The validation value of reading and the validation value for writing the register；
If inconsistent, judge that the FPGA is in anomalous operating mode, restart the FPGA.
5. the heartbeat detecting method according to claim 3 or 4, it is characterised in that the substrate manager passes through general defeated
Enter output interface i.e. GPIO and directly restart the FPGA.
6. heartbeat detecting method according to claim 1 or 2, it is characterised in that substrate manager compares from the deposit
The validation value read in device and the validation value for writing the register；
If consistent, judge that the FPGA is in normal mode of operation, continue to read and write the register.
7. a kind of heartbeat detection apparatus, it is characterised in that including writing module, comparison module, processing module；Wherein, it is described to write
Enter module to be connected with the processing module by the comparison module；
Said write module, for writing at least one validation value to the register of on-site programmable gate array FPGA；
The comparison module, for the checking by comparing the validation value read from the register with writing the register
Value, obtains comparative result；
The processing module, according to the comparative result, respective handling is carried out to the FPGA.
8. heartbeat detection apparatus according to claim 7, it is characterised in that said write module, is additionally operable to by regular
Alternate mode writes fixed value 0xAA and 0x55 to the register.
9. heartbeat detection apparatus according to claim 7, it is characterised in that the comparison module, is additionally operable to compare from institute
Validation value of the validation value read in register with writing the register is stated, inconsistent comparative result is obtained；
The processing module, is additionally operable to count the inconsistent number of times obtained in preset period of time；If being additionally operable to the inconsistent number of times
More than preset value, then judge that the FPGA is in anomalous operating mode, restart the FPGA.
10. a kind of palmus detection system, it is characterised in that set including the heartbeat detection as described in any one of claim 7 to 9
It is standby.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710353015.XA CN107193680A (en) | 2017-05-18 | 2017-05-18 | A kind of heartbeat detecting method, equipment and system |
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| CN201710353015.XA CN107193680A (en) | 2017-05-18 | 2017-05-18 | A kind of heartbeat detecting method, equipment and system |
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| CN107193680A true CN107193680A (en) | 2017-09-22 |
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| CN201710353015.XA Pending CN107193680A (en) | 2017-05-18 | 2017-05-18 | A kind of heartbeat detecting method, equipment and system |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109597731A (en) * | 2018-12-10 | 2019-04-09 | 浪潮(北京)电子信息产业有限公司 | A kind of state test method of processor |
| CN109614280A (en) * | 2018-12-10 | 2019-04-12 | 浪潮(北京)电子信息产业有限公司 | A kind of state test method storing equipment |
| CN110515437A (en) * | 2019-08-16 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of high-temperature protection method and device of FPGA accelerator card |
| CN111048139A (en) * | 2019-12-22 | 2020-04-21 | 苏州浪潮智能科技有限公司 | Storage medium detection method, device, equipment and readable storage medium |
| WO2020087227A1 (en) * | 2018-10-29 | 2020-05-07 | 深圳配天智能技术研究院有限公司 | Robot control system, heartbeat monitoring method and module, and storage medium |
| CN112685265A (en) * | 2021-03-17 | 2021-04-20 | 中国人民解放军国防科技大学 | Navigation receiver host and standby machine switching and testing method based on bidirectional communication serial port |
| CN114562475A (en) * | 2022-02-25 | 2022-05-31 | 苏州浪潮智能科技有限公司 | Control method and device of fan controller and substrate manager |
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| CN106528311A (en) * | 2016-09-29 | 2017-03-22 | 杭州芯讯科技有限公司 | Embedded system and control method thereof |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020087227A1 (en) * | 2018-10-29 | 2020-05-07 | 深圳配天智能技术研究院有限公司 | Robot control system, heartbeat monitoring method and module, and storage medium |
| CN109597731A (en) * | 2018-12-10 | 2019-04-09 | 浪潮(北京)电子信息产业有限公司 | A kind of state test method of processor |
| CN109614280A (en) * | 2018-12-10 | 2019-04-12 | 浪潮(北京)电子信息产业有限公司 | A kind of state test method storing equipment |
| CN110515437A (en) * | 2019-08-16 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of high-temperature protection method and device of FPGA accelerator card |
| CN110515437B (en) * | 2019-08-16 | 2022-02-18 | 苏州浪潮智能科技有限公司 | High-temperature protection method and device for FPGA accelerator card |
| CN111048139A (en) * | 2019-12-22 | 2020-04-21 | 苏州浪潮智能科技有限公司 | Storage medium detection method, device, equipment and readable storage medium |
| CN112685265A (en) * | 2021-03-17 | 2021-04-20 | 中国人民解放军国防科技大学 | Navigation receiver host and standby machine switching and testing method based on bidirectional communication serial port |
| CN112685265B (en) * | 2021-03-17 | 2021-06-18 | 中国人民解放军国防科技大学 | Navigation receiver host and standby machine switching and testing method based on bidirectional communication serial port |
| CN114562475A (en) * | 2022-02-25 | 2022-05-31 | 苏州浪潮智能科技有限公司 | Control method and device of fan controller and substrate manager |
| CN114562475B (en) * | 2022-02-25 | 2023-09-12 | 苏州浪潮智能科技有限公司 | Control method and device of fan controller and substrate manager |
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Application publication date: 20170922 |
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