CN107180598A - A kind of array base palte and display panel - Google Patents
A kind of array base palte and display panel Download PDFInfo
- Publication number
- CN107180598A CN107180598A CN201710601756.5A CN201710601756A CN107180598A CN 107180598 A CN107180598 A CN 107180598A CN 201710601756 A CN201710601756 A CN 201710601756A CN 107180598 A CN107180598 A CN 107180598A
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- layer
- array base
- base palte
- flatness
- electrode layer
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133357—Planarisation layers
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Theoretical Computer Science (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- Human Computer Interaction (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a kind of array base palte and display panel, the array base palte includes flatness layer and the common electrode layer stacked gradually, and common electrode layer includes multiple spaced public electrode blocks, and flatness layer is provided with the via through flatness layer；Wherein, projection of the public electrode block on the flatness layer is arranged at intervals with the via.Pass through above-mentioned array base palte, the present invention is enabled to when preparing the common electrode layer of multiple spaced public electrode blocks, adjacent public electrode block will not cause electrical connection because of the electrode material being attached in preparation process in via, it is to avoid the display that adjacent public electrode block occurs the phenomenon of short circuit and caused is abnormal.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and display panel.
Background technology
With the development of Display Technique, contact panel is widely used in personal computer, smart phone, public information, intelligence
The various fields such as energy household electrical appliances, Industry Control, in order to realize the touch-control performance of contact panel, on the flatness layer of contact panel
Common electrode layer generally comprises multiple spaced public electrode blocks to sense touching signals, in the preparation of the common electrode layer
During, ito thin film layer is first deposited on flatness layer, spaced multiple public electrodes are then formed by photoetching process
Block, but in film forming procedure, ITO can be attached in the via of flatness layer and be difficult to clean off so that positioned at via both sides and phase
Adjacent public electrode block can be linked together by the ITO adhered in via, and then cause contact panel when in use, and this is adjacent
There is short circuit phenomenon in public electrode block, so as to cause display abnormal.
The content of the invention
The present invention is mainly to provide a kind of array base palte and display panel, it is intended to solves public electrode block and is led because of via
The problem of causing short circuit.
In order to solve the above technical problems, one aspect of the present invention is：A kind of array base palte, the battle array are provided
Row substrate includes flatness layer and the common electrode layer stacked gradually, and the common electrode layer includes multiple spaced common electricals
Pole block, the flatness layer is provided with the via through the flatness layer；Wherein, throwing of the public electrode block on the flatness layer
Shadow is arranged at intervals with the via.
In order to solve the above technical problems, another technical solution used in the present invention is：A kind of display panel is provided, it is described
Display panel includes spaced first substrate and second substrate, and the second substrate includes flatness layer and the public affairs stacked gradually
Common electrode layer, the common electrode layer includes multiple spaced public electrode blocks, and the flatness layer is provided with through described flat
The via of smooth layer；Wherein, projection of the public electrode block on the flatness layer is arranged at intervals with the via.
The beneficial effects of the invention are as follows：It is different from the situation of prior art, the common electrical that the present invention passes through common electrode layer
The via of projection and flatness layer of the pole block on flatness layer is arranged at intervals so that preparing multiple spaced public electrode blocks
Common electrode layer when, will not be because of being attached in preparation process in via positioned at via both sides and adjacent public electrode block
Electrode material and cause electrical connection, it is to avoid the display that adjacent public electrode block occurs short circuit phenomenon and caused is abnormal.
Brief description of the drawings
Fig. 1 is the schematic cross-section for the array base palte first embodiment that the present invention is provided；
Fig. 2 is common electrode layer and the schematic top plan view of flatness layer in Fig. 1；
Fig. 3 is the schematic top plan view for the array base palte second embodiment that the present invention is provided；
Fig. 4 is the structural representation for the display panel first embodiment that the present invention is provided；
Fig. 5 is the structural representation for the display panel second embodiment that the present invention is provided.
Embodiment
To make those skilled in the art more fully understand technical scheme, below in conjunction with the accompanying drawings and specific implementation
Mode is described in further detail to a kind of array base palte and display panel provided by the present invention.
Refering to Fig. 1, the array base palte first embodiment that the present invention is provided includes flatness layer 11 and the public affairs being cascading
Common electrode layer 12.
Wherein, flatness layer 11 is provided with the via 111 through flatness layer 11.
Common electrode layer 12 includes multiple spaced public electrode blocks 121, optionally, in the present embodiment, public
The quantity of electrode block 121 is 18 × 30.
Wherein, projection of the public electrode block 121 on flatness layer 11 is arranged at intervals with via 111.
As shown in figure 1, two adjacent public electrode blocks 121 are located at the left and right sides of via 111 respectively, the left and right sides
Public electrode block 121 is set with the corresponding marginating compartment of via 111 respectively close to the side of via 111, optionally, in other realities
Apply in example, two adjacent public electrode blocks 121 can also be one of them close to the side of via 111 and the side of via 111
Edge is arranged at intervals, and another coincides close to the side of via 111 and the edge of via 111.
During actually preparing, one layer of electrode material layer, now, the mistake of flatness layer 11 can be deposited on flatness layer 11
Electrode material can be attached with deposition process in hole 111, be then divided into the electrode material layer by photoetching process multiple
Electrode material block, and in the etching process of the photoetching process so that projection of the electrode material block of formation on flatness layer 11
It is arranged at intervals with via 111, even and if then causing the array base palte being attached with via 111 in electrode material, the present embodiment to exist
In the process of actual use, the two electrode material blocks adjacent with via 111 also will not be because of the electrode material adhered in via 111
Expect and cause electrical connection, it is to avoid the phenomenon of short circuit occur in the two electrode material blocks adjacent with via 111, namely ensure that
Two adjacent with the via 111 public electrode block 121 stated is not in the phenomenon of short circuit.
Optionally, the electrode material is ITO.
Refering to Fig. 2, the array base palte in the present embodiment includes viewing area 101 and non-display area 102, and via 111 includes the
One via 1111, the first via 1111 is arranged at the flatness layer 11 positioned at viewing area 101.
It should be understood that the via 111 in the present embodiment is only arranged at the flatness layer 11 positioned at viewing area 101, and it is located at
The flatness layer 11 of non-display area 102 is without via 111.
Fig. 1 is further regarded to, the array base palte of the present embodiment also includes the pixel for being located at flatness layer both sides about 11 respectively
Electrode layer 13 and semiconductor layer 14.
Further, pixel electrode layer 13 is stacked with common electrode layer 12, and pixel electrode layer 13 and public electrode
Insulating barrier 15 is additionally provided between layer.
Wherein, pixel electrode layer 13 extends to semiconductor layer 14 to electrically connect with semiconductor layer 14 by via 111.
Actually prepare during, can deposition of electrode material on insulating barrier 15 and in via 111, with insulating barrier
Electrode material layer is formed on 15 as pixel electrode layer 15, the pixel electrode layer 15 passes through the electrode material in via 111 and half
Conductor layer 14 is electrically connected.
Optionally, the electrode material is ITO.
Via 211 in the array base palte second embodiment provided refering to Fig. 3, the present invention also includes the second via 2112.
Wherein, the second via 2112 is arranged at the flatness layer 21 of the non-display area 202 of array base palte.
It should be understood that the via 211 in the present embodiment includes the first via 2111 and the second via 2112, the first via
2111 is identical with above-mentioned first embodiment, is arranged at the flatness layer 21 of the viewing area 201 of array base palte, and the second via 2112 is set
In the flatness layer 21 of the non-display area 202 of array base palte.
Other structures and principle in the present embodiment are identical with above-mentioned first embodiment, will not be repeated here.
Fig. 1, Fig. 2 and Fig. 4 are referred to jointly, and the display panel first embodiment that the present invention is provided includes spaced first
Substrate 30 and second substrate 31, wherein, the second substrate in the present embodiment and the array in above-mentioned array base palte first embodiment
Substrate is identical.
Specifically, second substrate 31 includes flatness layer 11 and the common electrode layer 12 being cascading.
Wherein, flatness layer 11 is provided with the via 111 through flatness layer 11.
Common electrode layer 12 includes multiple spaced public electrode blocks 121, optionally, in the present embodiment, public
The quantity of electrode block 121 is 18 × 30.
Wherein, projection of the public electrode block 121 on flatness layer 11 is arranged at intervals with via 111.
As shown in figure 1, two adjacent public electrode blocks 121 are located at the left and right sides of via 111 respectively, the left and right sides
Public electrode block 121 is set with the corresponding marginating compartment of via 111 respectively close to the side of via 111, optionally, in other realities
Apply in example, two adjacent public electrode blocks 121 can also be one of them close to the side of via 111 and the side of via 111
Edge is arranged at intervals, and another coincides close to the side of via 111 and the edge of via 111.
During actually preparing, one layer of electrode material layer, now, the mistake of flatness layer 11 can be deposited on flatness layer 11
Electrode material can be attached with deposition process in hole 111, be then divided into the electrode material layer by photoetching process multiple
Electrode material block, and in the etching process of the photoetching process so that projection of the electrode material block of formation on flatness layer 11
It is arranged at intervals with via 111, even and if then causing the array base palte being attached with via 111 in electrode material, the present embodiment to exist
In the process of actual use, the two electrode material blocks adjacent with via 111 also will not be because of the electrode material adhered in via 111
Expect and cause electrical connection, it is to avoid the phenomenon of short circuit occur in the two electrode material blocks adjacent with via 111, namely ensure that
Two adjacent with the via 111 public electrode block 121 stated is not in the phenomenon of short circuit.
Optionally, the electrode material is ITO.
The array base palte further regarded in Fig. 2, the present embodiment includes viewing area 101 and non-display area 102, via 111
Including the first via 1111, the first via 1111 is arranged at the flatness layer 11 of viewing area 101.
It should be understood that the via 111 in the present embodiment is only arranged at the flatness layer 11 positioned at viewing area 101, and it is located at
The flatness layer 11 of non-display area 102 is without via 111.
Fig. 1 is further regarded to, the array base palte of the present embodiment also includes the pixel for being located at flatness layer both sides about 11 respectively
Electrode layer 13 and semiconductor layer 14.
Further, pixel electrode layer 13 is stacked with common electrode layer 12, and pixel electrode layer 13 and public electrode
Insulating barrier 15 is additionally provided between layer.
Wherein, pixel electrode layer 13 extends to semiconductor layer 14 to electrically connect with semiconductor layer 14 by via 111.
Actually prepare during, can deposition of electrode material on insulating barrier 15 and in via 111, with insulating barrier
Electrode material layer is formed on 15 as pixel electrode layer 15, the pixel electrode layer 15 passes through the electrode material in via 111 and half
Conductor layer 14 is electrically connected.
Optionally, the electrode material is ITO.
Common to participate in Fig. 3 and Fig. 5, the display panel second embodiment that the present invention is provided includes the base of first substrate 40 and second
Plate 41, wherein, second substrate 41 is identical with the array base palte in above-mentioned array base palte second embodiment.
Specifically, the via 211 in flatness layer 21 also includes the second via 2112.
Wherein, the second via 2112 is arranged at the flatness layer 21 of the non-display area 202 of array base palte.
It should be understood that the via 211 in the present embodiment includes the first via 2111 and the second via 2112, the first via
2111 is identical with above-mentioned first embodiment, is arranged at the flatness layer 21 of the viewing area 201 of array base palte, and the second via 2112 is set
In the flatness layer 21 of the non-display area 202 of array base palte.
Other structures and principle in the present embodiment are identical with above-mentioned display panel first embodiment, will not be repeated here.
Be different from prior art, the present invention by projection of the public electrode block of common electrode layer on flatness layer with it is flat
The via of layer is arranged at intervals so that when preparing the common electrode layer of multiple spaced public electrode blocks, adjacent is public
Electrode block will not cause electrical connection because of the electrode material being attached in preparation process in via, it is to avoid adjacent common electrical
The display that pole block occurs the phenomenon of short circuit and caused is abnormal.
Embodiments of the invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this hair
Equivalent structure or equivalent flow conversion that bright specification and accompanying drawing content are made, or directly or indirectly it is used in other related skills
Art field, is included within the scope of the present invention.
Claims (10)
1. a kind of array base palte, it is characterised in that the array base palte includes flatness layer and the common electrode layer stacked gradually, institute
Stating common electrode layer includes multiple spaced public electrode blocks, and the flatness layer is provided with the via through the flatness layer；
Wherein, projection of the public electrode block on the flatness layer is arranged at intervals with the via.
2. array base palte according to claim 1, it is characterised in that the array base palte includes viewing area and non-display
Area, the via includes the first via, and first via is located at the flatness layer of the viewing area.
3. array base palte according to claim 2, it is characterised in that the via also includes the second via, described second
Via is located at the flatness layer of the non-display area.
4. array base palte according to claim 1, it is characterised in that the array base palte also includes being located at described put down respectively
The pixel electrode layer and semiconductor layer of both sides above and below smooth layer, the pixel electrode layer extend to the semiconductor by the via
Layer with the semiconductor layer to electrically connect.
5. array base palte according to claim 4, it is characterised in that the pixel electrode layer and the public electrode are layer by layer
It is folded to set, and it is additionally provided with insulating barrier between the pixel electrode layer and the common electrode layer.
6. a kind of display panel, it is characterised in that the display panel includes spaced first substrate and second substrate, institute
Flatness layer and common electrode layer that second substrate includes stacking gradually are stated, the common electrode layer includes multiple spaced public affairs
Common electrode block, the flatness layer is provided with the via through the flatness layer；
Wherein, projection of the public electrode block on the flatness layer is arranged at intervals with the via.
7. array base palte according to claim 6, it is characterised in that the array base palte includes viewing area and non-display
Area, the via includes the first via, and first via is located at the flatness layer of the viewing area.
8. array base palte according to claim 7, it is characterised in that the via also includes the second via, described second
Via is located at the flatness layer of the non-display area.
9. array base palte according to claim 6, it is characterised in that the array base palte also includes being located at described put down respectively
The pixel electrode layer and semiconductor layer of both sides above and below smooth layer, the pixel electrode layer extend to the semiconductor by the via
Layer with the semiconductor layer to electrically connect.
10. array base palte according to claim 9, it is characterised in that the pixel electrode layer and the common electrode layer
It is stacked, and insulating barrier is additionally provided between the pixel electrode layer and the common electrode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710601756.5A CN107180598A (en) | 2017-07-21 | 2017-07-21 | A kind of array base palte and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710601756.5A CN107180598A (en) | 2017-07-21 | 2017-07-21 | A kind of array base palte and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107180598A true CN107180598A (en) | 2017-09-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710601756.5A Pending CN107180598A (en) | 2017-07-21 | 2017-07-21 | A kind of array base palte and display panel |
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| CN (1) | CN107180598A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108279521A (en) * | 2018-03-30 | 2018-07-13 | 京东方科技集团股份有限公司 | Display base plate and display panel |
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| KR20170076185A (en) * | 2015-12-24 | 2017-07-04 | 엘지디스플레이 주식회사 | Array Substrate For Touch Display Device And Method Of Fabricating The Same |
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| US20140061606A1 (en) * | 2012-08-31 | 2014-03-06 | Hwa-Jeong Kim | Thin-film transistor array substrate and display device including the same |
| KR20170076185A (en) * | 2015-12-24 | 2017-07-04 | 엘지디스플레이 주식회사 | Array Substrate For Touch Display Device And Method Of Fabricating The Same |
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| CN108279521A (en) * | 2018-03-30 | 2018-07-13 | 京东方科技集团股份有限公司 | Display base plate and display panel |
| CN108279521B (en) * | 2018-03-30 | 2020-12-29 | 京东方科技集团股份有限公司 | Display substrate and display panel |
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Application publication date: 20170919 |