CN107170721B - Packaging structure and packaging method of fingerprint identification chip - Google Patents
Packaging structure and packaging method of fingerprint identification chip Download PDFInfo
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- CN107170721B CN107170721B CN201710522966.5A CN201710522966A CN107170721B CN 107170721 B CN107170721 B CN 107170721B CN 201710522966 A CN201710522966 A CN 201710522966A CN 107170721 B CN107170721 B CN 107170721B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
Abstract
The invention provides a packaging structure and a packaging method of a fingerprint identification chip, wherein the packaging structure comprises: a silicon substrate; a rewiring layer formed on the silicon substrate; a metal bump formed on the rewiring layer; the fingerprint identification chip is arranged on the rewiring layer through a metal welding spot, wherein the front surface of the fingerprint identification chip faces the rewiring layer; and the packaging material covers the fingerprint identification chip, and the metal lug is exposed out of the packaging material. Compared with the existing fingerprint identification chip package, the Fan-out type package (Fan out) fingerprint identification chip has the advantages of low cost, small thickness and high yield.
Description
Technical Field
The present invention relates to semiconductor packaging structures and packaging methods, and more particularly, to a semiconductor packaging structure and a semiconductor packaging method for a fingerprint identification chip.
Background
With the increasing functionality, performance and integration level of integrated circuits, and the emergence of new types of integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and accounts for an increasing proportion of the value of the entire electronic system. Meanwhile, as the feature size of the integrated circuit reaches the nanometer level, the transistor is developed to a higher density and a higher clock frequency, and the package is also developed to a higher density.
Because the fan-out wafer level package (fowlp) technology has the advantages of miniaturization, low cost, high integration, better performance, and higher energy efficiency, the fan-out wafer level package (fowlp) technology has become an important packaging method for high-demand electronic devices such as mobile/wireless networks, and is one of the most promising packaging technologies currently.
Fingerprint identification technology is the most mature and cheap biometric identification technology at present. At present, the technology of fingerprint identification is most widely applied, the figure of the fingerprint identification technology can be seen in an access control and attendance system, and more fingerprint identification applications are available in the market: such as notebook computer, mobile phone, automobile, bank payment can all apply the technology of fingerprint identification.
The prior art packaging method of fingerprint identification chip is shown in fig. 1a to 1 c:
first, as shown in fig. 1a, a deep groove is formed in a fingerprint identification chip 101, the deep groove is bonded to an FPC board 102, and then a metal wire 103 is formed through a wire bonding process to electrically connect the fingerprint identification chip 101 and the FP C board 102, wherein the FPC is a Flexible Printed Circuit (hereinafter referred to as a "Flexible Printed Circuit") for short, and has the characteristics of high wiring density, light weight, and thin thickness.
Second, as shown in fig. 1b, a frame 104 is manufactured;
and thirdly, as shown in fig. 1c, covering a sapphire cover plate 105 on the fingerprint identification chip to finish packaging.
This method has the following disadvantages: the packaging structure comprises a three-layer structure of the FPC board, the fingerprint identification chip and the sapphire cover plate, the packaging thickness is thick, the metal connecting wires are easy to break due to pulling of the FPC board and the like, and the overall yield is low.
Another method for packaging a fingerprint identification chip is shown in fig. 2a to 2 c:
first, as shown in fig. 2a, a through-hole electrode 106 is formed in the fingerprint recognition chip 101 by a through-silicon via TSV technique;
secondly, as shown in fig. 2b, the sapphire cover plate 105, the fingerprint identification chip 101 and the FPC board 102 are laminated together, and a metal connecting wire 103 is manufactured through a wire bonding process to connect the fingerprint identification chip 101 and the FPC board 102;
third, as shown in FIG. 2c, the frame 104 is fabricated.
This method has the following disadvantages: the fingerprint identification chip is packaged by a sapphire cover plate, the thickness is thick, the cost of a silicon perforation process is high, metal connecting wires are easy to break due to pulling of an FPC (flexible printed circuit) soft board and the like, the thickness of the fingerprint identification chip is thin, the cracking phenomenon is easy to occur, and the overall yield is low.
Based on the above, it is necessary to provide a fingerprint identification chip package structure and a fingerprint identification chip package method with low cost, low thickness and high package yield.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a package structure and a packaging method for a fingerprint identification chip, which are used to solve the problems of the prior art, such as a large thickness of the fingerprint identification package, a low yield, and the like.
To achieve the above and other related objects, the present invention provides a package structure of a fingerprint identification chip, including: a silicon substrate; a rewiring layer formed on the silicon substrate; a metal bump formed on the rewiring layer; the fingerprint identification chip is arranged on the rewiring layer through a metal welding spot, wherein the front surface of the fingerprint identification chip faces the rewiring layer; and the packaging material covers the fingerprint identification chip, and the metal lug is exposed out of the packaging material.
Preferably, a gap is formed between the fingerprint identification chip and the rewiring layer, and a protective layer is formed in the gap and completely covers the front surface of the fingerprint identification chip.
Furthermore, the protective layer is made of epoxy resin.
Preferably, the vertically corresponding region of the redistribution layer and the fingerprint identification chip includes a continuous dielectric layer and does not include a metal layer, so as to serve as an identification window of the fingerprint identification chip.
Preferably, the encapsulation material includes one of polyimide, silicone, and epoxy.
Preferably, the redistribution layer comprises a patterned dielectric layer and a patterned metal wiring layer.
Further, the dielectric layer is made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide and phosphorosilicate glass, and the fluorine-containing glass, and the metal wiring layer is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
Preferably, the metal bump comprises a copper pillar, a nickel layer located on the upper surface of the copper pillar, and a solder bump located on the nickel layer.
Further, the metal barrier layer comprises a nickel layer, and the material of the solder bump comprises one of lead, tin and silver or an alloy containing any one of the above solder metals.
Preferably, the thickness of the silicon substrate ranges from 1 μm to 700 μm.
The invention also provides a packaging method of the fingerprint identification chip, which comprises the following steps: 1) providing a silicon substrate, wherein the silicon substrate is provided with a first surface and a second surface which are opposite; 2) forming a rewiring layer on the first surface of the silicon substrate, and forming a metal bump on the rewiring layer; 3) providing a fingerprint identification chip, and installing the fingerprint identification chip on the rewiring layer through a metal welding spot, wherein the front surface of the fingerprint identification chip faces the rewiring layer; 4) packaging the fingerprint identification chip by adopting a packaging material, wherein the metal lug is exposed out of the packaging material; and 5) thinning the silicon substrate from the second surface of the silicon substrate.
Preferably, in step 3), after the fingerprint identification chip is mounted on the rewiring layer through the metal solder joint, a gap is formed between the fingerprint identification chip and the rewiring layer, and step 3) further includes a step of forming a protective layer in the gap, wherein the protective layer completely covers the front surface of the fingerprint identification chip.
Further, the protective layer is made of epoxy resin, and is formed in a gap between the fingerprint identification chip and the rewiring layer in a dispensing or die pressing mode.
Preferably, the vertically corresponding region of the redistribution layer and the fingerprint identification chip includes a continuous dielectric layer and does not include a metal layer, so as to serve as an identification window of the fingerprint identification chip.
Preferably, the step 2) of fabricating the rewiring layer includes the steps of: 2-1) forming a dielectric layer on the surface of the silicon substrate by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form a patterned dielectric layer; 2-2) forming a metal layer on the surface of the graphical dielectric layer by adopting a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and etching the metal layer to form a graphical metal wiring layer.
Further, the dielectric layer is made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide and phosphorosilicate glass, and the fluorine-containing glass, and the metal wiring layer is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
Preferably, the method for preparing the metal bump comprises the following steps: a) forming a copper column on the surface of the rewiring layer by adopting an electroplating method; b) forming a metal barrier layer on the surface of the copper pillar by adopting an electroplating method; c) and forming solder metal on the surface of the metal barrier layer by adopting an electroplating method, and forming solder bumps on the surface of the metal barrier layer by adopting a high-temperature reflow process.
Further, the metal barrier layer comprises a nickel layer, and the material of the solder bump comprises one of lead, tin and silver or an alloy containing any one of the above solder metals.
Preferably, the method for encapsulating the fingerprint identification chip with an encapsulation material includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating, and the encapsulation material includes one of polyimide, silicone and epoxy resin.
And 5), thinning the silicon substrate by adopting a mechanical grinding process, wherein the thickness range of the thinned silicon substrate is 0-700 mu m.
As described above, the packaging structure and the packaging method of the fingerprint identification chip of the present invention have the following beneficial effects:
1) the Fan-out type packaging (Fan out) fingerprint identification chip is adopted, and compared with the existing other fingerprint identification chip packaging, the Fan-out type fingerprint identification chip packaging structure has the advantages of low cost, small thickness and high yield;
2) the invention can realize the packaging of the fingerprint identification chip without a routing process and a high-cost Through Silicon Via (TSV) process, thereby greatly reducing the process difficulty and the cost;
3) the rewiring layer or the lamination of the rewiring layer and the silicon substrate sheet is directly adopted as the cover plate of the fingerprint identification chip, and a sapphire cover plate is not required to be additionally arranged, so that the thickness and the cost of packaging are greatly reduced;
4) the invention adopts Fan-out packaging (Fan out) process, the electric leading-out of the chip does not need the traditional FPC board, the packaging thickness and the stability of the electric leading-out structure can be reduced, and the packaging yield is improved;
5) the invention has simple process, creatively adopts fan-out packaging process to package the fingerprint identification chip, and has wide application prospect in the technical field of semiconductor packaging.
Drawings
Fig. 1a to fig. 1c are schematic structural diagrams showing steps of a packaging method for a fingerprint identification chip in the prior art.
Fig. 2a to 2c are schematic structural diagrams showing steps of another fingerprint identification chip packaging method in the prior art.
Fig. 3 to 10 are schematic structural diagrams of steps of the method for packaging a fingerprint identification chip according to the present invention, wherein fig. 10 is a schematic structural diagram of a packaging structure of a fingerprint identification chip according to the present invention.
FIG. 11 is a schematic diagram illustrating a principle of the package structure of the fingerprint identification chip according to the present invention.
Description of the element reference numerals
201 silicon substrate
202 identify windows
203 dielectric layer
204 metal wiring layer
205 metal bump
206 fingerprint identification chip
207 metal welding spot
208 protective layer
209 encapsulant
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to 11. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 3 to 10, the present embodiment provides a method for packaging a fingerprint identification chip 206, where the fingerprint identification chip 206 includes an optical fingerprint identification chip, a capacitive fingerprint identification chip, and an ultrasonic fingerprint identification chip, and the method includes the steps of:
as shown in fig. 3, step 1) is performed first, a silicon substrate 201 is provided, and the silicon substrate has a first surface and a second surface opposite to each other.
The silicon substrate 201 is used for manufacturing a rewiring layer on the first surface of the silicon substrate, so that the rewiring layer with high quality can be obtained, the silicon substrate 201 can be used as a protective cover plate of a fingerprint identification chip packaging structure after a subsequent thinning process, a sapphire cover plate does not need to be additionally arranged, the process is smooth, and meanwhile, the cost is saved.
As shown in fig. 4 to 6, step 2) is then performed to form a redistribution layer on the silicon substrate 201, and form a metal bump 205 on the redistribution layer.
As an example, the step 2) of fabricating the rewiring layer includes the steps of:
as shown in fig. 4, step 2-1) is performed, a dielectric layer 203 is formed on the surface of the silicon substrate 201 by using a chemical vapor deposition process or a physical vapor deposition process, and the dielectric layer 203 is etched to form a patterned dielectric layer 203.
By way of example, the material of the dielectric layer 203 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass. In this embodiment, the dielectric layer 203 is silicon oxide.
As shown in fig. 5, performing step 2-2), forming a metal layer on the surface of the patterned dielectric layer 203 by using a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process, or a chemical plating process, and etching the metal layer to form a patterned metal wiring layer 204.
As an example, the material of the metal wiring layer 204 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. In this embodiment, the material of the metal wiring layer 204 is selected to be copper.
It should be noted that the redistribution layer may include a plurality of dielectric layers 203 and a plurality of metal routing layers 204 stacked in sequence, and interconnection between the metal routing layers 204 is realized by patterning each dielectric layer 203 or making a through hole according to a connection requirement, so as to realize connection requirements of different functions.
By way of example, the metal bump 205 may be selected from a copper pillar, a nickel pillar, a solder metal (such as a solder ball), a combination of a copper pillar and a solder metal, a combination of a nickel pillar and a solder metal, a combination of a copper pillar, a metal barrier layer and a solder metal, and the like.
In this embodiment, the metal bump 205 is selected from a combination of a copper pillar, a metal barrier layer and a solder metal, and the method for manufacturing the metal bump 205 includes the steps of:
step a), forming a copper column on the surface of the rewiring layer by adopting an electroplating method;
step b), forming a metal barrier layer on the surface of the copper pillar by adopting an electroplating method;
and c), forming solder metal on the surface of the metal barrier layer by adopting an electroplating method, and forming solder bumps on the surface of the metal barrier layer by adopting a high-temperature reflow process.
As an example, the metal barrier layer includes a nickel layer, and the material of the solder bump includes one of lead, tin and silver or an alloy containing any one of the above solder metals.
The electroplating method can be used for preparing a high-quality copper pillar and improving the quality of the metal bump 205. The metal barrier layer may block diffusion of the solder metal, improving electrical performance of the metal bump 205.
As an example, the area of the redistribution layer corresponding to the vertical direction of the fingerprint identification chip 206 includes a continuous dielectric layer 203 and does not include a metal layer, so as to serve as the identification window 202 of the fingerprint identification chip 206. The recognition window 202 can obtain a good recognition effect for a capacitive fingerprint recognition chip and an ultrasonic fingerprint recognition chip, especially for an optical fingerprint recognition chip.
As shown in fig. 7 to 8, step 3) is performed to provide a fingerprint identification chip 206, and the fingerprint identification chip 206 is mounted on the redistribution layer through a metal pad 207, wherein a front surface of the fingerprint identification chip 206 faces the redistribution layer;
as an example, the metal pad 207 may be made of a metal material such as copper, gold, silver, aluminum, tin, and the like.
As an example, in step 3), after the fingerprint identification chip 206 is mounted on the redistribution layer through the metal pad 207, a gap is formed between the fingerprint identification chip 206 and the redistribution layer, and step 3) further includes a step of forming a protection layer 208 in the gap, where the protection layer 208 completely covers the front surface of the fingerprint identification chip 206.
As an example, the protection layer 208 is a transparent polymer layer, in this embodiment, the protection layer 208 is selected from epoxy resin, and is formed in a gap between the fingerprint identification chip 206 and the redistribution layer by using a dispensing or molding method. The protection layer 208 can effectively protect the fingerprint identification chip 206, for example, can prevent moisture from entering the fingerprint identification chip, and can serve as a buffer structure for impact, over-pressure, and the like.
Of course, the fingerprint identification chip 206 may be directly packaged with a packaging material without fabricating the protection layer 208.
As shown in fig. 9, step 4) is then performed to package the fingerprint identification chip 206 with an encapsulation material 209, and the metal bumps 205 are exposed from the encapsulation material 209.
As an example, the method for encapsulating the fingerprint recognition chip 206 with the encapsulating material 209 includes one of compression molding, transfer molding, liquid encapsulation, vacuum lamination, and spin coating, and the encapsulating material 209 includes one of polyimide, silicone, and epoxy. After packaging, the metal bumps 205 are exposed from the packaging material 209, so as to facilitate electrical connection with other devices or electrical extraction of the metal bumps.
As shown in fig. 10, step 5) is finally performed to thin the silicon substrate 201 from the second surface of the silicon substrate 201.
Illustratively, the silicon substrate 201 is thinned by a mechanical grinding process, and the thickness of the thinned silicon substrate 201 ranges from 0 μm to 700 μm. For example, the thickness of the silicon substrate 201 is preferably 50 to 100 μm, which can ensure the mechanical strength and the thickness of a smaller package structure. It is further noted that the silicon substrate 201 can be completely removed by a thinning process, and the fingerprint identification chip can be protected by the redistribution layer and/or the protection layer 208. Of course, other thinning processes are equally applicable and are not limited to the examples listed herein.
Finally, the packaged fingerprint identification chip 206 is configured with a suitable frame, so that the fingerprint identification chip can be applied to different functional components, such as a mobile phone, a tablet computer, an access control device, and the like.
As shown in fig. 10, the present embodiment further provides a package structure of a fingerprint identification chip 206, where the package structure includes: a silicon substrate 201; a rewiring layer formed on the surface of the silicon substrate 201; a metal bump 205 formed on the rewiring layer; the fingerprint identification chip 206 is arranged on the rewiring layer through a metal welding spot 207, wherein the front surface of the fingerprint identification chip 206 faces the rewiring layer; and a packaging material 209 covering the fingerprint identification chip 206, wherein the metal bump 205 is exposed out of the packaging material 209.
As an example, there is a gap between the fingerprint identification chip 206 and the redistribution layer, and a protection layer 208 is formed in the gap, and the protection layer 208 completely covers the front surface of the fingerprint identification chip 206. Further, the protective layer 208 is selected from epoxy resin.
As an example, the area of the redistribution layer corresponding to the vertical direction of the fingerprint identification chip 206 includes a continuous dielectric layer 203 and does not include a metal layer, so as to serve as the identification window 202 of the fingerprint identification chip 206.
By way of example, the encapsulation material 209 includes one of polyimide, silicone, and epoxy.
Illustratively, the re-routing layer includes a patterned dielectric layer 203 and a patterned metal routing layer 204. Further, the material of the dielectric layer 203 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the metal wiring layer 204 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
By way of example, the metal bump 205 includes a copper pillar, a nickel layer on an upper surface of the copper pillar, and a solder bump on the nickel layer. Further, the metal barrier layer comprises a nickel layer, and the material of the solder bump comprises one of lead, tin and silver or an alloy containing any one of the above solder metals.
By way of example, the silicon substrate 201 has a thickness in the range of 1 μm to 700 μm. For example, in the package structure of the fingerprint identification chip of the present example, the thickness of the silicon substrate 201 is preferably 50 to 100 μm, which can ensure the mechanical strength on one hand and the smaller thickness on the other hand. The silicon substrate 201 is used as a protective cover plate of the fingerprint identification chip packaging structure, a sapphire cover plate does not need to be additionally arranged, the process is smooth, and meanwhile, the cost is saved.
As shown in fig. 11, the principle of the package structure of the fingerprint identification chip 206 of the present embodiment is as shown in fig. 11, and includes:
in the first step, an image of the fingerprint to be identified is obtained through the package structure of the fingerprint identification chip 206. In this embodiment, an image of the fingerprint to be identified is acquired through the identification window 202.
And secondly, preprocessing the acquired fingerprint image as follows: the method comprises the steps of image quality judgment, image enhancement, fingerprint region detection, fingerprint directional diagram and frequency estimation, image binarization (setting the gray value of each pixel point in a fingerprint image to be 0 or 255) and image thinning.
And thirdly, acquiring ridge line data of the fingerprint from the preprocessed image.
And fourthly, extracting characteristic points required by fingerprint identification from ridge line data of the fingerprint.
And fifthly, matching the extracted fingerprint features (information of the feature points) with the fingerprint features stored in the database one by one, and judging whether the extracted fingerprint features are the same fingerprints.
And sixthly, outputting a processing result of fingerprint identification after finishing fingerprint matching processing.
As described above, the package structure and the package method of the fingerprint identification chip 206 of the present invention have the following advantages:
1) the Fan-out type packaging (Fan out) fingerprint identification chip 206 is adopted, and compared with the existing packaging of other fingerprint identification chips 206, the Fan-out type fingerprint identification chip has the advantages of low cost, small thickness and high yield;
2) the invention can realize the packaging of the fingerprint identification chip 206 without a routing process and a high-cost Through Silicon Via (TSV) process, thereby greatly reducing the process difficulty and the cost;
3) the rewiring layer or the lamination of the rewiring layer and the silicon substrate sheet is directly adopted as the cover plate of the fingerprint identification chip 206, and a sapphire cover plate is not required to be additionally arranged, so that the thickness and the cost of packaging are greatly reduced;
4) the invention adopts Fan-out packaging (Fan out) process, the electric leading-out of the chip does not need the traditional FPC board, the packaging thickness and the stability of the electric leading-out structure can be reduced, and the packaging yield is improved;
5) the invention has simple process, creatively adopts fan-out packaging process to package the fingerprint identification chip 206, and has wide application prospect in the technical field of semiconductor packaging.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A packaging structure of a fingerprint identification chip is characterized in that the packaging structure comprises:
the silicon substrate is 1-100 mu m thick;
the rewiring layer is formed on the silicon substrate and comprises a graphical dielectric layer and a graphical metal wiring layer;
the metal bump is formed on the patterned metal wiring layer;
the fingerprint identification chip is arranged on the rewiring layer through a metal welding spot, wherein the metal welding spot is formed on the graphical metal wiring layer, the front surface of the fingerprint identification chip faces the rewiring layer, and a vertical corresponding area of the rewiring layer and the fingerprint identification chip comprises a continuous dielectric layer and does not comprise the metal wiring layer to be used as an identification window of the fingerprint identification chip; and
and the packaging material is covered on the fingerprint identification chip, and the metal lug is exposed out of the packaging material.
2. The package structure of fingerprint identification chip of claim 1, wherein: a gap is formed between the fingerprint identification chip and the rewiring layer, a protective layer is formed in the gap, and the protective layer completely covers the front face of the fingerprint identification chip.
3. The package structure of fingerprint identification chip of claim 2, wherein: the protective layer is made of epoxy resin.
4. The package structure of fingerprint identification chip of claim 1, wherein: the packaging material comprises one of polyimide, silica gel and epoxy resin.
5. The package structure of fingerprint identification chip of claim 1, wherein: the dielectric layer is made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide and phosphorosilicate glass, and the fluorine-containing glass, and the metal wiring layer is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
6. The package structure of fingerprint identification chip of claim 1, wherein: the metal bump comprises a copper column, a metal barrier layer positioned on the upper surface of the copper column and a solder bump positioned on the metal barrier layer.
7. The package structure of fingerprint identification chip of claim 6, wherein: the metal barrier layer comprises a nickel layer, and the solder bump is made of one of lead, tin and silver or an alloy containing any one of the solder metals.
8. A packaging method of a fingerprint identification chip is characterized by comprising the following steps:
1) providing a silicon substrate, wherein the silicon substrate is provided with a first surface and a second surface which are opposite;
2) forming a dielectric layer on the surface of the silicon substrate by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form a patterned dielectric layer; forming a metal layer on the surface of the patterned dielectric layer by adopting a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and etching the metal layer to form a patterned metal wiring layer; forming a rewiring layer on the first surface of the silicon substrate, and forming a metal bump on the patterned metal wiring layer;
3) providing a fingerprint identification chip, and installing the fingerprint identification chip on the rewiring layer through a metal welding spot, wherein the metal welding spot is formed on the graphical metal wiring layer, the front surface of the fingerprint identification chip faces the rewiring layer, and the vertically corresponding area of the rewiring layer and the fingerprint identification chip comprises a continuous dielectric layer and does not comprise the metal wiring layer to be used as an identification window of the fingerprint identification chip;
4) packaging the fingerprint identification chip by adopting a packaging material, wherein the metal lug is exposed out of the packaging material; and
5) thinning the silicon substrate from the second surface of the silicon substrate; and thinning the silicon substrate by adopting a mechanical grinding process, wherein the thickness range of the thinned silicon substrate is 1-100 mu m.
9. The packaging method of the fingerprint identification chip of claim 8, wherein: in step 3), after the fingerprint identification chip is mounted on the rewiring layer through the metal welding spot, a gap is formed between the fingerprint identification chip and the rewiring layer, and step 3) further comprises a step of forming a protective layer in the gap, wherein the protective layer completely covers the front surface of the fingerprint identification chip.
10. The packaging method of the fingerprint identification chip of claim 9, wherein: the protective layer is made of epoxy resin and is formed in a gap between the fingerprint identification chip and the rewiring layer in a dispensing or die pressing mode.
11. The packaging method of the fingerprint identification chip of claim 8, wherein: the dielectric layer is made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide and phosphorosilicate glass, and the fluorine-containing glass, and the metal wiring layer is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
12. The packaging method of the fingerprint identification chip of claim 8, wherein: the preparation method of the metal bump comprises the following steps:
a) forming a copper column on the surface of the rewiring layer by adopting an electroplating method;
b) forming a metal barrier layer on the surface of the copper pillar by adopting an electroplating method;
c) and forming solder metal on the surface of the metal barrier layer by adopting an electroplating method, and forming solder bumps on the surface of the metal barrier layer by adopting a high-temperature reflow process.
13. The packaging method of fingerprint identification chip of claim 12, wherein: the metal barrier layer comprises a nickel layer, and the solder bump is made of one of lead, tin and silver or an alloy containing any one of the solder metals.
14. The packaging method of the fingerprint identification chip of claim 8, wherein: the method for packaging the fingerprint identification chip by adopting the packaging material comprises one of compression molding, transfer molding, liquid seal molding, vacuum lamination and spin coating, wherein the packaging material comprises one of polyimide, silica gel and epoxy resin.
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| CN110148567A (en) * | 2019-06-06 | 2019-08-20 | 中芯长电半导体（江阴）有限公司 | A kind of encapsulating structure and packaging method of fingerprint recognition chip |
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| CN104201115A (en) * | 2014-09-12 | 2014-12-10 | 苏州晶方半导体科技股份有限公司 | Wafer-level fingerprint recognition chip packaging structure and method |
| CN105470207A (en) * | 2015-12-24 | 2016-04-06 | 华天科技（西安）有限公司 | Fingerprint identification chip packaging structure based on high-flatness substrate and manufacturing method thereof |
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| CN104201115A (en) * | 2014-09-12 | 2014-12-10 | 苏州晶方半导体科技股份有限公司 | Wafer-level fingerprint recognition chip packaging structure and method |
| CN105470207A (en) * | 2015-12-24 | 2016-04-06 | 华天科技（西安）有限公司 | Fingerprint identification chip packaging structure based on high-flatness substrate and manufacturing method thereof |
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