CN107169917A - Vector graphics processor does not complete the device of graph image real-time rendering by DDR - Google Patents
Vector graphics processor does not complete the device of graph image real-time rendering by DDR Download PDFInfo
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- CN107169917A CN107169917A CN201710265440.3A CN201710265440A CN107169917A CN 107169917 A CN107169917 A CN 107169917A CN 201710265440 A CN201710265440 A CN 201710265440A CN 107169917 A CN107169917 A CN 107169917A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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Abstract
The present invention provides the device that a kind of vector graphics processor does not complete graph image real-time rendering by DDR, and described device is connected with the central processing unit and image display inside SOC, and described device includes：Vector graphics processor, the first data selector, the second data selector, the 3rd data selector, the 4th data selector, the first internal storage, the second internal storage, the 3rd internal storage, the 4th internal storage and display controller.Present invention saves the area of whole SOC.97% memory area can be saved.Because the speed for accessing internal storage SRAM is more faster than access DDR, the present invention is greatly improved the performance of SOC inter access memory, reduces system power dissipation.The present invention has framework clear, and the division of labor is clear and definite, easily realizes, the advantages of software control flow is simple can be widely applied in Internet of Things, wearable device and mobile unit.
Description
Technical field
The present invention relates to image processing field, more particularly to a kind of vector graphics processor does not complete figure by DDR
The device of image real-time rendering.
Background technology
In the existing chip architecture comprising vector graphics processor, the storage part required for vector graphics processor
External memory storage DDR including vector graphics processor internal storage SRAM and vector graphics processor.Internal storage
SRAM is interim treatment region of the vector graphics processor in configuration processor, and its outstanding advantages are that access speed is fast, but are held
Amount is typically small.External memory storage DDR is the external data needed for storing vector graphics computing device program, DDR's
Capacity is larger, and access speed is slow, in a SOC system, and the ratio that DDR cost is shared in holistic cost is increasing.
With continuing to develop that wearable device and Internet of Things are applied, the vector graphics processor chips pair of embedded product
The requirement more and more higher of area and performance.In the design of vector graphics processor chips, chip area and raising are saved
Performance is the main direction of studying of chip designer.How area is reduced as best one can and is carried while ensureing that chip functions are complete
High-performance, becomes a difficult point and important topic for chip design field.Therefore the present invention proposes one kind without using outside
Memory DDR vector graphics processor chips solution, in this solution, all vector graphics processors are deposited
Storage part is all to use internal storage SRAM, due to external memory storage DDR interview of the area in whole SOC and into
This is shared than larger, therefore can be substantially reduced without using external memory storage DDR the area of whole vector graphics processor chips
With SOC cost, simultaneously because internal storage SRAM speed is faster, the performance of vector graphics processor chips can also be carried
It is high.
Graph image real-time rendering is not completed by DDR there is provided a kind of vector graphics processor in view of the above, to subtract
The device of few vector graphics processor chips area and raising vector graphics processor performance is necessary.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of vector graphics processor is obstructed
The device that DDR completes graph image real-time rendering is crossed, it is excessive for solving vector graphics processor chips area in the prior art
With vector graphics processor performance it is relatively low the problem of.
In order to achieve the above objects and other related objects, a kind of vector graphics processor of present invention offer is not complete by DDR
Into the device of graph image real-time rendering, described device is connected with the central processing unit and image display inside SOC, institute
Stating device includes：Vector graphics processor, the first data selector, the second data selector, the 3rd data selector, the 4th number
According to selector, the first internal storage, the second internal storage, the 3rd internal storage, the 4th internal storage and display
Controller；The central processing unit is connected with first data selector, in first data selector and described first
Portion's memory and second internal storage are connected, second data selector and first internal storage and
Second internal storage is connected, the vector graphics processor and second data selector and the 3rd data
Selector is connected, and the 3rd data selector is connected with the 3rd internal storage and the 4th internal storage,
4th data selector is connected with the 3rd internal storage and the 4th internal storage, the display control
Device is connected with the 4th data selector and described image display；The central processing unit is used to send row synchronously and arranged
Order and data required for synchronizing signal to described device, and transmission vector graphics processor；The first data selection
Device, the second data selector, the 3rd data selector and the 4th data selector are used for order and the transmission of data；Described first
Internal storage, the second internal storage, the 3rd internal storage and the 4th internal storage are used for needed for one two field picture of storage
Order and data；The vector graphics processor is used to complete graph image real-time rendering according to the order and data；Institute
State display controller be used for read data and according to image display protocol output image to described image display.
Preferably, described device is when handling image using 8 rows as a processing unit, and the summation of each processing unit is
The pixel of 8 times of picture traverses.
Preferably, the central processing unit is used to sending that row to be synchronous and row synchronizing signal, and by vector graphics processor
Required order and data is written in the first internal storage or the second internal storage by the first data selector.
Preferably, first data selector be used for control will order and data be written to the first internal storage or
In second internal storage, in the first two field picture, order and data are written to inside first by the first data selector and deposited
In reservoir, in the second two field picture, order and data are written in the second internal storage by the first data selector, afterwards
It is alternately written into successively into the first internal storage or the second internal storage.
Preferably, first internal storage and the second internal storage be used for store a two field picture needed for order and
Data, the first internal storage and the second internal storage are used alternatingly in units of a two field picture, in the first frame figure
Before as starting, central processing unit will be ordered and data are written to the first internal storage by the first data selector, work as arrow
When order in spirogram shape the first internal storage of computing device and data, central processing unit will be ordered and data pass through first
Data selector is written to the second internal storage, then when next two field picture starts, vector graphics computing device second
Order and data in internal storage, while central processing unit will be ordered and data are written to the by the first data selector
In one internal storage, by that analogy, in ensuing image, vector graphics processor is alternately performed the first internal storage
With the order in the second internal storage and data.
Preferably, second data selector is used to control by the first internal storage or the second internal storage
Data and order read in vector graphics processor.
Preferably, the order in the internal storage of vector graphics computing device first or the second internal storage
And corresponding figure is drawn out, and 8 line numbers have often been drawn for sending capable synchronous and row synchronizing signal according to central processing unit
According to just drawn data are written in the 3rd internal storage or the 4th internal storage by the 3rd data selector.
Preferably, the 3rd data selector is used to control to write the drawn data of the vector graphics processor
Into the 3rd internal storage or the 4th internal storage, when first 8 row Image Rendering is complete, drawn data pass through
3rd data selector is written in the 3rd internal storage, and when second 8 row Image Rendering is complete, drawn data pass through
3rd data selector is written in the 4th internal storage, and every 8 row data afterwards are alternately written into inside the 3rd successively deposits
In reservoir or the 4th internal storage.
Preferably, the 3rd internal storage and the 4th internal storage are drawn for storing vector graphics processor
8 row data, the 3rd internal storage and the 4th internal storage are used alternatingly in units of 8 row data, in first 8 line number
Before write-in, 8 row data are written to the 3rd internal storage by vector graphics processor by the 3rd data selector, when aobvious
When showing that controller reading reads the data in the 3rd internal storage by the 4th data selector, vector graphics processor is by under
One group of 8 row data is written to the 4th internal storage by the 3rd data selector, then when next group of 8 row data start,
Display controller reads the data in the 4th internal storage, while 8 new row data are passed through the 3rd by vector graphics processor
Data selector is written in the 3rd internal storage, by that analogy.
Preferably, the 4th data selector is used to control by the 3rd internal storage or the 4th internal storage
Digital independent into display controller, the display controller be used for control deposited inside the 3rd internal storage or the 4th
The data that are read in reservoir and according to image display protocol output image into image display, the display controller is output to
Data include row synchronizing signal, line synchronising signal and row view data in image display.
As described above, the vector graphics processor of the present invention does not complete the device of graph image real-time rendering, tool by DDR
There is following beneficial effect：
1) present invention saves the area of whole SOC.By taking 1920x1080 resolution ratio as an example, present invention uses 4
Individual internal storage SRAM, the size of each internal storage is 1920*8*4 bytes；If using traditional DDR scheme, needed
The memory size to be prepared is 1920*1080*4 bytes, and 97% memory area can be saved using new scheme.
2) present invention can improve the performance of SOC inter access memory, because accessing internal storage
SRAM speed is more faster than accessing DDR.By reducing data delay, it can just reach that image is real-time with relatively low clock frequency
Draw.System power dissipation can be reduced while the performance for improving graphics process.
3) present invention does not complete the framework method of graph image real-time rendering by DDR, and present system is considered well
In each submodule collaborative work relation, clear with framework, the division of labor is clear and definite, easily realizes, it is excellent that software control flow is simple etc.
Point, can be widely applied in Internet of Things, wearable device and mobile unit.
Brief description of the drawings
The vector graphics processor that Fig. 1 is shown as the present invention does not complete the device of graph image real-time rendering by DDR
Structural representation.
The vector graphics processor that Fig. 2 is shown as the present invention is not walked by the DDR methods for completing graph image real-time rendering
Rapid flow chart.
Component label instructions
101 first data selectors
102 second data selectors
103 the 3rd data selectors
104 the 4th data selectors
105 first internal storages
106 second internal storages
107 the 3rd internal storages
108 the 4th internal storages
109 vector graphics processors
110 display controllers
201 central processing units
301 image displays
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1~Fig. 2.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only display is with relevant component in the present invention rather than according to package count during actual implement in illustrating then
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in figure 1, a kind of vector graphics processor 109 of the present embodiment offer is not real-time by DDR completion graph images
The device of drafting, described device is connected with the central processing unit 201 and image display 301 inside SOC, described device bag
Include：Vector graphics processor 109, the first data selector 101, the second data selector 102, the 3rd data selector 103,
Four data selectors 104, the first internal storage 105, the second internal storage 106, in the 3rd internal storage the 107, the 4th
Portion's memory 108 and display controller 110；The central processing unit 201 is connected with first data selector 101, institute
The first data selector 101 is stated with first internal storage 105 and second internal storage 106 to be connected, it is described
Second data selector 102 is connected with first internal storage 105 and second internal storage 106, the arrow
Amount graphics processor 109 is connected with second data selector 102 and the 3rd data selector 103, and the described 3rd
Data selector 103 is connected with the 3rd internal storage 107 and the 4th internal storage 108, the 4th number
It is connected according to selector 104 with the 3rd internal storage 107 and the 4th internal storage 108, the display control
Device 110 is connected with the 4th data selector 104 and described image display 301；
The central processing unit 201 is used to send row synchronously and row synchronizing signal is to described device, and sends polar plot
Order and data required for shape processor 109；First data selector 101, the second data selector the 102, the 3rd number
It is used to order the transmission with data according to the data selector 104 of selector 103 and the 4th；First internal storage 105, second
Internal storage 106, the 3rd internal storage 107 and the 4th internal storage 108 are used to store the order needed for a two field picture
And data；The vector graphics processor 109 is used to complete graph image real-time rendering according to the order and data；It is described aobvious
Show controller 110 be used for read data and according to image display protocol output image to described image display 301.
Described device is when handling image using 8 rows as a processing unit, and the summation of each processing unit is 8 times of images
The pixel of width.Central processing unit 201 is by continuously transmitting capable synchronous and row synchronizing signal to the vector graphics processor
109 do not complete the device of graph image real-time rendering to control the operation of this device by DDR.
The central processing unit 201 is used to sending that row to be synchronous and row synchronizing signal, and by the institute of vector graphics processor 109
The order and data needed is written to the first internal storage 105 or the second internal storage by the first data selector 101
In 106.
First data selector 101 be used for control will order and data be written to the first internal storage 105 or
In second internal storage 106, in the first two field picture, order and data are written to first by the first data selector 101
In internal storage 105, in the second two field picture, order and data are written to inside second by the first data selector 101
In memory 106, it is alternately written into successively afterwards into the first internal storage 105 or the second internal storage 106.
The internal storage 106 of first internal storage 105 and second be used for store a two field picture needed for order and
Data, the first internal storage 105 and the second internal storage 106 are used alternatingly in units of a two field picture,
Before one two field picture starts, central processing unit 201 will be ordered and data are written to inside first by the first data selector 101
Memory 105, when vector graphics processor 109 performs order and data in the first internal storage 105, central processing unit
Order and data are written to the second internal storage 106 by 201 by the first data selector 101, then in next two field picture
During beginning, vector graphics processor 109 performs order and data in the second internal storage 106, while central processing unit 201
Order and data are written in the first internal storage 105 by the first data selector 101, by that analogy, following
Image in, vector graphics processor 109 is alternately performed the life in the first internal storage 105 and the second internal storage 106
Order and data.
Second data selector 102 is used to control the first internal storage 105 or the second internal storage 106
In data and order read in vector graphics processor 109.
The vector graphics processor 109 performs the life in the first internal storage 105 or the second internal storage 106
Make and draw out corresponding figure, and 8 have often been drawn for sending capable synchronous and row synchronizing signal according to central processing unit 201
Drawn data, are just written to inside the 3rd internal storage 107 or the 4th by row data by the 3rd data selector 103
In memory 108.
3rd data selector 103 is used to control to write the drawn data of the vector graphics processor 109
Into the 3rd internal storage 107 or the 4th internal storage 108, when first 8 row Image Rendering is complete, drawn number
It is written in the 3rd internal storage 107, when second 8 row Image Rendering is complete, draws according to by the 3rd data selector 103
Good data are written in the 4th internal storage 108 by the 3rd data selector 103, and every 8 row data afterwards are handed over successively
For being written in the 3rd internal storage 107 or the 4th internal storage 108.
3rd internal storage 107 and the 4th internal storage 108 are painted for storing vector graphics processor 109
8 row data of system, the 3rd internal storage 107 and the 4th internal storage 108 be used alternatingly in units of 8 row data, the
Before one 8 row data write-in, 8 row data are written to the 3rd by vector graphics processor 109 by the 3rd data selector 103
Internal storage 107, is read in the 3rd internal storage 107 when display controller 110 is read by the 4th data selector 104
Data when, next group of 8 row data are written to inside the 4th by vector graphics processor 109 by the 3rd data selector 103
Memory 108, then when next group of 8 row data start, display controller 110 reads the number in the 4th internal storage 108
According to while 8 new row data are written to the 3rd storage inside by vector graphics processor 109 by the 3rd data selector 103
In device 107, by that analogy.
4th data selector 104 is used to control the 3rd internal storage 107 or the 4th internal storage 108
In digital independent into display controller 110, the display controller 110 be used to control from the 3rd internal storage 107 or
The data that are read in the internal storage 108 of person the 4th and according to image display protocol output image into image display 301, institute
Stating display controller 110 and being output in image display 301 data includes row synchronizing signal, line synchronising signal and row picture number
According to.
It should be noted that the present embodiment provide only a kind of relatively simple vector graphics processor 109 not by DDR
The device of graph image real-time rendering is completed, in other implementation processes, it is public that those skilled in the art are based on the present embodiment institute
After the scheme opened, it is extended by increasing the quantity of data selector and internal storage come the device to the present embodiment,
Such as increase by 1~100 data selector and 1~100 internal storage, based on the present embodiment disclosure of that, lead to
The annexation for designing each part is crossed, can obtain that disposal ability is stronger, more large-scale vector graphics processor 109 does not pass through
DDR complete graph image real-time rendering device, should also belong to the claims in the present invention it is claimed within the scope of.
As shown in Fig. 2 the present embodiment also provides a kind of vector graphics processor 109 does not complete graph image reality by DDR
When the method drawn, comprise the following steps：
Step 1), the device that a kind of vector graphics processor 109 does not complete graph image real-time rendering by DDR is built,
Described device is connected with the central processing unit 201 and image display 301 inside SOC, and described device includes：Vector graphics
Processor 109, the first data selector 101, the second data selector 102, the 3rd data selector 103, the selection of the 4th data
Device 104, the first internal storage 105, the second internal storage 106, the 3rd internal storage 107, the 4th internal storage
108 and display controller 110；The central processing unit 201 is connected with first data selector 101, first number
It is connected according to selector 101 with first internal storage 105 and second internal storage 106, second data
Selector 102 is connected with first internal storage 105 and second internal storage 106, at the vector graphics
Reason device 109 is connected with second data selector 102 and the 3rd data selector 103, the 3rd data selection
Device 103 is connected with the 3rd internal storage 107 and the 4th internal storage 108, the 4th data selector
104 are connected with the 3rd internal storage 107 and the 4th internal storage 108, the display controller 110 and institute
State the 4th data selector 104 and described image display 301 is connected.
Step 2), the central processing unit 201 is used to send capable synchronous and row synchronizing signal, and vector graphics is handled
Order and data required for device 109 are written to inside the first internal storage 105 or the second by the first data selector 101
In memory 106, in the first two field picture, order and data are written to the first storage inside by the first data selector 101
In device 105, in the second two field picture, order and data are written to the second internal storage 106 by the first data selector 101
In, it is alternately written into successively afterwards into the first internal storage 105 or the second internal storage 106.
Step 3), the internal storage 106 of the first internal storage 105 and second stores the order needed for a two field picture
And data, the first internal storage 105 and the second internal storage 106 be used alternatingly in units of a two field picture,
Before first two field picture starts, central processing unit 201 will be ordered and data are written in first by the first data selector 101
Portion's memory 105, when vector graphics processor 109 performs order and data in the first internal storage 105, center processing
Device 201 will be ordered and data are written to the second internal storage 106 by the first data selector 101, then in next frame figure
During as starting, vector graphics processor 109 performs order and data in the second internal storage 106, while central processing unit
201 are written to order and data in the first internal storage 105 by the first data selector 101, by that analogy；
Step 4), in ensuing image, vector graphics processor 109 is alternately held by the second data selector 102
Row the first internal storage 105 and order in the second internal storage 106 and data draw out corresponding figure, and in
Central processor 201 is used to sending that row to be synchronous and row synchronizing signal, has often drawn 8 row data, and drawn data just are passed through into the
Three data selectors 103 are written in the 3rd internal storage 107 or the 4th internal storage 108；For example, in first 8 row
When Image Rendering is complete, drawn data are written in the 3rd internal storage 107 by the 3rd data selector 103,
When two 8 row Image Renderings are complete, drawn data are written to the 4th internal storage 108 by the 3rd data selector 103
In, every 8 row data afterwards are alternately written into the 3rd internal storage 107 or the 4th internal storage 108 successively.
Step 5), before first 8 row data write-in, 8 row data are passed through the 3rd data by vector graphics processor 109
Selector 103 is written to the 3rd internal storage 107, is read when display controller 110 is read by the 4th data selector 104
During data in the 3rd internal storage 107, vector graphics processor 109 selects next group of 8 row data by the 3rd data
Device 103 is written to the 4th internal storage 108, then when next group of 8 row data start, and display controller 110 reads the 4th
Data in internal storage 108, while 8 new row data are passed through the 3rd data selector 103 by vector graphics processor 109
It is written in the 3rd internal storage 107, by that analogy.
Step 6), the 4th data selector 104 is controlled the 3rd internal storage 107 or the 4th internal storage
Digital independent in 108 is into display controller 110, and the display controller 110 is used to control from the 3rd internal storage 107
Or the 4th the data read in internal storage 108 and according to image display protocol output image into image display 301,
The display controller 110, which is output to data in image display 301, includes row synchronizing signal, line synchronising signal and row picture number
According to.
As described above, the vector graphics processor 109 of the present invention does not complete the dress of graph image real-time rendering by DDR
Put, have the advantages that：
1) present invention saves the area of whole SOC.By taking 1920x1080 resolution ratio as an example, present invention uses 4
Individual internal storage SRAM, the size of each internal storage is 1920*8*4 bytes；If using traditional DDR scheme, needed
The memory size to be prepared is 1920*1080*4 bytes, and 97% memory area can be saved using new scheme.
2) present invention can improve the performance of SOC inter access memory, because accessing internal storage
SRAM speed is more faster than accessing DDR.By reducing data delay, it can just reach that image is real-time with relatively low clock frequency
Draw.System power dissipation can be reduced while the performance for improving graphics process.
3) present invention does not complete the framework method of graph image real-time rendering by DDR, and present system is considered well
In each submodule collaborative work relation, clear with framework, the division of labor is clear and definite, easily realizes, it is excellent that software control flow is simple etc.
Point, can be widely applied in Internet of Things, wearable device and mobile unit.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of vector graphics processor does not complete the device of graph image real-time rendering by DDR, it is characterised in that the dress
Put and be connected with the central processing unit and image display inside SOC, described device includes：Vector graphics processor, first
Data selector, the second data selector, the 3rd data selector, the 4th data selector, the first internal storage, in second
Portion's memory, the 3rd internal storage, the 4th internal storage and display controller；
The central processing unit is connected with first data selector, is deposited inside first data selector and described first
Reservoir and second internal storage are connected, second data selector and first internal storage and described
Second internal storage is connected, and the vector graphics processor is selected with second data selector and the 3rd data
Device is connected, and the 3rd data selector is connected with the 3rd internal storage and the 4th internal storage, described
4th data selector is connected with the 3rd internal storage and the 4th internal storage, the display controller with
4th data selector and described image display are connected；
The central processing unit is used to send row synchronously and row synchronizing signal is to described device, and sends vector graphics processor
Required order and data；
First data selector, the second data selector, the 3rd data selector and the 4th data selector are used to order
With the transmission of data；
First internal storage, the second internal storage, the 3rd internal storage and the 4th internal storage are used to store
Order and data needed for one two field picture；
The vector graphics processor is used to complete graph image real-time rendering according to the order and data；
The display controller is used for the data read and according to image display protocol output image to described image display.
2. vector graphics processor according to claim 1 does not complete the device of graph image real-time rendering by DDR, its
It is characterised by：Described device is when handling image using 8 rows as a processing unit, and the summation of each processing unit is 8 times of figures
The pixel of image width degree.
3. vector graphics processor according to claim 1 does not complete the device of graph image real-time rendering by DDR, its
It is characterised by：The central processing unit is used to send capable synchronous and row synchronizing signal, and by required for vector graphics processor
Order and data be written to by the first data selector in the first internal storage or the second internal storage.
4. vector graphics processor according to claim 1 does not complete the device of graph image real-time rendering by DDR, its
It is characterised by：First data selector is used to control order and data being written in the first internal storage or second
In portion's memory, in the first two field picture, order and data are written in the first internal storage by the first data selector,
In the second two field picture, order and data are written in the second internal storage by the first data selector, are handed over successively afterwards
For being written in the first internal storage or the second internal storage.
5. vector graphics processor according to claim 1 does not complete the device of graph image real-time rendering by DDR, its
It is characterised by：The order and data of first internal storage and the second internal storage needed for for storing a two field picture,
First internal storage and the second internal storage are used alternatingly in units of a two field picture, are started in the first two field picture
Before, central processing unit will be ordered and data are written to the first internal storage by the first data selector, work as vector graphics
When order in the internal storage of computing device first and data, central processing unit will be ordered and data are selected by the first data
Select device and be written to the second internal storage, then when next two field picture starts, deposited inside vector graphics computing device second
Order and data in reservoir, while central processing unit will be ordered and data are written to inside first by the first data selector
In memory, by that analogy, in ensuing image, vector graphics processor is alternately performed the first internal storage and second
Order and data in internal storage.
6. vector graphics processor according to claim 1 does not complete the device of graph image real-time rendering by DDR, its
It is characterised by：Second data selector is used to control the data in the first internal storage or the second internal storage
Read with order in vector graphics processor.
7. vector graphics processor according to claim 1 does not complete the device of graph image real-time rendering by DDR, its
It is characterised by：The internal storage of vector graphics computing device first or order and drafting in the second internal storage
Go out corresponding figure, and according to central processing unit be used to sending that row to be synchronous and row synchronizing signal, often drawn 8 row data, just will
Drawn data are written in the 3rd internal storage or the 4th internal storage by the 3rd data selector.
8. vector graphics processor according to claim 1 does not complete the device of graph image real-time rendering by DDR, its
It is characterised by：3rd data selector is used to control the drawn data of the vector graphics processor being written to the 3rd
In internal storage or the 4th internal storage, when first 8 row Image Rendering is complete, drawn data pass through the 3rd number
It is written to according to selector in the 3rd internal storage, when second 8 row Image Rendering is complete, drawn data pass through the 3rd number
Be written to according to selector in the 4th internal storage, every 8 row data afterwards be alternately written into successively to the 3rd internal storage or
In the internal storage of person the 4th.
9. vector graphics processor according to claim 1 does not complete the device of graph image real-time rendering by DDR, its
It is characterised by：3rd internal storage and the 4th internal storage are used for storing 8 rows that vector graphics processor is drawn
Data, the 3rd internal storage and the 4th internal storage are used alternatingly in units of 8 row data, are write in first 8 row data
Before entering, 8 row data are written to the 3rd internal storage by vector graphics processor by the 3rd data selector, when display control
When device reading processed reads the data in the 3rd internal storage by the 4th data selector, vector graphics processor is by next group
8 row data are written to the 4th internal storage by the 3rd data selector, then when next group of 8 row data start, display
Controller reads the data in the 4th internal storage, while 8 new row data are passed through the 3rd data by vector graphics processor
Selector is written in the 3rd internal storage, by that analogy.
10. vector graphics processor according to claim 1 does not complete the device of graph image real-time rendering by DDR,
It is characterized in that：4th data selector is used to control the number in the 3rd internal storage or the 4th internal storage
According to reading in display controller, the display controller is used to control from the 3rd internal storage or the 4th internal storage
The data of middle reading and according to image display protocol output image into image display, the display controller is output to image
Data include row synchronizing signal, line synchronising signal and row view data in display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710265440.3A CN107169917B (en) | 2017-04-21 | 2017-04-21 | Device for vector graphics processor to finish real-time drawing of graphics image without DDR |
Applications Claiming Priority (1)
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