CN107168172B

CN107168172B - Switching value acquisition device based on CPLD

Info

Publication number: CN107168172B
Application number: CN201710429776.9A
Authority: CN
Inventors: 蔡志伟; 孙荣智; 丁宝华
Original assignee: Beijing Danhua Haobo Power Science And Technology Co ltd
Current assignee: Beijing Danhua Haobo Power Science And Technology Co ltd
Priority date: 2017-06-09
Filing date: 2017-06-09
Publication date: 2020-06-30
Anticipated expiration: 2037-06-09
Also published as: CN107168172A

Abstract

A switching value acquisition device based on a CPLD technology comprises a switching value input, a photoelectric coupler, a bus driver, a CPLD, a CPU, an RS232 transceiver and an RS485 transceiver; the input end of the photoelectric coupler is connected to the switching value input terminal, and the input end of the bus driver is connected to the output end of the photoelectric coupler; the output end of the bus driver is connected to the input end of the CPLD; the CPLD is connected to the CPU through parallel buses (data bus DB [15:0], address bus AD [25:23], nRD read enable signal, nCS0 chip select signal). The CPU realizes RS232 and RS485 communication through integrating the UART0 and the UART1 and transmits switching value data information to the host, and the switching value sampling device can be used for collecting switching value signals of electric automation equipment and providing high-reliability real-time data collection for realizing automation functions of power equipment. The invention has mature technology and high reliability.

Description

Switching value acquisition device based on CPLD

Technical Field

The invention relates to the technical field of electric power, is mainly used for collecting switching value signals of electric automation equipment and is a common device of the electric automation equipment.

Background

For the field of power automation, multi-way switching value acquisition is often performed. The signal direct transmission method uses the existence or nonexistence of a signal to represent the validity and invalidity of the signal. This approach has a significant disadvantage: when the signal path is interrupted, the receiving end of the signal cannot determine the state of the signal. And the complex programmable logic device CPLD can conveniently realize the wired real-time data transmission with high reliability. At a sending end, data to be transmitted is coded by a CPU and then sent by wired networks such as optical fibers, cables and the like; at the receiving end, the signal after passing through the front end receiving and adjusting circuit is sent to the CPLD, decoded by the decoding circuit and then output to the CPU. The decoding circuit also filters the received data to filter burrs, thereby ensuring the output data to be real and reliable.

In order to be compatible with the electric automation equipment better, the switching value signal sampling control panel based on the CPLD technology is adopted, so that the capacity expansion requirement of the equipment can be well met.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a switching value acquisition device based on a CPLD (complex programmable logic device) to fill the blank of the related technical fields at home and abroad.

The technical scheme of the invention is as follows:

a switching value acquisition device based on a CPLD comprises a plurality of switching value input ends, a plurality of photoelectric couplers, a plurality of bus drivers corresponding to the photoelectric couplers, the CPLD, a CPU, an RS232 transceiver and an RS485 transceiver; it is characterized in that:

each photoelectric coupler obtains a switching value on-off signal from a switching value input end correspondingly connected with the photoelectric coupler, converts the switching value on-off signal into a 5V level signal and sends the 5V level signal to a bus driver correspondingly connected with the photoelectric coupler;

each bus driver obtains the converted 5V level signal from the corresponding photoelectric coupler, converts the 5V level signal into a 3.3V level signal and sends the 3.3V level signal to the CPLD;

the CPLD receives the 3.3V level signals sent by each bus driver, converts each level signal into binary switching value data information, and then stores the switching value data information into a register of the CPLD;

the CPU reads the switching data information from the CPLD into the CPU through parallel buses (a data bus DB [15:0], an address bus AD [25:23], nRD read enable signals and an nCS0 chip select signal).

The CPU outputs switching data information at CMOS level through the integrated UART0, and then converts the CMOS level into RS232 level signal through the RS232 transceiver connected with the CPU, and transmits the switching data information to the host. The host decodes the received binary data information to generate switching value data information.

The CPU outputs switching data information in a CMOS level through the integrated UART1, then converts the CMOS level into an RS485 differential signal through an RS485 transceiver connected with the CMOS level, and transmits the switching data information to a host.

The invention further comprises the following preferred embodiments:

the photoelectric coupler converts the switching value on-off signal into a 5V level signal, and converts the 5V level signal into a 3.3V level signal through a bus driver to be connected to the CPLD.

The CPU reads data information in the CPLD through a 16-bit parallel bus (a data bus DB [15:0], an address bus AD [25:23], an nRD read enable signal and an nCS0 chip selection signal).

The invention has the following technical effects:

1. the switching value signal acquisition device based on the CPLD adopts an RS485 or RS232 communication mode, can realize high-reliability wired real-time data transmission, and has the advantages of good real-time performance, high controllability and flexible organization. The space and the cost of the PCB can be effectively saved.

2. The board card adopts a plug-in structure.

3. The switching value signal acquisition device based on the CPLD is very convenient for the capacity expansion of the electric automation equipment, each sampling control board can be expanded by 80 paths at most, and only the sampling control board is added when the sampling control board exceeds 80 paths.

Drawings

The abstract attached drawing is a structural schematic diagram of the switching value acquisition device based on the CPLD;

fig. 1 is a block diagram of the switching value acquisition device based on the CPLD of the present invention.

Fig. 2 is a diagram of a data transmission model.

Fig. 3 is a schematic diagram of an RS232 transceiver.

Fig. 4 is a schematic diagram of an RS485 transceiver.

Fig. 5 is a diagram of a switching value acquisition front-end circuit.

Fig. 6 is a timing diagram of data access between the CPU and the CPLD.

Wherein U1, U20 represents 20 inverter inverters; U21-U30 are voltage converter chips; u31 is CPLD, U32 is CPU controller, U33 is RS232 transceiver, U34 is RS485 transceiver.

Detailed Description

The technical scheme of the invention is further explained in detail by specific examples in the following with the specification and the drawings.

The invention provides a switching value signal sampling control panel based on a CPLD technology. The working principle of the sampling control board is as follows: the input end of the NOT gate is changed into a 0-5V level signal from a switching device and a photoelectric coupler at the front end, a voltage signal is obtained through RC filtering and a pull-down resistor, the NOT gate inverts the signal, the digital quantity signal is changed into a 0-3.3V level signal after overvoltage transformation, the digital signal of each channel is decoded and filtered through a CPLD, the NOT gate is communicated with a CPU through a parallel bus, the CPU is encoded through an RS232 transceiver and an RS485 transceiver, high-reliability wired real-time data transmission is achieved, and therefore the collection of switching value information is achieved.

The sampling plate consists of a NOT gate, a voltage converter, a CPLD, a CPU, an RS485 transceiver and an RS232 transceiver, and all components are welded on a PCB.

The sampling plate is based on the principle shown in FIG. 1, including NOT gates U1-U20, voltage converters U21-U30, CPLD chip U31, CPU chip U32, RS232 transceiver U33 and RS485 transceiver U34. U1-U20-U21-U30 show that the digital level signal of 0- +5V is inverted and changed into a digital level signal between 0 and +3.3V, the CPLD decodes and filters each path of digital signal, the CPU reads the switching value signal data from the CPLD through a data bus, and the CPU encodes the switching value signal data through RS485 and RS232 and sends out the data, so that the high-reliability wired real-time data transmission is achieved, and the acquisition of the switching value information is realized.

The data transmission model is as shown in fig. 2, the switching value signal data processed by the voltage converter is connected with the CPLD chip in a parallel data transmission mode, decoded and filtered by the CPLD chip, then connected with the CPU in a parallel data transmission mode, and encoded by the CPU and transmitted in a serial data mode through the RS232 transceiver and the RS485 transceiver, thereby realizing high-reliability wired real-time data transmission.

The RS232 transceiver is schematically shown in fig. 3, and has a function of converting a CMOS level signal output by the CPU into an RS232 level signal, enabling it to communicate with an upper computer (or a main control board), and realizing reliable acquisition of switching value signal data through serial data communication.

The RS485 transceiver is schematically shown in fig. 4, and has a function of converting a CMOS level signal output by the CPU into an RS485 differential signal, so that the RS485 differential signal can communicate with an upper computer (or a main control board), and the transmission of differential data enhances the anti-interference performance of the signal, increases the transmission distance, and thus realizes reliable transmission and acquisition of switching value signal data.

The switching value acquisition front-end circuit is shown in fig. 5, and has the main functions of hardware isolation and filtering, a TLP521 optical coupling isolation chip isolates a system from the outside, and the isolated system passes through a filter circuit composed of a resistor and a capacitor and then is connected to a sampling control panel. Through the optical coupling filtering front-end circuit, the common mode and differential mode interference resistance of the system is greatly enhanced, and surge pulse group interference can be effectively inhibited.

The time sequence between the CPU and the CPLD is shown in figure 6, the CPLD is accessed as a memory, when the CPU collects switching value signals, the CPU sends out a chip selection nCS0, an address signal A25-A23 and a read enable nRD signal through a program instruction, the address information of the CPLD memory is output to the AD [25:23], the nCS0 is enabled to be in a low level, after the signal is established and stabilized, a read signal is sent out (pulled down through nRD), then the CPLD reads the corresponding open port data of the address bus and outputs the port data to the data bus DB [15:0], after the CPU reads the switching value data, nRD is pulled up, after the reading is finished, the chip selection and the address signal (the nCS0 is set high, and the AD [25:23] is set to be high resistance), and one-time signal reading is finished.

While the best mode for carrying out the invention has been described in detail and illustrated in the accompanying drawings, it is to be understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the invention should be determined by the appended claims and any changes or modifications which fall within the true spirit and scope of the invention should be construed as broadly described herein.

Claims

1. A switching value acquisition device based on a CPLD comprises a plurality of switching value input ends, a plurality of photoelectric couplers, a plurality of bus drivers corresponding to the photoelectric couplers, the CPLD, a CPU, an RS232 transceiver and an RS485 transceiver; it is characterized in that:

the NOT gate, the voltage converter, the CPLD, the CPU, the RS485 transceiver and the RS232 transceiver are welded on a PCB;

the on-off signals of every four paths of switching values are connected with the input end of a NOT gate, and the output ends of two NOT gates are connected with the input end of a voltage converter;

each photoelectric coupler obtains a switching signal of the switching value from a switching value input end correspondingly connected with the photoelectric coupler, converts the switching signal into a 5V level signal, obtains a voltage signal through RC filtering and a pull-down resistor, inverts the signal by a NOT gate and inputs the inverted signal into a voltage converter, and the inverted signal is converted into a digital level signal between 0 and +3.3V by the voltage converter and then is sent into the CPLD;

the CPLD receives the digital level signals sent by each voltage converter, decodes and filters each path of digital signals, converts each digital level signal into binary switching value data information, and then stores the switching value data information into a register of the CPLD;

the CPU reads the switching value data information from the CPLD into the CPU through a parallel bus;

the CPU outputs switching value data information in a CMOS level through an integrated serial port UART0, then the CMOS level is converted into an RS232 level signal through an RS232 transceiver connected with a serial port UART0, the switching value data information is transmitted to a host, and the host decodes the received binary data information to generate the switching value data information;

the CPU outputs switching data information in a CMOS level through an integrated serial port UART1, then converts the CMOS level into an RS485 differential signal through an RS485 transceiver connected with a serial port UART1, and transmits the switching data information to a host;

switching value signal data processed by the voltage converter are connected with the CPLD chip in a parallel data transmission mode, decoded and filtered by the CPLD chip, then connected with the CPU in a parallel data transmission mode, and sent out in a serial data mode through the RS232 transceiver and the RS485 transceiver after being coded by the CPU;

the parallel bus between the CPU and the CPLD comprises a data bus DB [15:0], an address bus AD [25:23], an nRD read enable signal line and an nCS0 chip selection signal line;

the CPLD is accessed as a memory, when the CPU collects switching value signals, the CPU sends out a chip selection nCS0, an address signal A25-A23 and a read enable nRD signal through a program instruction, the address information of the CPLD memory is output to the AD [25:23], the nCS0 becomes low level, after the signals are established and stabilized, a read signal is sent out to pull down nRD, then the CPLD reads the data of an open-ended port corresponding to an address bus and outputs the port data to a data bus DB [15:0], after the CPU reads the switching value data, nRD is pulled up, after the reading is finished, the nCS0 is put high, the AD [25:23] is put high resistance, and the signal reading is finished for one time.