CN107146781B - It is a kind of to have core plate structure and its manufacturing method for the two-sided of BOT encapsulation - Google Patents
It is a kind of to have core plate structure and its manufacturing method for the two-sided of BOT encapsulation Download PDFInfo
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- CN107146781B CN107146781B CN201710389777.5A CN201710389777A CN107146781B CN 107146781 B CN107146781 B CN 107146781B CN 201710389777 A CN201710389777 A CN 201710389777A CN 107146781 B CN107146781 B CN 107146781B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
One embodiment of the present of invention, which provides, a kind of two-sided has core plate structure, comprising: in two-sided at least two layers of the semi-solid preparation substrate having on core plate structure two sides；Half embedment route being partly embedded in the semi-solid preparation substrate；Wherein, first face of the half embedment route is located on the surface of the semi-solid preparation substrate ipsilateral with the route, second face opposite with first face of the half embedment route is located under the surface of the semi-solid preparation substrate ipsilateral with the route, a part of the side of the half embedment route is located on the surface of the ipsilateral semi-solid preparation substrate of the route, and another part of the side of the half embedment route is wrapped up by the semi-solid preparation substrate；And solder mask, the solder mask at least partly cover described half surface for being embedded to route, and exposure pad openings.
Description
Technical field
The present invention relates to field of semiconductor package more particularly to it is a kind of for BOT encapsulation it is two-sided have core plate structure and its
Manufacturing method.
Background technique
Increasingly develop to miniaturization, intelligence, high-performance and high reliability direction to meet electronic product, chip
Miniaturization, it is intelligent make the quantity of chip package pin while being promoted, the size of packaging pin also drops at the fast speed；
Meanwhile system in package SiP (System In a Package) is required again by multiple active electron components with different function
It is packaged into a function system with optional passive device, this poses realize multiple high performance chips on a package substrate
Encapsulation requirement.
When chip chip bonding pad spacing less than 50 μm in the case where, encapsulation must use BOT (Bump on Trace) skill
Art, by the copper pillar bump Direct Bonding of chip surface on substrate fine-line, it is desirable that substrate is bonded wire sizes less than 25 μm.
It is to be realized by MSAP or SAP technique, and this manufacturing method manufactures that the prior art manufactures fine-line on having core substrate
Route when line width/line-spacing is less than 20 μm/20 μm, as shown in Figure 1, only bottom contacts its bottom insulation resin to route 120
110, therefore, the binding force of route is very small, when using BOT encapsulating structure, 20 μm of route and ball bond processes below
In, the risk for thering is route to remove, and route is thinner, and risk is bigger.
It is embedded to Line technology ETS (embedded Trace Substrate), is one kind of centreless (Coreless) substrate
Special line construction, because its can accomplish 15 μm/15 μm of minimum feature line-spacing hereinafter, and route control precision it is high, route is embedding
Enter in resin.Refer to that the upper surface of route is coated by resin in so-called embedded resin, route binding force is big.
But conventional embedment Line technology (ETS) uses the two-sided pressing embedded mode of loading plate, is carrying plate surface first
Two layers of extra thin copper foil is made, manufactures high-precision fine rule road in extra thin copper foil facet, presses to form route and bury by insulating resin
Enter the structure of insulating resin, then manufacture subsequent route on insulating resin, behind route after processing is completed by loading plate two sides
Two coreless substrates processed peel, and form two coreless substrate structures with extra thin copper foil embedment route, then will surpass
Thin copper foil etches away, and due to the effect of corrosive agent, being embedded to circuit surface can also be corroded Partial Height, so foring Fig. 2
Shown in the characteristics of being embedded to line construction, being embedded to line construction 220 be that circuit surface is in embedment 210 upper surface of insulating resin
Lower section.This embedment line construction can only be formed in coreless substrate processing.It can be only applied in coreless substrate processing and manufacturing, and
And it is only used for the first sandwich circuit, it is not available therefore in the later route of first layer, BOT technology can only add in the side of substrate
Work.Therefore embedment Line technology is very limited in the application.
Since conventional embedment Line technology (ETS) can not have core plate applied to existing, and can only be in the side of substrate
Processing, therefore BOT technology can only be used in the side of substrate, while the high density essence of conventional half addition (SAP) technique manufacture
There is biggish binding force defect again when welding in fine rule road and chip.Therefore a kind of novel package substrate construction and manufacture are needed
Method solves problem above.
Summary of the invention
For the technical problems in the prior art, one embodiment of the present of invention, which provides, a kind of two-sided has core plate knot
Structure, comprising: in two-sided at least two layers of the semi-solid preparation substrate having on core plate structure two sides；Partly it is embedded to the semi-solid preparation substrate
In half embedment route；Wherein, the first face of the half embedment route is located at the semi-solid preparation substrate ipsilateral with the route
Surface on, second face opposite with first face of the half embedment route is located at described half ipsilateral with the route
Under the surface for solidifying substrate, a part of the side of the half embedment route is located at the ipsilateral semi-solid preparation base of the route
On the surface of plate, another part of the side of the half embedment route is wrapped up by the semi-solid preparation substrate；And solder mask, institute
It states solder mask and at least partly covers described half surface for being embedded to route, and exposure pad openings.
In an embodiment of the present invention, semi-solid preparation substrate is semi-solid preparation insulating resin sheet.
In an embodiment of the present invention, semi-solid preparation substrate is BT or FR4 prepreg.
In an embodiment of the present invention, this it is two-sided have core plate structure further include be clipped at least two layers semi-solid preparation substrate it
Between one or more layers internal substrate.Internal substrate material and the semi-solid preparation baseplate material are identical or different.The internal layer base
Plate is core plate, and the core plate is obtained by removing the surface copper foil of double face copper.
In an embodiment of the present invention, the depth of half embedment route embedment semi-solid preparation substrate is by semi-solid preparation substrate internal structure
It determines.
It is in an embodiment of the present invention, two-sided that have core plate structure further include one or more conductive through holes and/or inner wire
Road, the conductive through hole is for connecting substrate internal wiring and/or half embedment route.
It is in an embodiment of the present invention, two-sided that have core plate structure further include on the half embedment route by BOT upside-down mounting
The chip of weldering.
Another embodiment of the present invention provides a kind of two-sided manufacturing methods for having core plate structure, comprising: passes through the first pressure
It closes technique and presses semi-solid preparation substrate and surface copper foil on the two sides of internal substrate, wherein first pressing keeps described partly solid
The semi-cured state for changing substrate is constant；Remove the surface copper foil of the semi-solid preparation substrate；In the semi-solid preparation substrate for having removed copper foil
Surface deposit to form the first plating seed layer；The first plating mask and first are lithographically formed on first plating seed layer
Window is electroplated；Plating forms conducting wire on the first plating window；Remove first plating mask；Remove described
First plating seed layer below one plating mask；The conducting wire is pressed by the second process for pressing, wherein described
Second process for pressing is embedded to the conducting wire partly in the semi-solid preparation substrate, and makes the semi-solid preparation material of the semi-solid preparation substrate
Material solidification.
In another embodiment of the present invention, this method further include: form protective film on cured substrate；?
It drills on cured substrate；Deposit the second plating seed layer；It is lithographically formed the second plating mask and the second plating window；Pass through electricity
Filling perforation is plated, for the substrate intraconnection or element installation positioning；Remove second plating mask；Remove second electricity
Plate the second plating seed layer under exposure mask；Solder mask is made in the non-solder region of the semi-solid preparation package substrate upper and lower surface,
And exposure pad openings.
In another embodiment of the present invention, it includes passing through electroless copper shape that protective film is formed on cured substrate
At layers of copper as protective film.
In another embodiment of the present invention, it is electroless copper or sputtering plating kind that deposition, which forms the first plating seed layer,
Sublayer.
In another embodiment of the present invention, chemical-copper-plating process further comprise neutralization, it is acidleach, cleaning, microetch, pre-
Leaching, reduction, changes copper, washing at activation.
In another embodiment of the present invention, the first, second plating seed layer of removal is to dodge erosion method, to reduce etching liquid
Corrosion to conducting wire.
In another embodiment of the present invention, it after making solder mask, is made in half embedment conducting wire and/or pad
Make surface and applies organic protection epithelium OSP, NiAu or NiPdAu.
The two-sided half embedment route high-density base board structure that embodiment through the invention provides has the advantages that
1. two sandwich circuits of the substrate surface of structure of the present invention are the route of half embedment substrate, substrate surface route
It is partially embedded into underfill resin layer insulating layer, is significantly increased with substrate binding force, meet the requirement of BOT flip-chip packaged.
2. the substrate of structure of the present invention can be partially submerged by the cured prepreg of core plate, core plate two sides
Two sandwich circuit of surface in cured prepreg resin and the welding resistance protective layer for being covered on circuit surface are constituted, wherein half is solid
The material for changing piece can be identical with core material, can also be different.
4. it is exposed that two layers half embedment route upper surfaces of the substrate of structure of the present invention are higher by route bottom insulation resin
Surface, rather than the embedment route exposed surface that conventional embedment Line technology is formed is lower than insulating resin surface.Can directly it expire
The BOT flip-chip packaged of sufficient chip.
5. insulating layer resin used in half embedment route of production can be conventional base plate in the substrate of structure of the present invention
Material: ABF, BT prepreg, FR prepreg and other circuit boards resin prepreg.
6. the half of the substrate of structure of the present invention is embedded to the length of embedment of route, i.e., the R value in board structure of the present invention
Size, determined by the material of semi-solid preparation insulating resin.
7. the substrate of structure of the present invention carries out electroless copper to whole surface, carries out before the through-hole processing of substrate
Protection, this is the technique not having in routine techniques.Its effect includes: a) to play in machine drilling to substrate surface resin layer table
The protection in face and route, in case external force is damaged；B) it needs to do de-smear processing after machine drilling, in through-hole, in de-smear process
In, the resin layer on chemical plating copper layer protective substrate surface is not by de-smear solution corrosion.
8. board structure of the present invention is two-sided to be all made of half embedment line construction, therefore two-sided it can be carried out narrow section
BOT flip-chip packaged, packaging density is bigger, and integrated level is higher, and 3D package dimension is smaller.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding component will use identical or class
As mark indicate.
Shown in fig. 1 is the line assumption diagram of the SAP technique manufacture of the prior art.
Fig. 2 shows be the prior art ETS technique manufacture embedment line assumption diagram.
Fig. 3 shows that the present invention half is embedded to the top view and diagrammatic cross-section of line construction.
Fig. 4 shows half embedment route of the present invention and semi-solid preparation board structure size relationship schematic diagram.
Fig. 5 shows two-sided half embedment line construction diagrammatic cross-section according to another embodiment of the invention.
Fig. 6 shows being placed on the inside of two layers of semi-solid preparation substrate as no core plate for another embodiment manufacture of the invention
Board structure diagrammatic cross-section.
Fig. 7 shows that further embodiment manufacture of the present invention has the signal of core plate structure section for the two-sided of BOT encapsulation
Figure.
Fig. 8 shows the two-sided stream that has core plate structure of the further embodiment manufacture for BOT encapsulation according to the present invention
Cheng Tu.
Fig. 9 A to Fig. 9 S shows that further embodiment manufacture according to the present invention has core plate knot for the two-sided of BOT encapsulation
The diagrammatic cross-section of structure process.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can implement in the case where none or multiple specific details each embodiment or with other replacements and/or additional party
Method, material or component implement each embodiment together.In other situations, well known structure, material are not shown or are not described in detail
Or it operates in order to avoid keeping the aspects of various embodiments of the present invention obscure.Similarly, for purposes of explanation, certain number is elaborated
Amount, material and configuration, in order to provide the comprehensive understanding to the embodiment of the present invention.However, the present invention can be in no specific detail
In the case where implement.Further, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the invention.Occur in everywhere in this specification short
Language " in one embodiment " is not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention is described processing step with particular order, however this is only
Facilitate and distinguish each step, and is not the sequencing for limiting each step, it in different embodiments of the invention, can be according to work
Skill is adjusted to adjust the sequencing of each step.
It, can only be in substrate side in order to overcome conventional embedment Line technology (ETS) that can not have core plate applied to existing
It uses, can only be used in substrate side so as to cause BOT technology, while the high density of conventional half addition (SAP) technique manufacture
There is biggish binding force defect problem in fine-line and chip, one embodiment of the present of invention provides one kind in base again when welding
Circuit pack is embedded to the two-sided of following insulating resin by plate two sides core plate structure and its manufacturing method, has core substrate two-sided
On be respectively formed half embedment line construction, in the two-sided of package substrate while realizing route and be partly embedded to structure, increase route with
The binding force of substrate solves the problems, such as that BOT technology can not be two-sided in package substrate while using.
Fig. 3 shows top view and the section signal of half embedment line construction 300 according to an embodiment of the invention
Figure.Half embedment line construction 300 includes semi-solid preparation substrate 310 and half embedment route 320.
In an embodiment of the present invention, semi-solid preparation substrate refers to: after resin adhesive liquid thermally treated (preliminary drying), resin enters
B-stage and manufactured sheeting, semi-solid preparation substrate can soften under heating pressurization, can react solidification after cooling.
The material of semi-solid preparation substrate 310 is semi-solid preparation insulating materials, and can be selected includes glass-fiber-fabric and semi-solid preparation tree in structure
BT the or FR4 prepreg of rouge and resin extender particle, also can be selected structure in without reinforcing material ABF prepreg or
The semi-solid preparation insulating resin sheet of other all circuit board materials.In a specific embodiment of the present invention, the side of semi-solid preparation substrate
Or it is internal optionally include other circuit substrates with play the role of mechanical support or other, while may be used also in other circuit substrates
Improve the packaging efficiency of system with embedding passive element and conducting wire, passive element can be inductance, capacitor, resistance,
Filter, antenna etc..
Half embedment route 320 is placed in the one or both sides of semi-solid preparation substrate 310, wherein being placed in the substrate of package substrate two sides
Structural schematic diagram, as shown in Figure 5.
Half embedment 320 upper surface of route is higher than the upper surface 330 of route bottom semi-solid preparation substrate 310, a part of side
On the upper surface of semi-solid preparation substrate 310 330, another part of side is coated by semi-solid preparation substrate 310.This kind half is embedded to
Line construction be embedded into package substrate insulating resin below, the bottom surface of route and surface are contacted with resin, top
Face, i.e. bonding face are exposed, so that route binding force is improved significantly, avoid in bonding process and after bonding, due to key
Resultant force and encapsulation stress cause route fall off cracking formed integrity problem.In an embodiment of the present invention, half embedment route
320 minimum feature line-spacing is smaller than 15 μm/15 μm, and the thickness of route is in the range of 18 μm to 20 μm.
Fig. 4 shows the size relationship schematic diagram of half embedment route 320 and structure corresponding to semi-solid preparation substrate 310.Half is embedded to
320 total height of route is H, and the height of embedment semi-solid preparation substrate 310 is R, and the line levels for exposing package substrate surface 330 are h,
The size of wherein H > R, H > h, R and h are determined by the resin material of substrate processing technology and semi-solid preparation substrate 310.That is half embedment line
How many line levels embedment 310 resin layer of semi-solid preparation substrate is mainly by route bottom resinous wood in the whole height on road 320
What material determined.Line levels h > 0 is exposed in length of embedment R > 0.
Fig. 5 shows cuing open for the two-sided half embedment line construction 500 formed according to another embodiment of the invention
Face schematic diagram.Two-sided half embedment line construction 500 includes that package substrate 510 and two sides half are embedded to route 520.
Fig. 6 shows that the conduct formed according to still another embodiment of the invention is placed in two layers of semi-solid preparation base without core plate
The diagrammatic cross-section of board structure 600 on the inside of plate.The board structure 600 being placed in as no core plate on the inside of two layers of semi-solid preparation substrate
Including package substrate 610, package substrate 620 and half embedment of 620 inside of half embedment package substrate 610 and package substrate respectively
Route 630.For the one side of half embedment route 630 except package substrate 610, half is embedded to the another side of route 630 in package substrate
Except 620, and the side of half embedment route 630 is partially embedded into semi-solid preparation package substrate 610 and semi-solid preparation encapsulation base respectively
Inside the resin of plate 620.Identical as the other embodiment of the present invention, package substrate 610,620 may include the half of BT or FR4 material
Cured sheets also may include the prepreg of ABF and the semi-solid preparation insulating resin sheet of other all circuit board materials.
Fig. 7 shows that a kind of of formation has core for the two-sided of BOT encapsulation according to still another embodiment of the invention
The diagrammatic cross-section of hardened structure 700.
As shown in fig. 7, thering is core plate structure 700 to include upper layer and lower layer semi-solid preparation insulated with material layer for the two-sided of BOT encapsulation
701 and 702,701 and 702 can be one or more layers semi-solid preparation insulated with material layer under special circumstances herein；In upper layer and lower layer
Half embedment has one or more half embedment routes 703 and 704 respectively on the surface of semi-solid preparation insulated with material layer 701 and 702；Upper and lower
The surface of two layers of semi-solid preparation insulated with material layer 701 and 702 is partially covered by solder mask (green oil layer) 705 and 706 respectively；Upper
The surface of lower two layers of semi-solid preparation material embedment line insulation layer 701 and 702 is laid out respectively several embedment line pads and through-hole
Pad 707 and 708；It is opened on the surface of embedment line pad and via pad 707 and 708, and half embedment route 703 and 704
There are pad openings 709 and 710.
The optional BT or FR4 prepreg of semi-solid preparation insulated with material layer 701 and 702, also can be selected ABF prepreg or other
The semi-solid preparation insulating resin sheet of all circuit board materials, but preferred material is BT or FR4 prepreg.After its function needs to meet
Route is pressed into when continuous high-temperature laminating technique.In addition, as shown in fig. 7, optionally being wrapped between semi-solid preparation insulated with material layer 701 and 702
Containing internal substrate 711, internal substrate 711 optionally includes internal layer circuit and/or embedding passive element to improve system
Packaging efficiency, passive element can be inductance, capacitor, resistance, filter, antenna etc..
Half embedment route 703 and 704 is embedded to route 703 and 704 in the two-sided two sides up and down for having core plate structure 700, half
Outer surface is located at except semi-solid preparation insulated with material layer 701 and 702 surfaces, to expose.Further, since half embedment line
Inside the resin of the buried insulating layer 701 and 702 of road 703 and 704 half, the binding force of route and insulating layer is significantly enhanced, is met
The two-sided BOT of the two-sided subsequent multiple chips for having core plate structure 700, which is encapsulated, to be required.
Further, as shown in fig. 7, two-sided to have the inside of core plate structure 700 selectable include one or more conductive
Through-hole 712 and internal wiring, the conductive through hole 712 is for substrate intraconnection and/or element installation positioning etc..
Below with reference to Fig. 8 and Fig. 9 A to Fig. 9 S, manufacture according to one embodiment of present invention is introduced for the double of BOT encapsulation
There is the process of core plate structure 700 in face.Fig. 8, which shows manufacture according to one embodiment of present invention, has core for the two-sided of BOT encapsulation
The flow chart of hardened structure 700, Fig. 9 A to Fig. 9 S show two-sided having of the manufacture according to one embodiment of present invention for BOT encapsulation
The diagrammatic cross-section of the process of core plate structure 700.
It is solid to press half in core plate two sides low temperature by the way that a double face copper is peelled off surface copper foil as core plate for this method
Change piece and copper foil, does SAP processing high density fine rule road on prepreg surface, then pass through high-temperature laminating for the semi-solid preparation of semi-solid preparation
In the fine rule road indentation prepreg on piece surface, and prepreg is formed by curing embedment route.
Fine rule road is formed using low temperature pressing prepreg surface, route is embedded in prepreg tree using high-temperature laminating
In rouge, and the cured mode of prepreg is formed into two-sided embedment in the route insertion route line face insulating resin of another side
Line construction.
As shown in flow chart 8, firstly, in step 801, preparing double face copper, the structural profile of double face copper shows
It is intended to as shown in Figure 9 A, be made of internal substrate 901 and the copper foil 902 for being covered in 901 upper and lower surface of internal substrate.
Next, in step 802, as shown in Figure 9 B, the surface copper foil 902 of double face copper is removed, internal substrate
901 are used as core plate, and the specific technique that removes can be by including but is not limited to that the techniques such as etching are realized.
Then, in step 803, as shown in Figure 9 C, 904 He of copper foil is pressed in the upper and lower surface low temperature of internal substrate 901
Prepreg 903, wherein copper foil 904 is located at the outermost of the substrate after pressing.Prepreg optional BT or FR4 half is solid
Change piece, ABF prepreg or the semi-solid preparation insulating resin sheet of other all circuit board materials also can be selected, but preferred material is BT
Or FR4 prepreg.Core material can be identical as pre-preg materials, can also be different.Vacuum film pressing can be used in pressing
Machine pressing or the low temperature pressing in laminating machine, it is ensured that prepreg is in semi-cured state.In addition to this kind of method, this field
Technical staff has semi-solid preparation it should be appreciated that can also make to be formed by other prior arts and existing baseplate material
Can, and meet subsequent machining technology mechanical support or its desired semi-solid preparation substrate, it is described above to cannot function as to skill of the present invention
The limitation of art scheme.
Next, in step 804, as shown in fig. 9d, copper foil 904 will be removed, specific removal technique again may be by
The including but not limited to techniques such as etching are realized.
Then, in step 805, as shown in fig. 9e, in the upper layer and lower layer semi-solid preparation for having removed the substrate of surface copper foil 904
The outside deposition of piece 903 forms plating seed layer 905.In usual technique, generally by electroless copper to form copper plating
Seed layer.However it should be appreciated by one skilled in art that but the scope of the present invention is not limited thereto, for example, it is also possible to
Copper plating seed layer or All other routes plating seed layer are formed by other already known processes such as sputterings.In addition, conventional chemical plating
Process for copper include: it is fluffy, except glue, neutralization, acidleach, cleaning, microetch, preimpregnation, activation, reduction, change copper, washing and etc., but this
Invention the method carries out electroless copper on uncured prepreg surface, does not do except glue and fluffy process, only does: neutralize,
Acidleach, microetch, preimpregnation, activation, reduction, changes copper, washing at cleaning.The purpose is to prevent from changing the roughness on prepreg surface,
The binding force between route and prepreg to improve subsequent manufacture.Compared with the chemical-copper-plating process of the prior art, this hair
Bright disclosed chemical-copper-plating process not only simplifies processing step, but also obtains the better structure of performance.
Next, in step 806, as shown in fig. 9f, by photoetching process prepreg 903 plating seed layer
Plating mask 906 and plating window 907 are formed on 905.Specific photoetching process can by dry glue pad pasting or photoresist spin coating,
It is realized again by techniques such as subsequent exposure, developments, to ensure to form plating mask in logicalnot circuit region.
Then, in step 807, as shown in fig. 9g, to the prepreg for forming plating mask 906 and plating window 907
Substrate is electroplated, and conducting wire 908 is formed.In usual technique, generally copper facing, however those skilled in the art should
, it is realized that but the scope of the present invention is not limited thereto, for example, it is also possible to which other conductive materials are electroplated to form conducting wire.
Next, in step 808, as shown in Fig. 9 H, removing plating mask 906.Expose conducting wire 908 and aforementioned
Plating seed layer 905.
Then, in step 809, as shown in figure 91, the seed layer 905 of 906 lower section of plating mask is removed by dodging erosion method.
Sudden strain of a muscle erosion method mainly passes through the parameters such as control etch period and quickly removes seed layer, to reduce the excessive corrosion to conducting wire, tool
Body technology is not described in detail.
In an embodiment of the present invention, the minimum feature line-spacing for the route being formed by the above-mentioned technique is smaller than 15 μm/15 μ
M, the thickness of route is in the range of 18 μm to 20 μm.
Next, in step 810, as shown in Fig. 9 J, the conducting wire 908 that plating is formed is pressed by high-temperature laminating
Partly embedment route 908 is formed in the resin of prepreg 903, prepreg 903 can soften under heating pressurization, at this time by adding
Route 908 is pressed into the resin of prepreg 903 by pressure, and prepreg solidifies after cooling.Half embedment route 908 is embedded to prepreg
The depth of 903 resin depends on the material of the insulating layer of 908 lower section of route.For ABF prepreg, the most of height of route
It is embedded in resin.For BT or FR4 prepreg, the glass-fiber-fabric thickness in prepreg determines route length of embedment.
Such as: the prepreg of 40 μ m thicks is embedded to the depth of resin not less than 5 μm using 1027 glass-fiber-fabrics with a thickness of 30 μm.If
Using 1015 prepreg, it is 10 μm minimum for being embedded to the route depth of resin layer.Length of embedment and line density and route are thick
Degree has relationship.On the one hand resin surface that the effect being specifically embedded to requires the top surface of conducting wire to need to be higher by prepreg, it is another
Aspect needs in the bottom surface of conducting wire and the resin of a surface embedment semi-solid preparation piece.
Meanwhile in step 810, high-temperature laminating technique can be such that prepreg 903 solidifies.
Then, in step 811, as shown in Fig. 9 K, electroless copper is carried out to entire substrate surface, on monolith substrate surface
One layer of copper film 909 is formed, effect is to complete subsequent technique to substrate to protect, this is the technique not having in routine techniques.
The effect of copper film 909 includes: protection a) played in machine drilling to substrate surface resin layer surface and route, in case external force is damaged
Wound；B) it needs to do de-smear processing after machine drilling, in through-hole, during de-smear, chemical plating copper layer protective substrate surface
Resin layer not by de-smear solution corrosion.In a specific embodiment of the present invention, copper film 909 with a thickness of 1 μm.
Next, in step 812, so, being made and entire substrate surface to half embedment route 908 is completed such as Fig. 9 L
The substrate that copper plating film 909 is protected is learned to carry out the manufacture of one or more through-holes 910 and remove de-smear.Via process can be using sharp
Light through-hole, but can also be carried out using other substrate through-hole techniques such as machine drillings.
Then, in step 813, as shown in figure 9m, table in the entire substrate and through-hole 910 that through-hole 910 makes is completed
Face forms plating seed layer 911 by electroless deposition.
Next, in step 814, as shown in Fig. 9 N, by litho pattern formation process substrate plating seed layer
Plating mask 912 is formed on 911.Specific figure formation process can pass through subsequent photoetching, development etc. by dry glue pad pasting again
Technique is realized, to ensure to form plating mask in non through hole filling and/or land.
Then, in step 815, as shown at figure 90, the substrate for forming plating mask 912 is electroplated, copper is formed and fills out
Fill blind hole 913.Copper fills blind hole 913 for substrate intraconnection and/or element installation positioning etc..
Next, in step 816, as shown in Fig. 9 P, removing plating mask 912.Expose conducting wire 908, copper is filled out
Fill blind hole 913 and plating seed layer above-mentioned 911.
Then, in step 817, as shown in figure 9q, pass through the seed layer 911 dodged under erosion method removal plating mask 912.
Next, as shown in figure 9r, making solder mask (green oil in the substrate surface for completing step 817 in step 818
Layer) 914, and the surface system that the copper filling blind hole pad 913 covered in no solder mask (green oil layer) 914 is embedded to conducting wire 908 with half
Make surface coating protection.Coated material is OSP (organic protection epithelium) or NiAu, NiPdAu etc..
So far, a kind of as described in the present invention to there is core plate structure 700 to complete for the two-sided of BOT encapsulation.
Finally, in step 819, as shown in figure 9s, there is core for the two-sided of BOT encapsulation at this using two-sided BOT technology
On half embedment route 908 of the upper and lower surface of hardened structure 700, the direct multiple chips 915 and 916 of BOT flip chip bonding.
The above-mentioned manufacturing method of the present invention, the step from step 802 to step 810, referred to as SESAP (Super Easy Semi
Additive Process) technique, the dielectric resin material and copper foil of the sandwich circuit surface low-temperature that is included pressing semi-solid preparation are protected
The semi-cured state of semi-solid preparation resin is held, after removing copper foil, electroless copper forms plating seed layer on the resin of semi-solid preparation,
Photoetching carries out graphic plating and forms route in seed layer, stripping and after removing the seed layer that dry film covers below, by substrate entirety
Route is pressed into semi-solid preparation resin layer in high temperature press, and resin layer is formed by curing route；After step 810, belong to
General SAP or MSAP technique processing is carried out on cured baseplate material, to form corresponding through-hole, electrode, solder mask
Equal package substrates necessity structure.
The two-sided half embedment route high-density base board structure that embodiment through the invention provides has the advantages that
1. two sandwich circuits of the substrate surface of structure of the present invention are the route of half embedment substrate, substrate surface route
It is partially embedded into underfill resin layer insulating layer, is significantly increased with substrate binding force, meet the requirement of BOT flip-chip packaged.
2. the substrate of structure of the present invention can be partially submerged by the cured prepreg of core plate, core plate two sides
Two sandwich circuit of surface in cured prepreg resin and the welding resistance protective layer for being covered on circuit surface are constituted, wherein half is solid
The material for changing piece can be identical with core material, can also be different.
4. it is exposed that two layers half embedment route upper surfaces of the substrate of structure of the present invention are higher by route bottom insulation resin
Surface, rather than the embedment route exposed surface that conventional embedment Line technology is formed is lower than insulating resin surface.Can directly it expire
The BOT flip-chip packaged of sufficient chip.
5. insulating layer resin used in half embedment route of production can be conventional base plate in the substrate of structure of the present invention
Material: ABF, BT prepreg, FR prepreg and other circuit boards resin prepreg.
6. the half of the substrate of structure of the present invention is embedded to the length of embedment of route, i.e., the R value in board structure of the present invention
Size, determined by the material of semi-solid preparation insulating resin.
7. the substrate of structure of the present invention carries out electroless copper to whole surface, carries out before the through-hole processing of substrate
Protection, this is the technique not having in routine techniques.Its effect includes: a) to play in machine drilling to substrate surface resin layer table
The protection in face and route, in case external force is damaged；B) it needs to do de-smear processing after machine drilling, in through-hole, in de-smear process
In, the resin layer on chemical plating copper layer protective substrate surface is not by de-smear solution corrosion.
8. board structure of the present invention is two-sided to be all made of half embedment line construction, therefore two-sided it can be carried out narrow section
BOT flip-chip packaged, packaging density is bigger, and integrated level is higher, and 3D package dimension is smaller.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present
, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it
Without departing from the spirit and scope of the invention with change.Therefore, the width of the invention disclosed herein and range should not be upper
It states disclosed exemplary embodiment to be limited, and should be defined according only to the appended claims and its equivalent replacement.
Claims (15)
1. one kind is two-sided core plate structure, comprising:
In two-sided at least two layers of the semi-solid preparation substrate having on core plate structure two sides；
Partly it is embedded to the two and half embedment routes in the semi-solid preparation substrate on two-sided two faces for having core plate structure；
Wherein, for the two-sided each surface for having core plate structure, the first face of the half embedment route is located at and institute
On the surface for stating the ipsilateral semi-solid preparation substrate of route, described half is embedded to second face opposite with first face of route
Under the surface of the semi-solid preparation substrate ipsilateral with the route, a part of the side of the half embedment route is located at
On the surface of the ipsilateral semi-solid preparation substrate of the route, another part of the side of the half embedment route is by described half
Solidify substrate package, half is embedded to route total height as H, and the height for being embedded to the semi-solid preparation substrate is R, exposes the semi-solid preparation base
The line levels on the surface of plate are that the size of h, R and h are determined by route bottom resin material；And
Solder mask, the solder mask at least partly cover described half surface for being embedded to route, and exposure pad openings.
2. two-sided as described in claim 1 have core plate structure, which is characterized in that the semi-solid preparation substrate is semi-solid preparation insulation tree
Rouge piece.
3. two-sided as described in claim 1 have core plate structure, which is characterized in that the semi-solid preparation substrate is that BT or FR4 half is solid
Change piece.
4. two-sided as described in claim 1 have core plate structure, which is characterized in that further include being clipped at least two layers of semi-solid preparation
One or more layers internal substrate between substrate.
5. two-sided as claimed in claim 4 have core plate structure, which is characterized in that the internal substrate material and the semi-solid preparation
Baseplate material is identical.
6. two-sided as claimed in claim 4 have core plate structure, which is characterized in that the internal substrate material and the semi-solid preparation
Baseplate material is different.
7. two-sided as claimed in claim 4 have core plate structure, which is characterized in that the internal substrate is core plate, the core plate
It is obtained by removing the surface copper foil of double face copper.
8. two-sided as described in claim 1 have core plate structure, which is characterized in that the half embedment route is embedded to semi-solid preparation base
The depth of plate is determined by semi-solid preparation substrate internal structure.
Two-sided have core plate structure 9. as described in claim 1, which is characterized in that further include one or more conductive through holes and/
Or internal wiring, the conductive through hole is for connecting substrate internal wiring and/or half embedment route.
10. two-sided as described in claim 1 have core plate structure, which is characterized in that further include leading on the half embedment route
Cross the chip of BOT flip chip bonding.
11. a kind of two-sided manufacturing method for having core plate structure, comprising:
Semi-solid preparation substrate and surface copper foil are pressed on the two sides of internal substrate by the first process for pressing, wherein first pressure
It closes and keeps the semi-cured state of the semi-solid preparation substrate constant；
For the semi-solid preparation substrate on each face of internal substrate, the surface copper foil of the semi-solid preparation substrate is removed；
It deposits to form the first plating kind on the surface for the semi-solid preparation substrate for having removed copper foil by electroless copper or sputtering seed layer
Sublayer, chemical-copper-plating process include: neutralization, acidleach, cleaning, microetch, preimpregnation, activation, reduction, change copper, wash, but without removing
Glue and fluffy；
The first plating mask and the first plating window are lithographically formed on first plating seed layer；
Plating forms conducting wire on the first plating window；
Remove first plating mask；
Remove first plating seed layer below first plating mask；
The conducting wire is pressed by the second process for pressing, wherein second process for pressing is embedded to the conducting wire half
In the semi-solid preparation substrate, and make the semi-solid preparation material solidification of the semi-solid preparation substrate.
12. method as claimed in claim 11, which is characterized in that further include:
Protective film is formed on cured substrate；
It drills on cured substrate；
Deposit the second plating seed layer；
It is lithographically formed the second plating mask and the second plating window；
By the way that filling perforation is electroplated, for the substrate intraconnection or element installation positioning；
Remove second plating mask；
Remove the second plating seed layer under second plating mask；
Solder mask, and exposure pad openings are made in the non-solder region of the semi-solid preparation package substrate upper and lower surface.
13. method as claimed in claim 12, which is characterized in that forming protective film on cured substrate includes passing through
It learns copper facing and forms layers of copper as protective film.
14. the method as described in claim 11 or 12, which is characterized in that the first, second plating seed layer of the removal is to dodge
Erosion method, to reduce corrosion of the etching liquid to conducting wire.
15. method as claimed in claim 11, which is characterized in that after making solder mask, in half embedment conducting wire and/or
Surface is made on pad applies organic protection epithelium OSP, NiAu or NiPdAu.
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| CN201710389777.5A CN107146781B (en) | 2017-05-27 | 2017-05-27 | It is a kind of to have core plate structure and its manufacturing method for the two-sided of BOT encapsulation |
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| CN201710389777.5A CN107146781B (en) | 2017-05-27 | 2017-05-27 | It is a kind of to have core plate structure and its manufacturing method for the two-sided of BOT encapsulation |
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| CN107104091B (en) * | 2017-05-27 | 2019-07-05 | 华进半导体封装先导技术研发中心有限公司 | A kind of half is embedded to circuit substrate structure and its manufacturing method |
| CN108770242B (en) * | 2018-06-29 | 2020-10-23 | 沪士电子股份有限公司 | Method for manufacturing rear half-buried circuit of fine circuit on copper foil by corrosion reduction method |
| CN108770243B (en) * | 2018-06-29 | 2020-10-23 | 沪士电子股份有限公司 | Method for electroplating rear half-embedded circuit on copper foil |
| EP4068500A4 (en) * | 2019-12-19 | 2022-11-30 | Huawei Technologies Co., Ltd. | Antenna in package device and wireless communication apparatus |
| CN111970813B (en) * | 2020-08-15 | 2022-03-04 | 宁波甬强科技有限公司 | Wire-implanted circuit board, processing method and processing equipment thereof |
| CN115884494A (en) * | 2021-09-28 | 2023-03-31 | 深南电路股份有限公司 | Circuit embedded method and circuit embedded PCB |
| CN114190002A (en) * | 2021-12-09 | 2022-03-15 | 上达电子（深圳）股份有限公司 | Forming method of semi-embedded thick copper fine circuit of flexible packaging substrate |
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| CN103187311A (en) * | 2011-12-27 | 2013-07-03 | 深南电路有限公司 | Fabrication method of package substrate |
| CN103906371A (en) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | Circuit board having embedded components and manufacturing method thereof |
| CN103945644A (en) * | 2014-05-13 | 2014-07-23 | 张伯平 | Flat circuit board and manufacturing method thereof |
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| CN103187311A (en) * | 2011-12-27 | 2013-07-03 | 深南电路有限公司 | Fabrication method of package substrate |
| CN103906371A (en) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | Circuit board having embedded components and manufacturing method thereof |
| CN103945644A (en) * | 2014-05-13 | 2014-07-23 | 张伯平 | Flat circuit board and manufacturing method thereof |
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Application publication date: 20170908 Assignee: Shanghai Meadville Science & Technology Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2023980035123 Denomination of invention: A double-sided cored board structure and manufacturing method for BOT packaging Granted publication date: 20190830 License type: Common License Record date: 20230427 |
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