CN107146760A - FET, its preparation method and application based on topological insulator nano wire - Google Patents
FET, its preparation method and application based on topological insulator nano wire Download PDFInfo
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- CN107146760A CN107146760A CN201710329636.4A CN201710329636A CN107146760A CN 107146760 A CN107146760 A CN 107146760A CN 201710329636 A CN201710329636 A CN 201710329636A CN 107146760 A CN107146760 A CN 107146760A
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- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 14
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- 229910052797 bismuth Inorganic materials 0.000 claims description 13
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- 238000005566 electron beam evaporation Methods 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 13
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- 239000002184 metal Substances 0.000 claims description 5
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- 238000005520 cutting process Methods 0.000 claims description 4
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- 238000010438 heat treatment Methods 0.000 claims description 2
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- 240000007594 Oryza sativa Species 0.000 claims 1
- FBGGJHZVZAAUKJ-UHFFFAOYSA-N bismuth selenide Chemical compound [Se-2].[Se-2].[Se-2].[Bi+3].[Bi+3] FBGGJHZVZAAUKJ-UHFFFAOYSA-N 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 abstract description 6
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- 241001269238 Data Species 0.000 description 1
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
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- 229910052714 tellurium Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention provides the FET based on topological insulator nano wire, its preparation method and application, the FET that the present invention is provided can reduce background noise, sufficiently high signal to noise ratio is obtained, will be lower than the FET based on silicon or aluminum gallium arsenide in the noise of MHz frequency ranges.
Description
Technical field
The invention belongs to semiconductor applications, and in particular to a kind of FET based on topological insulator nano wire, and its
Preparation method and application.
Background technology
FET is component most basic in electronic integrated circuit so far, controls to flow through by field effect
Carrier concentration in device, so that the size of control electric current.FET is widely used in amplifier, gate and memory cell
Deng.
So far, FET is by silicon, the semi-conducting material manufacturing such as aluminum gallium arsenide.Common structure is source class, and drain connects
Connect the gate electrode of certain carrier type in the conducting channel and control raceway groove of source and drain level.By adjusting grid voltage, it is possible to
Realize the closing of raceway groove and connect.FET can be for making various types of amplifiers, can for signal to be amplified to
The stage of measurement.
In the minimum signal measurement such as quantum calculation, measured signal is typically some signal amplitudes very small single quantum
State, such as single electron state.Measured signal needs further amplification, could be by frequency spectrograph, lock phase or vector network analyzer etc.
Instrument is recognized.The material that existing small signal amplifier is used typically silicon, or the semi-conducting material such as aluminum gallium arsenide.This kind of material
The electronic device made is inherently by certain noise.So in actual use, the noise of measured signal may and field-effect
The background noise of itself is managed to be within a magnitude.
The content of the invention
Therefore, it is an object of the invention to overcome defect of the prior art there is provided a kind of FET of low noise, and
Its preparation method and application.
Before technical scheme is illustrated, term used herein is defined as follows：
Term " PMMA " refers to：Polymethyl methacrylate；
Term " MIBK " refers to：Methylisobutylketone；
Term " dimensional electron gas " refers to：The electronic system that electronics can only be moved freely along in unidimensional scale.
To achieve the above object, the first aspect of the present invention provides a kind of preparation method of topological insulator nano wire,
The preparation method comprises the following steps：
(1) silicon chip of the cutting cleaning with surface oxide layer；
(2) nano-Au films are deposited in electron beam evaporation on the silicon chip that step (1) is obtained；With
(3) the grown above silicon bismuth selenide for the being coated with gold thin film topology insulation obtained using vapour deposition process in step (2)
Body nano wire.
Described preparation method according to a first aspect of the present invention, wherein, in step (2), the thickness of the nano-Au films
For 1~5 nanometer, preferably 2 nanometers.
Preferably, in step (3)：Before the nanowire growth process, 500~1000 DEG C of elevated temperature heating stages (2) obtain
Silicon chip to the nano-Au films melt agglomerate, it is preferable that the heating-up temperature be 600 DEG C；And/or
The growth temperature of the nano wire is 480~600 DEG C, most preferably preferably 500~550 DEG C, 530 DEG C；It is described
The growth time of nano wire is 10~60 minutes, most preferably preferably 20~40 minutes, 30 minutes.
The second aspect of the present invention provides a kind of topological insulator nano wire, and the topological insulator nano wire is by basis
Method described in first aspect present invention is prepared.
The third aspect of the present invention provides a kind of FET, and the FET includes：
The topological insulator nano wire that according to a first aspect of the present invention prepared by methods described；
Doped silicon substrate；
Silica；
Source electrode；
Drain electrode；
Roof door；With
Side door.
The fourth aspect of the present invention provides a kind of for preparing FET described according to a third aspect of the present invention
Method, the preparation method comprises the following steps：
(1) described method prepares bismuth selenide topological insulator nano wire according to a first aspect of the present invention；
(2) cutting is with surface insulation oxide layer, the silicon chip that bottom is conductiving doping silicon, to the silicon chip insulating surfaces gluing
And hot plate baking；
(3) silicon chip after the gluing obtained to step (2) carries out electron beam exposure and development, and deposited by electron beam evaporation is deposited
Nano-Au films, obtain the silicon chip with coordinate array after removing photoresist；
(4) selenizing bismuth nano-wire prepared by step (1) is transferred on the silicon chip that step (3) is obtained using Electrostatic Absorption,
And shoot the photo for including the golden coordinate cross of at least two horizontal directions；
(5) a face gluing and hot plate baking of the silicon chip obtained to step (4) with nano wire；
(6) source-drain electrode and side door and roof door of FET are designed on the basis of the photo that step (4) is shot, and to electricity
Polar region domain carries out beamwriter lithography, exposure source-drain electrode and side door region, develops and cleans；
(7) nanometer metal palladium and nanogold is deposited in the silicon chip electron beam evaporation for obtaining step (6), removes photoresist；
(8) a face gluing of the silicon chip for obtaining step (7) with nano wire and hot plate baking, electronics is carried out to electrode zone
Beam photoetching, exposure roof door region, develops and cleans；
(9) sull and nanogold is deposited in the silicon chip electron beam evaporation for obtaining step (8), removes photoresist, must show up effect
Ying Guan；With
(10) FET that testing procedure (9) is obtained.
Preferably, step (2), (5), gluing process described in (8) apply PMMA glue using photoresist spinner, and rotating speed is 3000~
5000 revs/min, preferably 4000 revs/min；Hot plate baking temperature described in step (2) is 150~200 DEG C, baking time
For 1~20 minute, it is preferable that baking temperature is 180 DEG C, baking time is 2 minutes；Hot plate described in step (5) and (8) is toasted
Temperature is 100~150 DEG C, and baking time is 10~30 minutes, it is preferable that baking temperature is 120 DEG C, and baking time is 20 points
Clock.
Preferably, nano-Au films thickness described in step (3) is 10~50 nanometers, preferably 20 nanometers；In step (7)
The Technique of Nano Pd thickness is 1~5 nanometer, and nanogold thickness is 50~100 nanometers, it is preferable that Technique of Nano Pd thickness is 2 nanometers, is received
The golden thickness of rice is 70 nanometers；Oxide film material is selected from described in step (9)：Aluminum oxide and/or magnesia, thickness are 1~3
Nanometer, nanogold thickness is 50~100 nanometers；Preferably, oxide film material is aluminum oxide, and thickness is 2 nanometers, nanogold
Thickness is 70 nanometers.
The fifth aspect of the present invention provides second party prepared by methods described according to a first aspect of the present invention or of the present invention
Application of the topological insulator nano wire in FET is prepared described in face.
The sixth aspect of the present invention provides described in the third aspect present invention or side according to a fourth aspect of the present invention
The application of FET prepared by method in electronic integrated circuit is prepared.
In order to further reduce the background noise of FET, sufficiently high signal to noise ratio is obtained, the present inventor utilizes topology
In insulator nanowire surface state, the impurity scattering that electronics is subject to can repressed feature, made low noise FET.This
The noise of class FET MHz frequency ranges is lower than the FET based on silicon or aluminum gallium arsenide.
Topological insulator nano wire is referred to topology protection surface state, the ternary or two of tellurium, selenium and bismuth composition
First compound.Source includes but is not limited to direct growth nano wire, and obtains using physics, chemistry after topological insulator film
Method etching is obtained, and diameter is less than 100 nanometers of wire topological insulator, or is utilized on topological insulator Membranous Foundations
The dimensional electron gas obtained after local gate electrode emptying electronics.
The FET made based on topological insulator nano wire, it is raceway groove to refer mainly to using topological insulator nano wire,
Other metals are as source-drain electrode, using insulators such as air, oxides as the dielectric between grid and raceway groove, with other metals
It is used as the FET of grid.
The FET of the present invention can have but be not limited to following beneficial effect：
1st, the FET that the present invention is provided can reduce background noise, obtain sufficiently high signal to noise ratio.
2nd, the FET that provides of the present invention in the noise of MHz frequency ranges than the FET based on silicon or aluminum gallium arsenide
It is low.
Brief description of the drawings
Hereinafter, embodiment of the present invention is described in detail with reference to accompanying drawing, wherein：
Fig. 1 shows the topological insulator nanometer wire field effect tube top view that the present invention is provided.Received comprising topological insulator
Rice noodles, source electrode, drain electrode, roof door, side door, device is square on silica.
Fig. 2 shows the topological insulator nanometer wire field effect tube of the invention provided along nano wire long axis direction profile.
Fig. 3 shows the photo of the selenizing bismuth nano-wire on the silicon chip that the embodiment of the present invention 1 is provided.
Fig. 4 is shown in the embodiment of the present invention 4, under an optical microscope, with 1000 times of multiplication factor, in coordinate array
In the range of find diameter and be less than 100 nanometers, length is more than 10 microns of selenizing bismuth nano-wire.One is clapped after finding and includes at least two
The picture A of the golden coordinate cross of individual horizontal direction.
Fig. 5 shows that selenizing bismuth nano-wire shot noise is surveyed under the FET temperature 10mK that the embodiment of the present invention 4 is provided
Spirogram.
Embodiment
The present invention is further illustrated below by specific embodiment, it should be understood, however, that, these embodiments are only
It is used for specifically describing in more detail, and is not to be construed as limiting the present invention in any form.
This part carries out general description to the material and test method that are arrived used in present invention experiment.Although being
It is it is known in the art that still the present invention still uses up herein to realize many materials used in the object of the invention and operating method
It may be described in detail.It will be apparent to those skilled in the art that within a context, if not specified, material therefor of the present invention and behaviour
It is well known in the art as method.
The reagent and instrument used in following examples is as follows：Reagent：
Isopropanol, MIBK, acetone is purchased from Chemical Reagent Co., Ltd., Sinopharm Group；
Bismuth selenide source, palladium, gold, aluminum oxide, magnesia is purchased from AlfaAesar company；
PMMA electron beam resists are purchased from ALLRESIST companies, model 950K.
Silicon chip, purchased from SVM companies；
Quartz ampoule is purchased from Hefei Ke Jing Materials Technology Ltd..
Instrument：
Chemical vapor deposition CVD growth system, purchased from Hefei Ke Jing Materials Technology Ltd., model GSL-1100X-
XX-S(UL)。
Electron beam evaporation deposition machine, purchased from Liang Jie Science and Technology Ltd.s, model LJ-550E；
Photoresist spinner, purchased from Ming Ao Electron Material Co., Ltd of Shenzhen, model KW-4A types；
Electron beam exposure apparatus, purchased from German Raith companies, model Raith150；
Light microscope, purchased from NIKON, model eclipse lv150；
Dilution refrigeration machine system, purchased from Oxford company, model Triton 200；
DC source table, purchased from Keithley companies, model K2636A；
Frequency spectrograph, purchased from Hewlett-Packard, model 89410A.
Embodiment 1
The present embodiment is used for the preparation method for illustrating the nano wire that the present invention is provided.
1. a silicon chip with surface oxide layer is cut into slices, and is cleaned up by standard technology, acetone ultrasound is placed five minutes,
Place isopropanol ultrasound five minutes, place after new isopropanol is cleaned five minutes and dry up, obtain wide about 1 centimetre, be about 4 centimetres
Silicon chip A.
2. 2 nano-Au films are deposited in electron beam evaporation.
3. grow topological insulator nano wire using vapour deposition process.900 degrees Celsius of purging system quartz ampoules of high temperature first,
Begin to speak to be put into the silicon chip with gold thin film after cooling to quartz ampoule middle.600 degrees Centigrade of high temperature 15 minutes so that gold
Agglomerate after film melts, obtains being attached to the gold nano grain of silicon chip surface.
4. being put into high-purity (99.999%) bismuth selenide source after cooling, bismuth selenide source position is quartz ampoule middle, silicon chip position
It is set to the larger region of quartz ampoule terminal temperature gradient.It is 5 with ratio：1 argon gas/hydrogen mixed gas cleaning quartz ampoule five times.
Regulation mixed gas flow is argon gas 50sccm, hydrogen 10sccm, and gas pressure intensity is 17 supports in quartz ampoule.It is brought rapidly up to 530 taking the photograph
Family name's degree starts growth.Growth time 30 minutes.Growth terminates rear natural cooling, obtains diameter less than 100 nanometers, 10 microns of length
Selenizing bismuth nano-wire above, as shown in Figure 3.
Embodiment 2
The present embodiment is used for the preparation method for illustrating the nano wire that the present invention is provided.
1. a silicon chip with surface oxide layer is cut into slices, and is cleaned up by standard technology, acetone ultrasound is placed five minutes,
Place isopropanol ultrasound five minutes, place after new isopropanol is cleaned five minutes and dry up, obtain wide about 1 centimetre, be about 4 centimetres
Silicon chip A.
2. 5 nano-Au films are deposited in electron beam evaporation.
3. grow topological insulator nano wire using vapour deposition process.900 degrees Celsius of purging system quartz ampoules of high temperature first,
Begin to speak to be put into the silicon chip with gold thin film after cooling to quartz ampoule middle.900 degrees Centigrade of high temperature 5 minutes so that gold
Agglomerate after film melts, obtains being attached to the gold nano grain of silicon chip surface.
4. being put into high-purity (99.999%) bismuth selenide source after cooling, bismuth selenide source position is quartz ampoule middle, silicon chip position
It is set to the larger region of quartz ampoule terminal temperature gradient.It is 5 with ratio：1 argon gas/hydrogen mixed gas cleaning quartz ampoule five times.
Regulation mixed gas flow is argon gas 50sccm, hydrogen 10sccm, and gas pressure intensity is 17 supports in quartz ampoule.It is brought rapidly up to 480 taking the photograph
Family name's degree starts growth.Growth time 60 minutes.Growth terminates rear natural cooling, obtains diameter less than 100 nanometers, 10 microns of length
Selenizing bismuth nano-wire above.
Embodiment 3
The present embodiment is used for the preparation method for illustrating the nano wire that the present invention is provided.
1. a silicon chip with surface oxide layer is cut into slices, and is cleaned up by standard technology, acetone ultrasound is placed five minutes,
Place isopropanol ultrasound five minutes, place after new isopropanol is cleaned five minutes and dry up, obtain wide about 1 centimetre, be about 4 centimetres
Silicon chip A.
2. 5 nano-Au films are deposited in electron beam evaporation.
3. grow topological insulator nano wire using vapour deposition process.900 degrees Celsius of purging system quartz ampoules of high temperature first,
Begin to speak to be put into the silicon chip with gold thin film after cooling to quartz ampoule middle.500 degrees Centigrade of high temperature 30 minutes so that gold
Agglomerate after film melts, obtains being attached to the gold nano grain of silicon chip surface.
4. being put into high-purity (99.999%) bismuth selenide source after cooling, bismuth selenide source position is quartz ampoule middle, silicon chip position
It is set to the larger region of quartz ampoule terminal temperature gradient.It is 5 with ratio：1 argon gas/hydrogen mixed gas cleaning quartz ampoule five times.
Regulation mixed gas flow is argon gas 50sccm, hydrogen 10sccm, and gas pressure intensity is 17 supports in quartz ampoule.It is brought rapidly up to 600 taking the photograph
Family name's degree starts growth.Growth time 10 minutes.Growth terminates rear natural cooling, obtains diameter less than 100 nanometers, 10 microns of length
Selenizing bismuth nano-wire above.
Embodiment 4
The present embodiment is used for the preparation method for illustrating the FET that the present invention is provided.
1. the method according to embodiment 1 prepares silicon chip A.
2. have surface insulation oxide layer, bottom for conductiving doping silicon silicon chip cut into slices, about 5 millimeters of square of size.
3. with the speed of 4000 revs/min of photoresist spinner, it is about 200 nanometers that a layer thickness is covered in silicon chip insulating surfaces
PMMA electron beam resists.Whirl coating cleans silicon chip back side after finishing with acetone.And by silicon chip and PMMA glue with 180 degrees Celsius of heat
Plate is toasted 2 minutes.
4. utilizing electron beam exposure, the coordinate array of 4 millimeters of square of total size is engraved.Coordinate mark between at intervals of
0.1 millimeter.
5. it is isopropanol with ratio：MIBK=3：1 mixed liquor development, developing time is 1 minute.Develop after terminating with different
Propyl alcohol is cleaned 1 minute.
6. 20 nanogold are deposited in deposited by electron beam evaporation.Evaporation uses the remaining PMMA of acetone solution after finishing, and obtains with seat
Mark the silicon chip B of array.
7. one sides of a silicon chip B with array is tipped upside down on silicon chip A, the bismuth selenide on silicon chip A is set to receive using Electrostatic Absorption
Rice noodles are transferred on silicon chip B.
8. under an optical microscope, with 1000 times of multiplication factor, searching diameter is received less than 100 in the range of coordinate array
Rice, length is more than 10 microns of selenizing bismuth nano-wire.One is clapped after finding and includes the golden coordinate cross of at least two horizontal directions
Picture A, as shown in Figure 4.
9. using photoresist spinner, 4000 revs/min of speed covers one layer of PMMA, whirl coating in one sides of the silicon chip B with nano wire
The acetone cleaning silicon chip back side is used after finishing.And toast silicon chip and PMMA glue 20 minutes with 120 degrees Celsius of hot plate.
10. a picture A imported into electron-beam exposure system and carried in mapping software, scale and rotate to two golden coordinates
Array level, spacing is 100.The source-drain electrode of device, side door and roof door are designed on the basis of the photo.
11. beamwriter lithography, exposure source-drain electrode and side door region are carried out to electrode zone using electron beam exposure.
12. use isopropanol：MIBK=3：1 mixed liquor development, developing time is 1 minute.Development uses isopropanol after terminating
Cleaning 1 minute.
13. a silicon chip B is put into electronic beam evaporation vacuum intracavitary, original position is cleaned 20 seconds with argon plasma.
14. plating 2 nanometer metal palladiums, 70 nanogold of rear plating, evaporation uses the remaining PMMA of acetone solution after finishing.
15. using photoresist spinner, 4000 revs/min of speed covers one layer of PMMA, whirl coating in one sides of the silicon chip B with nano wire
The acetone cleaning silicon chip back side is used after finishing.And toast silicon chip and PMMA glue 20 minutes with 120 degrees Celsius of hot plate.
16. beamwriter lithography, exposure roof door region are carried out to electrode zone using electron beam exposure.
17. use isopropanol：MIBK=3：1 mixed liquor development, developing time is 1 minute.Development uses isopropanol after terminating
Cleaning 1 minute.
18. a silicon chip B is put into electronic beam evaporation vacuum intracavitary, original position is cleaned 20 seconds with argon plasma.
19. the aluminum oxide film of 2 nanometers of plating, 70 nanogold of rear plating, evaporation uses the remaining PMMA of acetone solution after finishing.
To in silica surface, using topological insulator nano wire as the FET of raceway groove.
20. test.The contact resistance of source-drain electrode and nano wire should be less than 1 kilohm.Should between side door and nano wire
Insulation.Any one in side door, bottom door and doped silicon is not connected with source electrode, drain electrode or nano wire.Side door, bottom door and mixes
Miscellaneous silicon insulate two-by-two.
Multiple FETs can be made on same silicon chip simultaneously, if source-drain electrode between different FET and
Side door is not all connected mutually.Carrier concentration in all FET raceway grooves is adjusted as global bottom door with doped silicon.Respectively
Side door in individual FET can individually adjust the carrier concentration in the FET raceway groove.Realize source-drain electrode conducting and
Shut-off.
Embodiment 5
The present embodiment is used for the preparation method for illustrating the FET that the present invention is provided.
The present embodiment is particularly limited to condition and operation is outer, affected and condition such as embodiment in remaining all step except following
Described in 4, wherein
Hot plate baking temperature is 150 degrees Celsius in step 3, and baking time is 10 minutes；
In step 6, the thickness of nanogold is 10 nanometers；
Hot plate baking temperature is 120 degrees Celsius in step 9, and baking time is 30 minutes；
Technique of Nano Pd thickness described in step 14 is 1 nanometer, and nanogold thickness is 50 nanometers；
Hot plate baking temperature is 100 degrees Celsius in step 15, and baking time is 30 minutes；
The magnesia film and 100 nanogold of 1 nanometer of plating in step 19.
Embodiment 6
The present embodiment is used for the preparation method for illustrating the FET that the present invention is provided.
The present embodiment is particularly limited to condition and operation is outer, affected and condition such as embodiment in remaining all step except following
Described in 4, wherein
Hot plate baking temperature is 200 degrees Celsius in step 3, and baking time is 1 minute；
In step 6, the thickness of nanogold is 50 nanometers；
Hot plate baking temperature is 150 degrees Celsius in step 9, and baking time is 10 minutes；
Technique of Nano Pd thickness described in step 14 is 5 nanometers, and nanogold thickness is 100 nanometers；
Hot plate baking temperature is 150 degrees Celsius in step 15, and baking time is 10 minutes；
3 nano oxidized aluminium films and 50 nanogold are plated in step 19.
Test example 1
This test example is used for the effect for illustrating the FET that the present invention is provided.
Test makes to drop at a temperature of FET using the dilution refrigeration machine systems of Triton 200 of Oxford company
10mK, DC bias supplies are provided using the K2636A DC sources table of Keithley companies.The shot-noise current of FET
Signal is converted to by the LC oscillation circuits that a resonant frequency is 2.6MHz after voltage signal, and amplifier is made by oneself by two-stage
Amplification, is input to the 89410A frequency spectrograph gathered datas of Hewlett-Packard.The data gathered take 2.6MHz resonance peak to pass through
The shot noise size of FET is can obtain after mathematical conversion.
It is remote with the shot noise background within the FET 10MHz of the method for the embodiment of the present invention 4 making by test
Less than the Noise Background based on conventional semiconductors such as silicon, aluminum gallium arsenides.Fig. 5 is selenizing bismuth nano-wire shot noise survey under temperature 10mK
Spirogram, transverse axis is bias current, and the longitudinal axis is shot noise.Tiltedly straight solid line is the expection noise of such as silicon, aluminum gallium arsenide conventional material
Value, circle data and curves are selenizing bismuth nano-wire shot noise value, and dash area represents repressed in selenizing bismuth nano-wire and made an uproar
Sound.
Although present invention has been a certain degree of description, it will be apparent that, do not departing from the spirit and scope of the present invention
Under the conditions of, the appropriate change of each condition can be carried out.It is appreciated that the invention is not restricted to the embodiment, and it is attributed to right
It is required that scope, it includes the equivalent substitution of each factor.
Claims (10)
1. a kind of preparation method of topological insulator nano wire, it is characterised in that the preparation method comprises the following steps：
(1) silicon chip of the cutting cleaning with surface oxide layer；
(2) nano-Au films are deposited in electron beam evaporation on the silicon chip that step (1) is obtained；With
(3) received using vapour deposition process in the grown above silicon bismuth selenide topological insulator for being coated with gold thin film that step (2) is obtained
Rice noodles.
2. preparation method according to claim 1, it is characterised in that in step (2), the thickness of the nano-Au films is
1~5 nanometer, preferably 2 nanometers.
3. preparation method according to claim 1, it is characterised in that in step (3)：
Before the nanowire growth process, the silicon chip that 500~1000 DEG C of elevated temperature heating stages (2) obtain to the nano-Au films
Melt agglomerate, it is preferable that the heating-up temperature is 600 DEG C；And/or
The growth temperature of the nano wire is 480~600 DEG C, most preferably preferably 500~550 DEG C, 530 DEG C；The nanometer
The growth time of line is 10~60 minutes, most preferably preferably 20~40 minutes, 30 minutes.
4. a kind of topological insulator nano wire, it is characterised in that the topological insulator nano wire is by according to claims 1 to 3
Method described in any one is prepared.
5. a kind of FET, it is characterised in that the FET includes：
The topological insulator nano wire prepared according to any one of claims 1 to 3 methods described；
Doped silicon substrate；
Silica；
Source electrode；
Drain electrode；
Roof door；With
Side door.
6. a kind of method for preparing FET according to claim 5, it is characterised in that the preparation method bag
Include following steps：
(1) bismuth selenide topological insulator nano wire is prepared according to the method described in claim 1；
(2) cutting is with surface insulation oxide layer, the silicon chip that bottom is conductiving doping silicon, to the silicon chip insulating surfaces gluing and heat
Plate is toasted；
(3) silicon chip after the gluing obtained to step (2) carries out electron beam exposure and development, and deposited by electron beam evaporation evaporation nanometer
Gold thin film, obtains the silicon chip with coordinate array after removing photoresist；
(4) selenizing bismuth nano-wire prepared by step (1) is transferred on the silicon chip that step (3) is obtained using Electrostatic Absorption, and clapped
Take the photograph the photo for including the golden coordinate cross of at least two horizontal directions；
(5) a face gluing and hot plate baking of the silicon chip obtained to step (4) with nano wire；
(6) source-drain electrode, side door and the roof door of FET are designed on the basis of the photo that step (4) is shot, and to electrode district
Domain carries out beamwriter lithography, exposure source-drain electrode and side door region, develops and cleans；
(7) nanometer metal palladium and nanogold is deposited in the silicon chip electron beam evaporation for obtaining step (6), removes photoresist；
(8) a face gluing of the silicon chip for obtaining step (7) with nano wire and hot plate baking, electron beam light is carried out to electrode zone
Carve, exposure roof door region is developed and cleaned；
(9) sull and nanogold is deposited in the silicon chip electron beam evaporation for obtaining step (8), removes photoresist, obtains FET；
With
(10) FET that testing procedure (9) is obtained.
7. method according to claim 6, it is characterised in that step (2), (5), gluing process described in (8) are using getting rid of
Glue machine applies PMMA glue, and rotating speed is 3000~5000 revs/min, preferably 4000 revs/min；Hot plate described in step (2) is toasted
Temperature is 150~200 DEG C, and baking time is 1~10 minute, it is preferable that baking temperature is 180 DEG C, and baking time is 2 minutes；
Hot plate baking temperature described in step (5) and (8) is 100~150 DEG C, and baking time is 10~30 minutes, it is preferable that baking temperature
Spend for 120 DEG C, baking time is 20 minutes.
8. method according to claim 6, it is characterised in that nano-Au films thickness described in step (3) is 10~50
Nanometer, preferably 20 nanometers；Technique of Nano Pd thickness described in step (7) is 1~5 nanometer, and nanogold thickness is 50~100 nanometers,
Preferably, Technique of Nano Pd thickness is 2 nanometers, and nanogold thickness is 70 nanometers；Oxide material is selected from described in step (9)：Oxidation
Aluminium and/or magnesia, thickness are 1~3 nanometer, and nanogold thickness is 50~100 nanometers；Preferably, oxide film material is
Aluminum oxide, thickness is 2 nanometers, and nanogold thickness is 70 nanometers.
9. topological insulator nanometer being prepared according to any one of claims 1 to 3 methods described or according to claim 4
Application of the line in FET is prepared.
10. FET that is described in claim 5 or being prepared according to any one of claim 5 to 8 methods described is preparing electricity
Application in sub- integrated circuit.
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