CN107134979B

CN107134979B - RC oscillator

Info

Publication number: CN107134979B
Application number: CN201710265726.1A
Authority: CN
Inventors: 陈景阔
Original assignee: IPGoal Microelectronics Sichuan Co Ltd
Current assignee: IPGoal Microelectronics Sichuan Co Ltd
Priority date: 2017-04-21
Filing date: 2017-04-21
Publication date: 2020-06-16
Anticipated expiration: 2037-04-21
Also published as: CN107134979A

Abstract

The invention discloses an RC oscillator, which comprises a first phase inverter, a second phase inverter, a buffer and a resistance circuit, wherein the output end of the first phase inverter is connected with the input end of the second phase inverter; wherein, it also includes decoder, basic capacitor and 2^N-1 capacitor calibration units, wherein two ends of the basic capacitor are respectively connected with the input end of the first inverter and the output end of the second inverter, each capacitor calibration unit is respectively connected with the input end of the first inverter and the output end of the second inverter, an external N-bit binary control word is input into the control end of the decoder, and two output ends of the decoder output two groups of 2^N-1 bit of binary control word and each input to a respective capacitance calibration unit. The RC oscillator has accurate capacitance value and does not change along with temperature, voltage and process; the resistance value does not change along with the temperature, and the frequency of the output clock is accurately locked near the design frequency.

Description

RC oscillator

Technical Field

The invention relates to the field of integrated circuits, in particular to an RC oscillator.

Background

The conventional RC oscillator circuit shown in fig. 1 includes two inverters INV1 and INV2, a buffer BUF, a resistor R and a capacitor C, which are specifically connected as shown in fig. 1. When the whole circuit starts to operate, that is, when the operation time t is 0, it is assumed that the voltage at the node Va is 0, the voltage at the node Vb is 1, and the voltage at the node Vc is 0. During time T1 (i.e., 0< T < T1), node Vb charges capacitor C through resistor R, and the voltage at node Va increases; when T is T1, the voltage at node Va reaches the inverse voltage of inverter INV1, and inverter INV1 inverts; then, the voltage of the node Vb is inverted to 0, and the voltage at the node Vc is inverted to 1; when T1< T < T2, the node Va discharges the capacitor C through the resistor R, so that the voltage at the node Va is reduced; when T is T2, the inverter INV1 inverts, the node Vb voltage inverts to 1, the inverter INV2 inverts, and the node Vc voltage is 0; when T is T3, the voltage at the node Vb is inverted again, the voltage at the node Vc is inverted, and the process is repeated, and the specific waveform is shown in fig. 2; and outputs the clock through the buffer BUF. CLK.

In the RC oscillator shown in fig. 1, the period t of the clock CLK is RC — ln [ (1+ Ksw) (2-Ksw)/(Ksw — Ksw) ], where Ksw is the ratio of the voltage at which the inverter starts to invert to the power supply voltage) generally takes 0.5, and after simplification, t is RC — ln9 — 2.2RC, and the frequency f of the clock CLK is 1/t — 1/(2.2 RC). The resistor R is generally a P + poly (P-type polysilicon) model, and the capacitor C is a MOS capacitor. The polysilicon resistor changes by +/-10% along with temperature, voltage and process angle, the MOS capacitor changes by more than +/-10% along with the voltage, the temperature and the process angle, and the frequency of the CLK clock is deviated from the deviation of the design frequency by +/-20% due to the delay change introduced by an inverter, a buffer and the like.

Therefore, there is a need to provide an improved RC oscillator to overcome the above-mentioned drawbacks.

Disclosure of Invention

The invention aims to provide an RC oscillator, which has accurate capacitance value and does not change along with temperature, voltage and process; the resistance value does not change along with the temperature, the deviation introduced by the MOS device is eliminated, and the frequency of the output clock is accurately locked near the design frequency.

In order to achieve the above object, the present invention provides an RC oscillator, including a first inverter, a second inverter, a buffer and a resistor circuit, wherein an output terminal of the first inverter is connected to an input terminal of the second inverter, an output terminal of the second inverter is connected to an input terminal of the buffer, and the resistor circuit is connected between the input terminal and the output terminal of the first inverter; the RC oscillator further comprises a capacitance calibration circuit, the capacitance calibration circuit is connected between the input end of the first inverter and the output end of the second inverter, and the capacitance calibration circuit comprises a decoder, a basic capacitor and a capacitor 2^N-1 capacitor calibration units, wherein two ends of the basic capacitor are respectively connected with an input end of a first inverter and an output end of a second inverter, each capacitor calibration unit is respectively connected with an input end of the first inverter and an output end of the second inverter, an external N-bit binary control word is input into a control end of the decoder, and two output ends of the decoder output two groups of 2^N-1 bit binary control word, and two sets of said 2^N-1 bit binary control words are all input to each capacitance calibration unit to control each capacitance calibration unit to calibrate the capacitance, N being a natural number greater than 1.

Preferably, the resistance circuit includes a first resistance and a second resistance; one end of the first resistor is connected with the input end of the first phase inverter, the other end of the first resistor is connected with one end of the second resistor, and the other end of the second resistor is connected with the output end of the first phase inverter.

Preferably, the first resistor is a non-silicide P-type polysilicon resistor, and the second resistor is a silicide P-type polysilicon resistor.

Preferably, the first resistor is a silicide P-type polysilicon resistor, and the second resistor is a non-silicide P-type polysilicon resistor.

Preferably, each of the capacitance calibration units has identical structural features, and each of the capacitance calibration units includes a first field effect transistor, a second field effect transistor and a step capacitor, one output end of the decoder is connected to the gate of the first field effect transistor, and the other output end of the decoder is connected to the gate of the second field effect transistor; the source electrode of the first field effect tube and the drain electrode of the second field effect tube are respectively connected with the input end of the first phase inverter, the drain electrode of the first field effect tube and the source electrode of the second field effect tube are respectively connected with one end of the stepping capacitor, the other end of the stepping capacitor is connected with the output end of the second phase inverter, the substrate of the first field effect tube is grounded, and the substrate of the second field effect tube is connected with an external power supply.

Preferably, the first field effect transistor is an N-type field effect transistor, and the second field effect transistor is a P-type field effect transistor.

Preferably, the 2 nd output of an output terminal of the decoder ^N2 control words input 2 nd^N-1 gate of the first FET of said capacitive calibration unit and 2 nd output from another output terminal of said decoder ^N2 control words input 2 nd^N-1 gate of a second field effect transistor of said capacitive calibration unit.

Preferably, the decoder is a thermometer-coded decoder.

Compared with the prior art, the RC oscillator also comprises a capacitance calibration circuit, and further the capacitance calibration circuit comprises a decoder, a basic capacitor and a capacitor 2^N1 capacitance calibration unit, so that the capacitance of the RC oscillator can be calibrated so that the capacitance value does not vary with temperature, voltage, process; meanwhile, the resistance circuit of the invention can be matched by using different resistorsThe total resistance value is adjusted, so that the resistance value does not change along with the temperature, and the deviation introduced by an MOS device is eliminated; therefore, the output clock frequency of the RC oscillator is accurately locked near the design frequency, and the stability is better.

The invention will become more apparent from the following description when taken in conjunction with the accompanying drawings, which illustrate embodiments of the invention.

Drawings

Fig. 1 is a block diagram of a prior art RC oscillator.

Fig. 2 is a waveform diagram of a prior art RC oscillator.

Fig. 3 is a structural diagram of the RC oscillator of the present invention.

Fig. 4 is a block diagram of a capacitance calibration circuit of the RC oscillator of the present invention.

Detailed Description

Embodiments of the present invention will now be described with reference to the drawings, wherein like element numerals represent like elements. As described above, the present invention provides an RC oscillator having an accurate capacitance value, which does not vary with temperature, voltage, and process; the resistance value does not change along with the temperature, the deviation introduced by the MOS device is eliminated, and the frequency of the output clock is accurately locked near the design frequency.

Referring to fig. 3, fig. 3 is a structural diagram of an RC oscillator according to the present invention. The RC oscillator comprises a first inverter INV1, a second inverter INV2, a buffer BUF, a resistor circuit and a capacitance calibration circuit. An output end of the first inverter INV1 is connected with an input end of the second inverter INV2, an output end of the second inverter INV2 is connected with an input end of the buffer BUF, the resistor circuit is connected between the input end and the output end of the first inverter INV1, the resistor circuit and the first inverter INV1 form a charge-discharge path to charge and discharge one polar plate of a capacitor in the capacitor calibration circuit, the second inverter INV2 charges the other polar plate of the capacitor in the capacitor calibration circuit and outputs a clock signal to the buffer BUF, and the buffer BUF shapes the input clock signal to output a clock CLK; the capacitance calibration circuit is connected between the input end of the first inverter INV1 and the output end of the second inverter INV2, so as to calibrate the capacitance of the entire RC oscillator.

Specifically, referring to fig. 4, the capacitance calibration circuit includes a decoder D2A, and basic capacitors cg and 2^N-1 capacitive calibration unit; two ends of the basic capacitor cg are respectively connected with an input end of the first inverter INV1 and an output end of the second inverter INV2, so as to serve as a main capacitor source of the RC oscillator of the invention; each of the capacitance calibration units is respectively connected with an input end of the first inverter INV1 and an output end of the second inverter INV2, and an external N-bit binary control word DF<N-1:0>The input is the control terminal u1 of the decoder D2A, and the two output terminals X1 and X2 of the decoder output two groups 2^N-1 bit binary control word TCB<2^N-2:0>、TC<2^N-2:0>And two sets of said 2^N-1 bit binary control word TCB<2^N-2:0>、TC<2^N-2:0>The capacitance value of the RC oscillator is adjustable and can not change along with temperature, voltage and process; n is a natural number greater than 1, and a specific value of N may be determined according to an actual use condition, and generally, the larger the value is, the higher the frequency accuracy of the output clock CLK is.

As a preferred embodiment of the present invention, the resistor circuit includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to the input end of the first inverter INV1, the other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the output end of the first inverter INV 1. In the invention, the first resistor R1 is a non-silicide P-type polysilicon resistor, and the second resistor R2 is a silicide P-type polysilicon resistor; the non-silicide P-type polysilicon resistor has a negative temperature coefficient, and the silicide P-type polysilicon resistor has a positive temperature coefficient; assuming that the temperature coefficient of the first resistor R1 is-a/° c, the temperature coefficient of the second resistor R2 is + b/° c, let R1 ═ m × rsh1(rsh is the square resistance of the resistor, i.e., the resistance of the resistor with length and width both being 1 is rsh, the square resistance of each resistor is a fixed value, and m is the number of the square blocks of the resistor), R2 ═ n rsh2(n is the number of the square blocks of the resistor), the temperature change is Δ t, the variation amounts of R1 and R2 are Δ R1 ═ m × rsh1 (-a) × Δ t, Δ R2 ═ n ═ rsh2 b Δ t, i.e., the sum of R1+ R2 is not changed with the temperature, i.e., Δ R1+ Δ R2)/(rsm ═ rsh, and the obtained rsh/n ═ rsh2 b Δ t, i.e., the circuit may be implemented according to the present invention, i.e., without changing the ratio of the R1+ a/R1, i.e., the present invention, the temperature coefficient thereof is zero, thereby making the accuracy of the frequency of the finally output clock CLK higher. In addition, as a preferred embodiment of the present invention, the combination of the resistor having a positive temperature coefficient and the resistor having a negative temperature coefficient is not limited to the above combination, and the combination of the first resistor R1 being a non-silicide P-type polysilicon resistor and the second resistor R2 being a silicide P-type polysilicon resistor may also achieve the temperature coefficient of the resistor circuit being zero by an appropriate proportion combination, which is not described in detail again.

As a preferred embodiment of the present invention, each of the capacitance calibration units (first capacitance calibration unit, second capacitance calibration unit … … 2 nd capacitance calibration unit)^N-1 capacitive calibration unit) have exactly the same structural features. Specifically, taking a first capacitance calibration unit as an example, it includes a first fet M01, a second fet M02 and a step capacitor C0, one output terminal X1 of the decoder D2A is connected to the gate of the first fet M01, and the other output terminal X2 of the decoder D2A is connected to the gate of the second fet M02; the source electrode of the first field effect transistor M01 and the drain electrode of the second field effect transistor M02 are respectively connected with the input end of the first phase inverter INV1, the drain electrode of the first field effect transistor M01 and the source electrode of the second field effect transistor M02 are respectively connected with one end of the stepping capacitor C0, the other end of the stepping capacitor C0 is connected with the output end of the second phase inverter INV2, the substrate of the first field effect transistor M01 is grounded, and the substrate of the second field effect transistor M02 is connected with an external power supply VDD. Furthermore, the first fet M01 is an N-type fet, and the second fet M02 is a P-type fet. In the present invention, the two output terminals X1 and X2 of the decoder D2A output two groups 2^N-1 bit binary control word TCB<2^N-2:0>、TC<2^N-2:0>To each capacitance calibration unit; specifically, the 0 th control word TCB output from an output terminal X1 of the decoder D2A<0>The 1 st control word TCB is input to the gate of the first FET M01 of the 1 st capacitor calibration unit and output from an output terminal X1 of the decoder D2A<1>The gate of the first FET M21 input to the 2 nd capacitor calibration unit, that is, the 2 nd output from an output terminal X1 of the decoder D2A^N-2 control words TCB<2^N-2>Input 2 nd^N-1 first field-effect transistor M (2) of said capacitive calibration unit^N-1) a gate of 1; correspondingly, the 0 th control word TC output by the other output terminal X2 of the decoder D2A<0>The 1 st control word TC output by another output terminal X2 of the decoder D2A is input to the gate of the second field effect transistor M02 of the 1 st capacitor calibration unit<1>The gate of the second FET M22 input to the 2 nd capacitor calibration unit, that is, the 2 nd output terminal X2 of the decoder D2A^N-2 control words TC<2^N-2>Input 2 nd^N-the gate of the first fet M (2N-1)1 of said capacitive calibration units and the 2N-2 control word output by the other output of said decoder are input to the gate of the second fet of the 2N-1 of said capacitive calibration units; as shown in particular in fig. 4.

In addition, as a preferred embodiment of the present invention, the decoder D2A is a thermometer-coded decoder. The output result of the N +1 th bit of the thermometer-coded decoder is increased by a positive value based on the nth bit, so that the value of the N +1 th bit is absolutely greater than that of the nth bit, and thus, the output continuity is good and absolutely monotonous.

Referring to fig. 3 and fig. 4, the working principle and the working process of the capacitance calibration of the RC oscillator of the present invention will be described by way of example, in this example, N is set to 6, that is, the decoder D2A is a thermometer-coded decoder with 6 bits. External 6bit digital signal DF<5:0>Input to the control terminal of the decoder D2A to generate two groups 2⁶-1 differentially encoded control word TCB<62:0>And TC<62:0>Each group of control words of the same number of bits controls a corresponding one of the stepped capacitances, e.g. control word TCB<0>And TC<0>Control step capacitor C0, control word TCB<62>And TC<62>The stepped capacitance C62 is controlled for a total of 63 stepped capacitances as shown in fig. 4. Every time the digital signal DF increases or decreases by M (M is less than 2)^NA natural number of-1, here less than 63), the step capacitance accessed will be reduced or increased by M, for example, when the value of DF is 000000, the step capacitance accessed by the entire RC oscillator is 0, and when the value of DF is increased by 8 on this basis, i.e. becomes 001000, the step capacitance accessed by the entire RC oscillator is increased by 8. The RC time constant is affected by the change of the effective capacitance, and the frequency of the output clock CLK is set to f, which is 1/(2.2 RC): the capacitance becomes large and the frequency decreases and the capacitance decreasing frequency increases. External input control value default set to DF<5:0>011111, the frequency f of the clock CLK output at this time is the design frequency, and the calibration can be continued 32 steps forward and backward respectively. In this example, the calibration step is set to 0.5%, so that the calibration step can be extended by 16% from the design frequency as the center, thereby expanding the output range and enabling the frequency to be accurately locked at the design frequency.

The specific calibration implementation process is as follows: assuming that when t is equal to 0, the externally input 6-bit control value DF <5:0>, for example DF, is 011111, and after D2A is subjected to digital-to-analog conversion, a control signal TCB <62:0> -63' h0000_0000_ FFFF is output, the frequency of the output clock CLK is f0, and at t1, the voltage (the operating voltage of the inverter INV1 or INV 2) is increased by Δ V, the increase in voltage reduces the propagation delay of the inverters INV1, INV2 and the buffer BUF, the period of clock inversion is shortened, the frequency is increased, and it is assumed that the frequency becomes f1 and f1> f 0. To return the frequency of the clock CLK to f0, the control value needs to be decreased (control value DF <5:0> monotonically increases from 000000 to 111111, the larger the value, the higher the clock frequency), a is (f1-f0)/(f0 × 0.5%), a is the number of steps to be adjusted, DF <5:0> is 011111-a, and the frequency returns to f 0. The frequency changes when the temperature or the process changes, and the adjustment scheme is the same as the above. Through the adjustment of the scheme of the invention, the temperature coefficient deviation of the whole RC oscillator is less than or equal to 0.4 percent, and the center frequency precision is more than or equal to 0.5 percent.

The present invention has been described in connection with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, and is intended to cover various modifications, equivalent combinations, which are made in accordance with the spirit of the present invention.

Claims

1. An RC oscillator comprises a first phase inverter, a second phase inverter, a buffer and a resistance circuit, wherein the output end of the first phase inverter is connected with the input end of the second phase inverter, the output end of the second phase inverter is connected with the input end of the buffer, and the resistance circuit is connected between the input end and the output end of the first phase inverter; the circuit is characterized by further comprising a capacitance calibration circuit, wherein the capacitance calibration circuit is connected between the input end of the first inverter and the output end of the second inverter and comprises a decoder, a basic capacitor and a reference capacitor 2^N-1 capacitor calibration units, wherein two ends of the basic capacitor are respectively connected with an input end of a first inverter and an output end of a second inverter, each capacitor calibration unit is respectively connected with an input end of the first inverter and an output end of the second inverter, an external N-bit binary control word is input into a control end of the decoder, and two output ends of the decoder output two groups of 2^N-1 bit binary control word, and two sets of said 2^N-1 bit binary control words are all input to each capacitance calibration unit to control each capacitance calibration unit to calibrate the capacitance, N being a natural number greater than 1.

2. The RC oscillator of claim 1, wherein the resistance circuit comprises a first resistance and a second resistance; one end of the first resistor is connected with the input end of the first phase inverter, the other end of the first resistor is connected with one end of the second resistor, and the other end of the second resistor is connected with the output end of the first phase inverter.

3. The RC oscillator of claim 2, wherein the first resistor is a non-silicide P-type polysilicon resistor and the second resistor is a silicide P-type polysilicon resistor.

4. The RC oscillator of claim 2, wherein the first resistor is a silicide P-type polysilicon resistor and the second resistor is a non-silicide P-type polysilicon resistor.

5. The RC oscillator of claim 2, wherein each of the capacitance calibration units has identical structural features and comprises a first fet, a second fet and a step capacitor, one output terminal of the decoder is connected to the gate of the first fet, and the other output terminal of the decoder is connected to the gate of the second fet; the source electrode of the first field effect tube and the drain electrode of the second field effect tube are respectively connected with the input end of the first phase inverter, the drain electrode of the first field effect tube and the source electrode of the second field effect tube are respectively connected with one end of the stepping capacitor, the other end of the stepping capacitor is connected with the output end of the second phase inverter, the substrate of the first field effect tube is grounded, and the substrate of the second field effect tube is connected with an external power supply.

6. The RC oscillator of claim 5, wherein the first field effect transistor is an N-type field effect transistor and the second field effect transistor is a P-type field effect transistor.

7. The RC oscillator of claim 5, wherein the 2 nd output of an output terminal of the decoder^N2 control words input 2 nd^N-1 gate of the first FET of said capacitive calibration unit and 2 nd output from another output terminal of said decoder^N2 control words input 2 nd^N-1 gate of a second field effect transistor of said capacitive calibration unit.

8. The RC oscillator of claim 1, wherein the decoder is a thermometer coded decoder.