CN107123619A - The method for forming isolation structure in Semiconductor substrate on insulator - Google Patents
The method for forming isolation structure in Semiconductor substrate on insulator Download PDFInfo
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- CN107123619A CN107123619A CN201710102509.0A CN201710102509A CN107123619A CN 107123619 A CN107123619 A CN 107123619A CN 201710102509 A CN201710102509 A CN 201710102509A CN 107123619 A CN107123619 A CN 107123619A
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- groove
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- sidewall spacer
- active region
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000002955 isolation Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 239000012212 insulator Substances 0.000 title abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 42
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 239000011810 insulating material Substances 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 40
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 239000011229 interlayer Substances 0.000 claims 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000000280 densification Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
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- 238000006467 substitution reaction Methods 0.000 description 2
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- 244000061458 Solanum melongena Species 0.000 description 1
- 235000002597 Solanum melongena Nutrition 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to the method that isolation structure is formed in Semiconductor substrate on insulator, a kind of disclosed illustrative method includes but is not limited to form first groove, it, which is stretched into, penetrates active layers and embedded type insulating barrier, and make the upper surface of bulk semiconductor layer be exposed to the bottom of first groove to define active region, active region has outer perimeter and in forming sidewall spacer in first groove around the whole outer perimeter of active region.This method also includes after forming the sidewall spacers, carrying out at least one etching program through first groove to define and stretching into the second groove of bulk semiconductor layer, and is formed the isolation structure of insulating materials is included in the composition of first groove and second groove.
Description
Technical field
The present invention is generally related to the manufacture of integrated circuit, and more espespecially on insulator on semiconductor (SOI) substrate
Form the various methods of isolation structure.
Background technology
It is in limited wafer face in such as microprocessor, ASIC, storage device and such modern integrated circuits
Larger numbers of circuit element is formed in product and on chip area, for example：Field-effect transistor (FET), bi-polar transistor arrangement,
Junction field effect transistor (JFET), capacitor, resistor etc..FET devices have a variety of configurations, for example：Plane is filled
Put, FinFET devices, sub- rice eggplant shape grid (omega gate) device, circulating type grid (GAA) device, such as nanowire device
Deng, and they can be formed with polysilicon gate electrodes or the gate electrode being made up of one layer or more metal.These FET devices
No matter it is in which kind of precise forms or configuration, is usually to operate in a switched mode, that is, highly conductive state is presented in these devices
(conducting state) and high impedance status (cut-off state).Field-effect transistor it is condition controlled in gate electrode, gate electrode exists
When applying appropriate control voltage, formed in the Semiconductor substrate under gate electrode between control drain region and source area
The electric conductivity of channel region.One layer of insulating materials makes gate electrode be separated with Semiconductor substrate.
In some applications, sometimes in so-called SOI substrate, (semiconductor-on-insulator is served as a contrast integrated circuit (IC) product
Bottom) on formed.For example, it can be formed on soi substrates including vague and general type or partially depleted type FET entirely (for example：Plane is filled
Put or FinFET devices) IC products.Figure 1A is referred to, the circuit element of these such as transistors is in SOI substrate
Active region 10A spaced apart defined in 12 is formed into 10F.More specifically, isolation structure 20 is formed in substrate 12
Mode be that isolated groove (not shown) is defined in substrate 12, and the grade isolated groove is loaded with insulating materials in thereafter.Production
Raw isolation structure 20 is sometimes referred to as shallow trench isolation (STI) structure.In fact, isolation structure 20 defines be spaced in the substrate
The active region 10A to 10F opened.Isolation structure 20 makes circuit element electrically isolated from one another, so that circuit can be operated as desired, without
Short circuit can be caused between neighboring devices.Active region 10A to 10F generally has rectangle configuration (when being inspected from top), but not institute
Have to apply and be not always the case.Active region 10A to 10F respectively has active section length (AL) and active sector width (AW).Active section length is led to
Often it is considered as active region parallel along the grid length direction of the transistor unit (not shown) with will be formed on active region
The size in direction.Conversely, active sector width is typically considered to active region along with the transistor formed on active region is filled
Put the size in the parallel direction in grid width direction of (not shown).In some applications, it can be formed on single active region
Multiple transistor units.
However, forming isolation structure on soi substrates not completely without problem.The sectional view of the illustrative SOI substrates 12 of Figure 1B
(along active section length (AL) direction takes and see).Generally, SOI substrate 12 is by active semiconductor layer 12A, bulk semiconductor layer
12C and the embedded type insulating barrier 12B (sometimes referred to as " BOX " layer) being placed between active layers 12A and body layer 12C are constituted.It is brilliant
Body pipe device is formed in active layers 12A and above active layers 12A.In this embodiment, active layers 12A is by first
Active layers region 12A1 and the second active layers region 12A2 are constituted, and wherein region 12A1 and 12A2 is by different semi-conducting material institutes
Constitute.For example, the first active layers region 12A1 can be one layer of tensile-strained silicon or carborundum, can N-type formed here
Transistor unit, and the second active layers region 12A2 can be a layer compression strained silicon Germanium, can P-type transistor dress formed here
Put.Elongation strain is induced on the first active layers region 12A1, to be lifted to be formed on the electric effect of N-type device therein
Can, and compression strain is then induced on the second active layers region 12A2, to be lifted to be formed on the electric effect of p-type device therein
Energy.Certainly, in some applications, whole active layers 12A can be as made by single semi-conducting material, such as：Silicon, wherein active layers
12A different zones, which induce, to be intended to strain, to lift the electric efficiency to be formed on transistor unit therein.In addition,
Active layers 12A these parts not all need to be strained semiconductor material.For example, the first active layers region 12A1 can
To be the substantive without strained semiconductor material region of N-type device to be formed, and the second active layers region 12A2 can form P
The compression strain semiconductor material regions of type device.
Fig. 1 C, which are illustrated, has formed first layer 14 and the product after the second layer 16 above active layers 12A.First and second layer 14,
16 can be made up of various different materials, and the thickness formed can be different.In one embodiment, first layer 14 can be
Oxide skin(coating) is padded, and the second layer 16 can be pad nitride layer.Layer part 14,16 can be collectively treated as hard mask layer.
Fig. 1 D illustrate the product after patterning first layer 14 and the second layer 16, and this patterning is used for defining by pattern spy
The etching mask that 17A and 17B is constituted is levied, these pattern characteristics will correspond respectively to the master for treating to be formed in SOI substrate 12
Dynamic area 10A, 10B shape.Layer part 14,16 can pass through the patterned etch mask (not shown) for for example patterning photoresist layer, lead to
Cross and perform one or more etching programs to be patterned, conventional lithographic tools can be used to come with technology for this patterned etch mask
Formed.
Fig. 1 E are illustrated carries out the product after one or more etching programs through pattern characteristics 17A, 17B, is stretched into define
Body layer 12C multiple isolated grooves 18.The depth and width of groove 18 may depend on application-specific and become.Formed groove 18 with
Just shallow trench isolation (STI) structure is formed on the product.The formation of groove 18 causes the first active region 10A and the second active region
10B's defines.
Fig. 1 F illustrate the IC products carried out after several procedure operation.First, face deposits one layer of insulating materials on the substrate 12
(for example：Silica), so as to excessive filling groove 18.Afterwards, terminate thing to carry out as grinding using second material layer 16
Cmp program.Then, insulant of the so-called densification anneal program to be densified in groove 18 is carried out.These behaviour
Isolated area 20 is resulted in, for example：STI region, it causes active region 10A to 10B (and the device being formed thereon) electric each other
Sexual isolation.However, deposition procedure and densification anneal the program typical case carried out for the deposition of insulative material in groove 18
For rich oxygen containing procedure operation.As a result, as shown in dashed region 13, loading groove 18 with insulating materials and/or carrying out
During densification anneal program, active layers region 12A1 and 12A2 is set to have part the efficient oxidation occur, so as to cause active layers area
Domain 12A1 and 12A2 has part unexpected consumption occur.Active layers region 12A1 and 12A2 is along active region length direction and master
There is undesirable consumption in dynamic sector width direction.This unexpected oxidation extends laterally 13L and can become with application-specific,
For example：5nm to 500nm.Unfortunately, active layers region 12A1,12A2 undesirable consumption can active layers region 12A1,
Stretching or the induction strain relaxation of compression-type are caused on 12A2, and then device efficiency can be reduced.The reduction of this device efficiency is actively
Layer zone length (AL) be less than about 300nm to 700nm when, may can especially turn into problem.
Fig. 1 G illustrate the product carried out after uniform etching removal program, and this program will expose material to the open air with substantially identical speed
All equably consume.The thinning part of second material layer 16 maintains appropriate position after this uniform etching removes EP (end of program)
Put.
Fig. 1 H illustrate the product after the program of being etched, for optionally removing the second layer 16 relative to adjacent material
Remainder.Pad oxide skin(coating) 14 to maintain to be located above first and second active layers region 12A1,12A2, for protecting semiconductor
Material.In this time point of manufacturing process, conventionally manufactured operation can be carried out to complete these dresses on active region 10A, 10B
Put.
The present invention for forming the various methods of isolation structure on semiconductor (SOI) substrate on insulator, it can avoid,
Or at least reduce the effect indicated above for recognizing problem one or more therein.
The content of the invention
Simplification summary of the invention introduced below, so that some aspects to the present invention have basic insight.This summary is simultaneously
The exhaustive overview of non-invention.It is not intended to point out the important or key element of the present invention, or narration scope of the invention.Mesh
Be only that and introduce some concepts in simplified form, be used as the introduction being described in more detail below.
Generally, various novelty sides of the present invention for formation isolation structure on semiconductor (SOI) substrate on insulator
Method.A kind of disclosed illustrative method also includes forming first groove, and it, which is stretched into, penetrates active layers and embedded type insulating barrier, and
And the upper surface of bulk semiconductor layer is exposed to the bottom of first groove to define active region, active region has outer perimeter simultaneously
Sidewall spacer is formed in first groove around the whole outer perimeter of active region.In this embodiment, this method also includes
After forming the sidewall spacers, carry out at least one etching program and stretch into bulk semiconductor layer through first groove to define
Second groove, and form the isolation structure that insulating materials is included in the composition of first groove and second groove.
An illustrative IC products disclosed herein include but is not limited to partly lead with the main body in SOI substrate
The active region that the first groove terminated on the upper surface of body layer is defined, active region has outer perimeter, and it includes active layers
A part, some is placed under this partial bottom of active layers and is in contact with it embedded type insulating barrier, and sidewall spacer is put
Around the whole outer perimeter of active layers, wherein sidewall spacer is placed on the side surface of this part of active layers and connect with it
Touch, on the side surface of this part of embedded type insulating barrier and be in contact with it and bulk semiconductor layer upper surface a part
Go up and be in contact with it.In this embodiment, this product also includes the second groove that bulk semiconductor layer is stretched into from first groove,
Isolation structure comprising the insulating materials being placed in the composition of first groove and second groove and be formed in active region and
Circuit element above active region.
Brief description of the drawings
The present invention accompanying drawing that can arrange in pairs or groups understands with reference to following explanation, and wherein identical reference represents similar element,
And wherein：
Figure 1A to 1H illustrates a kind of illustrative elder generation for being used on semiconductor (SOI) substrate on insulator form isolation structure
Preceding technique and skill；And
Fig. 2A to 2K, which is illustrated, various disclosed herein to be used to form isolation junction on semiconductor (SOI) substrate on insulator
The novel method of structure.
Although subject matter disclosed herein is easily influenceed by various modifications and substitutions forms, its certain specific embodiments
Still represented and be described in detail herein by the embodiment in schema.It should, however, be understood that specific herein
The explanation of specific embodiment is not intended to limit the invention to disclosed particular form, on the contrary, right of such as enclosing will
Ask book to be defined, be intended to cover all modifications, impartial example and alternative solution in the spirit and scope for falling within the present invention.
Embodiment
Illustrate every illustrative specific embodiment of the present invention below.It is in this specification and undeclared actual in order to clarify
All features of implementation aspect.Certainly, it will understand, when developing any this actual implementation and applying, it is necessary to make perhaps
Many specific decision-makings of implementation aspect can be only achieved the specific purpose of developer, for example meet system about and the relevant limitation bar of business
Part, these restrictive conditions can become with implementation aspect difference.In addition, will understand, this development effort may it is complicated and
It is time-consuming, although in this way, still can be the regular works for benefiting from the those of ordinary skill in the art of the present invention.
This patent target illustrates now with reference to accompanying drawing.Various structures, system and device are intended merely to explaination in the drawings
And illustrate, in order that the present invention should not be obscured because of the well-known details of those of ordinary skill in the art.Though
So in this way, will accompanying drawing include with illustrate and explain the present invention illustrative embodiment.Word group used herein and word
Group, which be should be appreciated that and be annotated as the word group and phrase understood with those of ordinary skill in the art, has consistent meaning.
The usual and different usual meaning vocabulary or phrase (defining) understood from those of ordinary skill in the art
It is specifically defined, it is not intended to furnish a hint by the uniformity usage of this paper vocabulary or phrase.With regard to term or phrase with being intended to
In acquiring a special sense for the aspect of (that is, the term or phrase understood different from one of ordinary skill in the art), this is special
Different definition is by the description directly and clearly to provide term or the specifically defined clear and definite mode of phrase gives clear proposition.
Various novel methods of the present invention for formation isolation structure on semiconductor (SOI) substrate on insulator.Herein
Disclosed in method and device can be used when using the various technologies manufacture product such as NMOS, PMOS, CMOS, and can
Used when manufacturing the various different IC products such as memory article, logical product, ASIC.Certainly, taken off herein
The invention shown is not to be seen as limited by illustrative embodiment illustrated and described herein.This is described in more detail now with reference to accompanying drawing
Every illustrative specific embodiment of the method and device disclosed in text.Each material layer described below can pass through various differences
Any one is formed known technology, for example：Chemical vapor deposition (CVD) program, ald (ALD) program, thermally grown journey
Sequence, rotary coating skill etc..In addition, such as user in this paper and appended claims, words " adjacent " will give broad sense
Annotate, and should annotate into and cover a feature and contact another feature really or in close proximity to that another feature.
Fig. 2A to 2K illustrates the formation isolation structure disclosed herein on semiconductor (SOI) substrate on insulator
Various novel methods.These schemas can be used identical reference to represent the previously institute in the section of present application prior art one
The project stated.
Fig. 2A illustrates the IC products corresponding to the manufacture time point shown in Fig. 1 D, that is, by mask features 17A, 17B institute
IC products after the patterned etch mask formation of composition.Active layers 12A can be by such as silicon, SiGe, germanium, carbon, silicon-carbon, any
One or more regions of any one are constituted in the various different semi-conducting materials such as iii-v combined material.In some applications,
Active layers 12A can be made up of single semi-conducting material completely, for example：Silicon or SiGe, and in other applications, active layers 12A
It can be made up of all regions of different semi-conducting materials.Similarly, body layer 12C can appoint in various different semi-conducting materials
One is constituted, and BOX layer 12B any one can be constituted in the various different insulative materials such as silica.BOX layer
12B thickness can also become with application-specific.Technology for forming such SOI substrate 12 is logical to having in art
Normal skill is well-known.
Pattern characteristics 17A, 17B that Fig. 2 B illustrate transmission patterned etch mask carry out the production after one or more etching programs
Product, to define the multiple initial or first grooves 30 for extending into body layer 12C portion of upper surface 32 and exposing it to the open air.Initially
The depth of groove 30 can become with width with application-specific, for example：Can be with active layers 12A and embedded type insulating barrier 12B thickness
And become.The formation of initial or first groove 30 causes defining for the first active region 31A and the second active region 31B.It is specific at one
In embodiment, the formation of groove 30 can pass through active layers 12A and exhausted in embedded type by carrying out the first anisotropic etching program
Terminated on edge layer 12B, after the first anisotropic etching program that completes, change etch chemistries, and carry out in main body
The the second anisotropic etching program terminated on semiconductor layer 12C upper surface 32.
Fig. 2 C illustrate progress conformal deposit program to form the product after conformal spacer material layer 34, the conformal spacer
Material layer is formed on the substrate 12, and position connects on the bottom end body layer 12C of initial trench 30 upper surface 32 and with it
Touch.Layer of spacer material 34 can (k values be equal to or greatly by such as silica, silicon nitride, silicon oxynitride, carborundum, high-g value
10) constituted, and can be manufactured by carrying out such as ALD programs in the various different materials such as.The thickness of layer of spacer material 34
Degree can become with application-specific and various factors, and for example it can have scope to fall the thickness in about 2nm to 10nm.
Fig. 2 D are shown in the product carried out in layer of spacer material 34 after anisotropic etching program, and the is placed in define
The first side wall sept 34S1 around one active region 31A whole circumference, and define and be placed in the whole of the second active region 31B
Individual other second sidewall sept 34S2 of periphery.Under certain situation below, reference 34S will generally be used for
Censure sidewall spacer.It note that in the specific embodiment illustrated, and refer to active region 31A, sept 34S1 is formed
In on active layers region 12A1 outer surface 33 and be in contact with it, on embedded type insulating barrier 12B outer surface 35 and and its
Contact and pad on outer surface of the oxide skin(coating) 14 with padding nitride layer 16 and be in contact with it.Sept 34S2 contacts are actively
Counter structure on area 31B.Sept 34S1,34S2 respectively have the upper table for the bottom end body layer 12C for being placed in first groove 30
On face 32 and the bottom end surface 37 that is in contact with it.
Fig. 2 E, which are illustrated, carries out one or more etching programs through the product after initial trench 30, sept 34S1,34S2
Now it is located in this initial trench, this etching program is used for defining multiple second or the body layer groove 36 for stretching into body layer 12C.The
The depth of two grooves 36 can become with width with application-specific, for example：The autonomous agent of second groove 36 layer 12C upper surface 32,
There can be about 50nm to 500nm depth.Note the outer rim 39 of edge 36A, 36B of second groove 36 respectively with sept 34S1
And the sept 34S2 substantive autoregistration of outer rim 41.
Fig. 2 F illustrate the product carried out after several procedure operation.First, face deposits one layer of insulating materials 38 on the substrate 12
(for example：Silica), so as to the composition of excessive filling first groove 30 and second groove 36.Afterwards, using the second material
Layer 16 terminates thing to carry out cmp program as grinding.Then, so-called densification anneal program is carried out with densification
Change the insulating materials 38 being placed in groove 30,36.These operations result in isolation structure 38, for example：STI region, it makes winner
Dynamic area 31A to 31B (and the device being formed thereon) is electrically isolated from one another.In the embodiment shown, the top of isolation structure 38
Be placed on sept 34S side surface 39,41 and with its material contact.It note that in being saved with present application prior art one
Unlike disclosed prior art program, during deposition of insulative material 38 and during densification anneal program, sept
34S1,34S2 protect active layers region 12A1,12A2 from playing oxidation during these rich oxygen containing procedure operation.Cause
This, can be avoided or at least relevant with the undesirable consumption of 12A1,12A2 of active layers region described in reduction present application prior art
The problem of.
Fig. 2 G illustrate the product carried out after uniform etching removal program, and this program is with substantially identical speed by the material exposed to the open air
Material is all equably consumed.The thinning part of second material layer 16 maintains appropriate position after this uniform etching removes EP (end of program)
Put.
Fig. 2 H illustrate the product after the program of being etched, for optionally removing the second layer 16 relative to adjacent material
Remainder.Pad oxide skin(coating) 14 maintains to be placed in active region 31A, 31B on first and second active layers region 12A1,12A2
Face, for protecting following semi-conducting material.
Fig. 2 I illustrate the product formed in active region 31A, 31B and above active region 31A, 31B after illustrative circuit element.
More specifically, the field-effect transistor being made up of the grid structure 40 simply illustrated is in active region 31A, 31B and main
Formed above dynamic area 31A, 31B.Grid structure 40 can be made up of with regard to N or p-type device different materials, and so-called grid can be used
(gate-first) or substitution grid (replacement-gate) manufacturing technology is extremely first made to manufacture.Grid structure 40 can be used for
Any kind of device, for example：Planar devices, FinFET devices, GAA devices etc..Other types of circuit element also can be
Formed in active region 31A, 31B and above active region 31A, 31B, for example：Resistor, capacitor, bipolar transistor etc..As above institute
State, in some applications, multiple circuit elements can be formed on active region 31A, 31B either of which or both, for example：It is brilliant
Body pipe device.Time point can be manufactured herein to carry out conventionally manufactured operation to complete these devices that active region 31A, 31B are formed above.
The plans of Fig. 2 J mono-, it simply illustrates the first sept being placed in around the first whole outer perimeters of active region 31A
34S1 and the second sept 34S2 being placed in around the second active region 31B.Shown (being represented by dotted lines) also has will be actively
The illustrative grid structure 40 that area 31A, 31B are formed above.It note that sept 34S1 and 34S2 are laterally disposed in isolation material respectively
Between material 38 and active region 31A, 31B.
Certainly, method disclosed herein can operate with the whole circumference in the active region of any be intended to shape or configuration
Surrounding forms protection interval thing 34S (i.e. sept 34S1,34S2).For example, Fig. 2 K illustrate the plan of an embodiment, its
In can carry out method disclosed herein with around the whole circumference of the active region 30C with overall L-shaped configuration formed protect
Protect sept 34S.Shape such as active region 30C active region sometimes IC products include so-called " taper " device in the case of shape
Into wherein the device with different grid lengths or grid width can be formed on single active region.In the embodiment shown,
First device is formed above overall active region 30C Part I, and with the first active layers length AL1And first master
Dynamic slice width degree AW1, and second device is formed above overall active region 30C Part II, and it is long with the second active layers
Spend AL2And the second active layers width AW2, wherein AL1Less than AL2, and AW1More than AW2。
The special specific embodiment of disclosed above only belongs to descriptive, as the present invention can use those skilled in the art
The different but impartial modes substantially known are changed and put into practice and instruct benefit with this paper.For example, the above
The program step proposed can be carried out according to different order.Furthermore, except as described in claims below, do not anticipate
Figure is limited to the details of construction illustrated herein or design.Therefore, it was demonstrated that specific specific implementation disclosed above can be altered or modified
Example, and all such variants be all considered as scope of the invention and spirit in.It should be noted that in this specification and appended
" first ", " second ", " the 3rd " or " the 4th " etc. is to illustrate the term of various programs or structure only in claims
The memorandum of such step/structure is treated as with reference to using, it is not necessary to which the right such step/structure of metaphor has according to sequencing
Row/formation.Certainly, depending on accurately demand language, the sequencing of this class method may or may not be needed.Therefore, originally
The person of carrying in the protection that text is sought such as claims below.
Claims (20)
1. it is a kind of on soi substrates formed isolated area method, the SOI substrate comprising active semiconductor layer, bulk semiconductor layer,
And the embedded type insulating barrier being placed between the active semiconductor layer and bulk semiconductor layer, this method includes：
At least one first etching program is carried out to define first groove, it, which is stretched into, penetrates the active semiconductor layer and the embedded type
Insulating barrier, and the upper surface of bulk semiconductor layer is exposed to the open air in the bottom of the first groove, wherein, the first groove is defined
Active region with outer perimeter；
In forming sidewall spacer in the first groove around the whole outer perimeter of the active region；
After the sidewall spacer is formed, carry out at least one second etching program and stretch into this through the first groove to define
The second groove of bulk semiconductor layer；And
Form the isolation structure for including insulating materials in the composition of the first groove and the second groove.
2. at least one first etching program is the method for claim 1, wherein carried out to define the first groove bag
Contain：
The first anisotropic etching program is carried out to be etched through the active semiconductor layer, and on the embedded type insulating barrier eventually
Only；And
After the first anisotropic etching program is completed, the terminated on the upper surface of bulk semiconductor layer is carried out
Two anisotropic etching programs.
3. the method for claim 1, wherein in shape in the first groove around the whole outer perimeter of the active region
Included into the sidewall spacer：
Carry out conformal deposit program with by conformal spacer material layer depositions above the active region and the active semiconductor layer
At least on side surface and be in contact with it, on the side surface of the embedded type insulating barrier and be in contact with it and the first groove should
The whole of the bulk semiconductor of this in bottom layer has been exposed to the open air on upper surface and has been in contact with it；And
Anisotropic spacer etch program is carried out in the conformal spacer material layer.
The sidewall spacer is formed as putting 4. the method for claim 1, wherein forming the grade sidewall spacer and including
In on the side surface of the active semiconductor layer and be in contact with it, on the side surface of the embedded type insulating barrier and be in contact with it and
In a part for the upper surface of the bulk semiconductor that the bottom end of the first groove exposes to the open air layer and it is in contact with it.
5. method as claimed in claim 4, wherein, the bottom end surface of the sidewall spacer is placed in being somebody's turn to do for bulk semiconductor layer
On the part of upper surface and it is in contact with it.
6. the method for claim 1, wherein the sidewall spacer includes silica, silicon nitride, silicon oxynitride, carbon
SiClx or high-g value (k values are equal to or more than 10) one of which.
7. the method for claim 1, wherein formed the isolation structure include by the isolation structure be formed so that this every
From a part of material contact of structure sidewall spacer.
8. the method for claim 1, wherein the insulating materials includes silica.
9. the method for claim 1, wherein the edge at the edge of the second groove and the sidewall spacer is substantially right
It is accurate.
10. a kind of method for forming isolated area on soi substrates, the SOI substrate includes active semiconductor layer, bulk semiconductor
Layer and the embedded type insulating barrier for being placed in the active semiconductor layer and the bulk semiconductor interlayer, this method are included：
At least one first etching program is carried out to define first groove, it, which is stretched into, penetrates the active semiconductor layer and the embedded type
Insulating barrier, and the upper surface of bulk semiconductor layer is exposed to the open air in the bottom of the first groove, wherein, the first groove is defined
Active region with outer perimeter；
Carry out conformal deposit program with by conformal spacer material layer depositions above the active region, in the first groove and
On whole upper surface exposed to the open air of bulk semiconductor layer and it is in contact with it in the bottom of the first groove；
Anisotropic spacer etch program is carried out in the conformal spacer material layer, so as in the whole periphery of the active region
Sidewall spacer is formed around boundary in the first groove, wherein, the bottom end surface of the sidewall spacer is placed in the first groove
In a part for the upper surface of the bulk semiconductor that the bottom end exposes to the open air layer and it is in contact with it；
After the sidewall spacer is formed, carry out at least one second etching program and stretch into this through the first groove to define
The second groove of bulk semiconductor layer；And
Form the isolation structure for including insulating materials in the composition of the first groove and the second groove.
11. method as claimed in claim 10, wherein, at least one first etching program is carried out to define the first groove
Comprising：
The first anisotropic etching program is carried out to be etched through the active semiconductor layer, and on the embedded type insulating barrier eventually
Only；And
After the first anisotropic etching program is completed, the terminated on the upper surface of bulk semiconductor layer is carried out
Two anisotropic etching programs.
12. method as claimed in claim 10, wherein, carry out the anisotropic spacer in the conformal spacer material layer
Etching program carries out the anisotropic spacer erosion to form the sidewall spacer in the conformal spacer material layer
Quarter program, so as to formed be placed on the side surface of the active semiconductor layer and be in contact with it and the embedded type insulating barrier side table
On face and the sidewall spacer that is in contact with it.
13. method as claimed in claim 10, wherein, the isolation structure is formed comprising the isolation structure is formed so that into this
A part of material contact of isolation structure sidewall spacer.
14. method as claimed in claim 10, wherein, the edge of the second groove is substantially right with the edge of the sidewall spacer
It is accurate.
15. a kind of IC products formed on soi substrates, the SOI substrate includes active semiconductor layer, bulk semiconductor
Layer and the embedded type insulating barrier for being placed in the active semiconductor layer and the bulk semiconductor interlayer, the product are included：
Active region, it is defined by the first groove terminated on the upper surface of bulk semiconductor layer, and the active region has
Outer perimeter, the active region includes a part for the active semiconductor layer；
A part for the embedded type insulating barrier, it is placed under the partial bottom of the active semiconductor layer and is in contact with it；
Sidewall spacer, it is placed in around the whole outer perimeter of the active region, and the sidewall spacer is placed in the active semiconductor layer
The part side surface on and be in contact with it, on the side surface of the part of the embedded type insulating barrier and be in contact with it and should
Bulk semiconductor layer the upper surface a part on and be in contact with it；
Second groove, it extends from the first groove and stretched into bulk semiconductor layer；
Isolation structure, it, which is included, is placed in the first groove and the insulating materials in the composition of the second groove；And
Circuit element, it is formed in the active region and above the active region.
16. IC products as claimed in claim 15, wherein, the sidewall spacer includes silica, silicon nitride, nitrogen
Silica, carborundum or high-g value (k values are equal to or more than 10) one of which.
17. IC products as claimed in claim 15, wherein, between a part of material contact of isolation structure side wall
Parting.
18. IC products as claimed in claim 15, wherein, the insulating materials includes silica.
19. IC products as claimed in claim 15, wherein, the edge of the second groove and the side of the sidewall spacer
Edge is substantially aligned.
20. IC products as claimed in claim 15, wherein, the circuit element includes at least one field effect transistor
Pipe.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201615051916A | 2016-02-24 | 2016-02-24 | |
| US15/051,916 | 2016-02-24 |
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| CN107123619A true CN107123619A (en) | 2017-09-01 |
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|---|---|---|---|
| CN201710102509.0A Pending CN107123619A (en) | 2016-02-24 | 2017-02-24 | The method for forming isolation structure in Semiconductor substrate on insulator |
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| TW (1) | TWI631662B (en) |
Cited By (1)
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|---|---|---|---|---|
| CN108054132A (en) * | 2017-12-13 | 2018-05-18 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090127649A1 (en) * | 2007-11-20 | 2009-05-21 | Oki Semiconductor Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN103137705A (en) * | 2011-12-05 | 2013-06-05 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
| US20140252534A1 (en) * | 2013-03-11 | 2014-09-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making deep trench, and devices formed by the method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050136588A1 (en) * | 2003-12-23 | 2005-06-23 | Chris Speyer | Method of forming isolation regions |
| US9502565B2 (en) * | 2014-06-27 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Channel strain control for nonplanar compound semiconductor devices |
-
2016
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090127649A1 (en) * | 2007-11-20 | 2009-05-21 | Oki Semiconductor Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN103137705A (en) * | 2011-12-05 | 2013-06-05 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
| US20140252534A1 (en) * | 2013-03-11 | 2014-09-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making deep trench, and devices formed by the method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108054132A (en) * | 2017-12-13 | 2018-05-18 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and preparation method thereof |
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| TW201731018A (en) | 2017-09-01 |
| TWI631662B (en) | 2018-08-01 |
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