CN107121581B - A kind of data processing method of data collection system - Google Patents
A kind of data processing method of data collection system Download PDFInfo
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- CN107121581B CN107121581B CN201710278724.6A CN201710278724A CN107121581B CN 107121581 B CN107121581 B CN 107121581B CN 201710278724 A CN201710278724 A CN 201710278724A CN 107121581 B CN107121581 B CN 107121581B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form
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Abstract
The invention discloses a kind of data processing methods of data collection system, pass through the snap shot coefficient sent using host computer, counter module will generate marking signal, it is postponed into a clock control multiply-accumulator core progress data pipeline and multiplies accumulating operation, the valid data in the marker output data can be utilized in this way.Achieve the purpose that save hardware resource using the part low level substitution divide operations that there is FPGA the ability for carrying out bit manipulation to data to cast out multiply-accumulator calculated result.
Description
Technical field
The invention belongs to measuring instrument acquisition technique fields, more specifically, are related to a kind of digital storage oscilloscope and adopt
The data processing method of collecting system.
Background technique
Important component of the measuring instrument as engineering field, has been widely used for every field.With technology
It continues to develop, measuring instrument is also more and more wider towards bandwidth, and sample rate is higher and higher, and the increasing direction of sampling precision is energetically
Development.With being obviously improved for ADC performance, the bottleneck of limitation measuring instrument overall performance is just present in carrying out acquisition data
In reason.
Fortune can be directly resulted in since data volume is excessively huge by directly carrying out operational analysis and storage to the data of ADC acquisition
Inefficiency is calculated, and huge data are not easily found suitable memory space.With the continuous development of analog channel technology,
Data volume can be also continuously increased, it is therefore necessary to be improved in data processing method.
Domestic and international instrument status is analyzed, common method is to carry out snap shot to data.It is different according to the when base of user setting,
Different degrees of snap shot is carried out to the data of sampling, it is assumed that snap shot coefficient is n, then it represents that a data are only taken in every n data,
Other data all abandon, and can reduce data volume in this way, improve operation efficiency, reduce memory space.Snap shot coefficient is not
Together, also not identical to the influence of initial data, snap shot coefficient is bigger, will lead to more to primary data information (pdi) loss.In order to
The accuracy for improving analysis data, frequently with box average method, for different snap shot coefficients, to the data of different number
It is averaged, (S1+S2+...+Sn)/n, wherein SnIndicate data, n indicates snap shot coefficient.Processing is for wanting to see in this way
The user that waveform profiles filter random noise improves the reliability of data.
It is found through practice, using existing method, with adding for Measurement channel number, the increase of ADC sampling precision, data
Bit wide increases, and is handled in FPGA with more resources, especially division is wanted to realize in FPGA, can consume especially more
Resource.But for the real-time for realizing measuring instrument, these processing all have to carry out in FPGA, hardware resource in FPGA
It is limited, therefore it is imperative to study a kind of method that can have not only guaranteed data reliability but also save FPGA resource.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of data processing sides of data collection system
Method averagely filters random noise using box in data snap shot, guarantees the reliability of data as far as possible, user is allowed to see subject to more
True profile information, and more FPGA resources are not consumed.
For achieving the above object, a kind of data processing method of data collection system of the present invention, which is characterized in that packet
Include following steps:
(1), system initialization
Host computer sends reset signal to data collection system by controller, executes and resets operation, after the completion of reset, on
Position machine sends initializing signal to controller, and control ADC configuration module is each by ADC signal coffret protocol configuration ADC's
Item parameter, completes initialization operation；
(2), ADC acquires data and is converted to the data reception module that digital signal is input to FPGA；
(3), data reception module receives according to the Data Transport Protocol of ADC, parses digital signal, then is input to box
Averaging module；
(4), box averaging module will carry out box average calculating operation to data using multiply-accumulator and the operation of bit wide cut position,
That is:Wherein, SnIndicate parallel data, K indicates that amplification coefficient, Y indicate the bit wide to be clipped, and n is indicated
Snap shot coefficient；
(5), the valid data deposit memory after taking box average calculating operation is read for host computer
Writing for the FLAG signal control memory generated using counter module in box averaging module is enabled, and FLAG is believed
The n data of output of corresponding box averaging module take box average result as valid data when number being high level clock
Memory is stored in read for host computer.
Wherein, the snap shot coefficient n issues FPGA by host computer calculating again；Wherein, the specific calculating side of snap shot coefficient n
Method are as follows:
If base is O seconds when user selects, then one lattice of screen of digital storage oscilloscope indicate points X, then between point
It is divided intoSecond, if data sampling rate is P per second, the sampling interval is 1/P seconds, then snap shot coefficient is
Further, the calculation method of the amplification coefficient K are as follows:
(3.1), snap shot coefficient n will be amplified A times, and obtains An, wherein A is related to average result precision；
(3.2), enable multiply-accumulator multiplies accumulating the X that coefficient is value before amplification coefficient is rounded, and takes and closest normal of An
Number 2Y- 1, then basisCalculate X value；
(3.3), X value is rounded, obtains amplification coefficient K.
Further, the multiply-accumulator multiplies accumulating operation using assembly line, and input port includes input multiplier
A, B, synchronous reset signal SCLR, control signal SUBTRACT, bypass control signal BYPASS, and clock enables CE, clock signal
CLK；
Realize that multiply-accumulator assembly line multiplies accumulating operation by the variable counter controls BYPASS signal of counts；
Wherein, the counts of counter are snap shot coefficient n, and counter module generates a FLAG signal, when counting down to n
When FLAG signal is drawn high a clock cycle, recycle d type flip flop by one clock cycle of FLAG signal delay go control multiplies
The BYPASS interface of accumulator is then the high level clock cycle in FLAG, and multiply-accumulator output is the output knot of cumulative n times
Fruit.
The bit wide intercept operation is intercepted to multiply-accumulator calculated result, Y exported from multiply-accumulator
Start to take with the data of ADC sampled data bit wide size same bit-width as box average output.
Goal of the invention of the invention is achieved in that
A kind of data processing method of data collection system of the present invention passes through the snap shot coefficient sent using host computer, meter
Number device module will generate marking signal, it is postponed a clock control multiply-accumulator core progress data pipeline and multiplies accumulating behaviour
Make, the valid data in the marker output data can be utilized in this way.Have using FPGA and bit manipulation is carried out to data
The part low level substitution divide operations that ability casts out multiply-accumulator calculated result achieve the purpose that save hardware resource.
Meanwhile a kind of data processing method of data collection system of the present invention also has the advantages that
(1), the box average algorithm of this method replaces traditional division arithmetic using the method for casting out low level, in FPGA,
It realizes that division arithmetic can consume many hardware resources, and casts out low level without consumption resource.When data acquisition channel number is got over
More, the resource of saving is more.The embodiment contains 128 channels, just saves 128 DSP48 core in FPGA.For tight
The FPGA hardware resource opened is a no small saving.
(2), traditional box mean time base, which is converted to snap shot coefficient, is carried out in FPGA, and there are many Ruo Shiji gear,
Also many resources can be consumed to store snap shot coefficient.For this method by snap shot coefficient to directly being sent by host computer, host computer will
Shi Ji is converted to snap shot coefficient and issues FPGA, also saves certain resource in this way for FPGA.
(3), control multiply-accumulator is gone using the method that the marking signal for generating counter postpones a clock, thus
The valid data in mark output data directly can be removed using the marking signal, generate number using other methods so as to save
According to the required hardware resource of effective marker.
Detailed description of the invention
Fig. 1 is a kind of specific embodiment structure chart of data collection system of the present invention；
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Embodiment
Fig. 1 is a kind of specific embodiment structure chart of data collection system of the present invention.
In the present embodiment, as shown in Figure 1, it is necessary first to data acquisition system be initialized, secondly, by upper
External signal is processed into the signal for meeting ADC range by the control of machine by external signal conditioning module.
ADC is configured by FPGA, and the signal after conditioning passes through ADC, digital signal is converted analog signals into, with certain lattice
Formula is sent in FPGA.
It mainly include ADC configuration module, data reception module, box averaging module and data memory module in FPGA.
Data reception module receives the digital signal that ADC is brought, and is arranged, is sent to box averaging module.
Box averaging module includes multiply-accumulator module and bit wide interception module etc..Snap shot number is after being calculated by host computer
Issue box averaging module.Base gear is converted to corresponding snap shot coefficient there are in host computer when host computer will be different, when with
When family selection is different when base, host computer will pass through controller and send different snap shot coefficients.
It is multiply-accumulator coefficient that multiply-accumulator module, which has a parameter, and data are amplified K times using the coefficient.Work as host computer
Different snap shot coefficients is sent, multiple selector will pass through snap shot coefficient and corresponding amplification coefficient is selected to be output to multiply-accumulator mould
Block.
Multiply-accumulator is the IP kernel example metaplasia by XILINX at Yao Liyong multiply-accumulator completes data processing behaviour not intermittently
Make, needs to utilize BYPASS signal.Different snap shot coefficients correspond to different accumulative frequencies, therefore the control of BYPASS signal is by one
The variable counter module of a counts is completed.The output bit wide S of multiply-accumulator be data accumulation number needed for bit wide, multiply it is tired
The sum of bit wide needed for adding device coefficient, data bit width three.In order to multiply accumulating calculating compatibility to all snap shot coefficients, multiply accumulating
The output bit wide of device selection bit wide required when should select snap shot coefficient maximum.
Multiply-accumulator is sent into bit wide interception module after calculating result, and the input data bit wide of bit wide interception module is S, defeated
Data bit width is Q, i.e. sampled data bit wide out.It by multiple selector and one Q register groups at.It is sent out according to host computer
The snap shot coefficient sent, multiple selector can select in the register of the data position [Y+Q-1, Y] deposit Q, then by the register
It passes in subsequent memory module.
Data of the box average computation after the completion it is necessary to handle are stored in back-end memory, when marking signal is high electricity
The output data of corresponding box averaging module is that n data take box average as a result, this valid data is entered when mean-time clock
Memory is read for host computer.
Below with reference to Fig. 1, book is described in detail to a kind of data processing method of data collection system of the present invention, specifically
The following steps are included:
S1, system initialization
Host computer sends reset signal to data collection system by controller, executes and resets operation, after the completion of reset, on
Position machine sends initializing signal to controller, and control ADC configuration module is each by ADC signal coffret protocol configuration ADC's
Item parameter, completes initialization operation；
In the present embodiment, ADC model AD9265 used, sampling bit wide are 16, sample rate 100M/S, selection
SPI interface protocol mode configures ADC, and into ADC, some registers send configuration order.As sent number toward the address 0x18 of ADC
Then indicate that reference voltage is configured to 2.0V according to 0xC0P-P。
S2, ADC acquisition data and the data reception module for being input to FPGA；
The data of ADC acquisition must satisfy the range of ADC, and the data of acquisition are usually analog signal, need to be converted into count
FPGA is then forwarded to after word signal.
S3, data reception module receive according to the Data Transport Protocol of ADC, parse digital signal, then be input to box
Averaging module；
S4, box averaging module will carry out box average calculating operation to data using multiply-accumulator and the operation of bit wide cut position, it may be assumed thatWherein, SnIndicate parallel data, K indicates that amplification coefficient, Y indicate the bit wide to be clipped, and n indicates to take out
Dot factor；
In the present embodiment, the snap shot coefficient that box averaging module is sent out according to host computer to data reception module be transmitted through come
Data carry out box average treatment, and the formula mainly realized is
Base is 10us when calculating below to assume that user selects, and one lattice of digital storage oscilloscope display points are 100,
The sample rate of ADC is that 100M is example, then snap shot coefficient byIt obtains being 10.Thus method calculates institute's base sometimes
The snap shot coefficient such as column of table 1 the 1st with shown in the 2nd column, by the snap shot coefficient there are in host computer, base when user's selection is different, on
Position machine then sends different snap shot coefficients into box averaging module.
Table 1
The calculation method of amplification coefficient K are as follows:
1), the selection of A.Since when amplification factor A selection is bigger, corresponding 2YAlso bigger, 1/2YValue with regard to smaller,
That is the weight of the least significant bit in K is smaller, it is also smaller to cast out error caused by the decimal place of K in this way, but A selection is bigger,
Bit wide requires bigger, therefore selects lesser A in the case where meeting error condition, selects A for 10000 here.
1) snap shot coefficient 10, is amplified 10000 times, obtaining An is 100000.As shown in the column of table 1 the 3rd, for base shelves sometimes
Under An calculated result；
2), enable multiply-accumulator multiplies accumulating the X that coefficient is value before amplification coefficient is rounded, take with it is 100000 closest normal
Number 2YIt is 217, then basisIt is 13107.1 that X value, which can be calculated,.Such as table 1
4, shown in 5 column, for sometimes under base shelves 2YWith the value of X；
3) decimal, is not present in FPGA, therefore X value is rounded, obtaining amplification coefficient K is 13107, and table 1 the 6th is classified as institute
Sometimes the value of the K under base shelves.By K value there are in the register of box averaging module, multiple selector will be sent according to host computer
Snap shot coefficient select corresponding K value to be sent to multiply-accumulator.
In the present embodiment, multiply-accumulator multiplies accumulating operation using assembly line, and input port includes input multiplier A, B,
Synchronous reset signal SCLR, controls signal SUBTRACT, bypass control signal BYPASS, and clock enables CE, clock signal clk；
The input of A is multiply-accumulator COEFFICIENT K, and the input of B is that data reception module is transmitted through the data come, and controls signal
SUBTRACT is low level, and it is high level that clock enables CE always.The counter controls BYPASS letter that can be changed by counts
Number operation is multiplied accumulating to realize multiply-accumulator using assembly line；
Wherein, the counts of counter are snap shot coefficient 10, and counter generates a FLAG signal, when counting down to 10
FLAG signal is drawn high a clock cycle, recycle d type flip flop by one clock cycle of FLAG signal delay go control multiply it is tired
Add the BYPASS interface of device, is then the high level clock cycle in FLAG, multiply-accumulator output is cumulative 10 times output results.
For the bit wide of multiply-accumulator output data, because it is bit wide needed for accumulative frequency, needed for multiply-accumulator coefficient
The sum of bit wide and data bit width three.Therefore position when maximum bit wide required for multiply-accumulator output is accumulative frequency maximum
Width, as shown in table 2, accumulative frequency are up to 50000, it is possible thereby to determine that the output bit wide of multiply-accumulator is 46.Last root
According to different snap shot coefficients take S [Y+Q-1, Y] just calculated it is box average as a result, table 2 the 6th be classified as export under base sometimes
The correspondence bit wide for needing to choose.When snap shot coefficient is 10, because Y is 17, S [33,17] should be chosen as box flat
Result.
Table 2
S5, the valid data deposit memory after box average calculating operation is taken to read for host computer
Writing for the FLAG signal control memory generated using counter in box averaging module is enabled, is by FLAG signal
When high level clock n data of the output of corresponding box averaging module take it is box average as a result, and using its result as
Valid data enter memory and read for host computer.This is because multiply-accumulator all can all data export always, but as long as working as FLAG
When being high, data are just that n data multiply accumulating result.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the column of protection.
Claims (5)
1. a kind of data processing method of data collection system, which comprises the following steps:
(1), system initialization
Host computer sends reset signal to data collection system by controller, executes and resets operation, after the completion of reset, host computer
Initializing signal, every ginseng that control ADC configuration module passes through ADC signal coffret protocol configuration ADC are sent to controller
Number completes initialization operation；
(2), ADC acquires data and is converted to the data reception module that digital signal is input to FPGA；
(3), data reception module receives according to the Data Transport Protocol of ADC, parses digital signal, then is input to box average
Module；
(4), box averaging module will carry out box average calculating operation to data using multiply-accumulator and the operation of bit wide cut position, it may be assumed thatWherein, SnIndicate the incoming data of data reception module, K indicates amplification coefficient, and Y expression to be clipped
Bit wide, n indicate snap shot coefficient；
(5), the valid data deposit memory after taking box average calculating operation is read for host computer
Writing for the FLAG signal control memory generated using counter module in box averaging module is enabled, is by FLAG signal
The output of corresponding box averaging module is stored in memory as valid data and reads for host computer when high level clock.
2. a kind of data processing method of data collection system according to claim 1, which is characterized in that the snap shot
Coefficient n issues FPGA by host computer calculating again；Wherein, the circular of snap shot coefficient n are as follows:
If base is O seconds when user selects, if one lattice of screen of the system indicate that points are X, then being divided between pointSecond, if
Data sampling rate is that P is per second, then the sampling interval beSecond, then snap shot coefficient is
3. a kind of data processing method of data collection system according to claim 1, which is characterized in that the amplification
The calculation method of COEFFICIENT K are as follows:
(3.1), snap shot coefficient n is amplified A times, obtains An；
(3.2), the coefficient that multiplies accumulating for enabling multiply-accumulator is the value before amplification coefficient is rounded, and is denoted as X, takes and closest normal of An
Number 2Y- 1, then basisCalculate X value；
(3.3), X value is rounded, obtains amplification coefficient K.
4. a kind of data processing method of data collection system according to claim 1, which is characterized in that described multiplying is tired
Device is added to multiply accumulating operation using assembly line, input port includes input multiplier A, B, and synchronous reset signal SCLR controls signal
SUBTRACT, bypass control signal BYPASS, clock enable CE, clock signal clk；
The counter module that can be changed by counts controls BYPASS signal to realize that multiply-accumulator is multiplied accumulating using assembly line
Operation；
Wherein, the counts of counter module are snap shot coefficient n, and counter module generates a FLAG signal, when counting down to n
When FLAG signal is drawn high a clock cycle, recycle d type flip flop by one clock cycle of FLAG signal delay go control multiplies
The BYPASS interface of accumulator is then the high level clock cycle in FLAG, and multiply-accumulator output is the output knot of cumulative n times
Fruit.
5. a kind of data processing method of data collection system according to claim 1, which is characterized in that the bit wide
Cut position operation is intercepted to multiply-accumulator output result, is taken and ADC sampled data since Y that multiply-accumulator exports
The identical bit wide data of bit wide size are as box average output.
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| CN108776249B (en) * | 2018-06-26 | 2020-04-14 | 电子科技大学 | Oscillograph recorder with double capturing functions |
| CN108897264B (en) * | 2018-09-27 | 2020-06-16 | 浙江大学 | Analog-digital converter control device for general system chip |
| CN109510759B (en) * | 2018-10-22 | 2021-08-06 | 智强通达科技（北京）有限公司 | System and method for realizing rapid universal multi-protocol gateway |
| CN113109613A (en) * | 2021-03-17 | 2021-07-13 | 电子科技大学 | Oscillography power analyzer compatible with multiple data acquisition modes |
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