CN107113002B - 振荡器校准 - Google Patents
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Abstract
一种锁相回路,其包括:可控振荡器(102);可变分频器布置(108、110),其从所述可控振荡器(102)获得信号并以可变量划分所述信号以提供较低频率信号;σ‑δ调制器(112),其经布置以将控制输入提供到所述可变分频器布置(108、110);和相位检测器(104),其由所述较低频率信号和参考时钟触发;其中所述锁相回路经布置可以正常模式和校准模式操作,在正常模式中所述可控振荡器(102)由来自所述相位检测器(104)的电压控制,在校准模式中所述可控振荡器(102)由来自从所述可变分频器布置(108、110)接收输入的校准模块(114)的信号用数字方式控制。
Description
技术领域
本发明涉及振荡器校准,特定来说(但非排外地)涉及调谐用于频率合成器中的锁相回路的压控振荡器,例如用于调谐数字无线电传输器和接收器中的应用。
背景技术
压控振荡器(Voltage controlled oscillator;VCO)常用于锁相回路(phaselocked loop;PLL)中。本申请人已了解的VCO问题为当它用于形成用于数字无线电应用的频率合成器的部分的PLL时,它要求在相对大的频率范围(例如,约为数百MHz)上操作。此频率调谐范围可能需要在仅0.6V的电压摆幅内调节,这意味着VCO需要具有极高增益且它因此对回路滤波器噪声敏感。
此敏感度又要求大的滤波器,这暗示需要就集成电路领域来说昂贵的大电容。典型的VCO还展现许多变化:例如其电容可能变化多达15%,这导致中心频率发生改变。
发明内容
本发明旨在提供一种不同方法。
当从第一方面检视时,本发明提供一种锁相回路,其包括:
可控振荡器;
可变分频器布置,其从所述可控振荡器获得信号并以可变量划分所述信号以提供较低频率信号;
σ-δ调制器,其经布置以将控制输入提供到所述可变分频器布置;和
相位检测器,其由所述较低频率信号和参考时钟触发;
其中所述锁相回路经布置可以正常模式和校准模式操作,在正常模式中所述可控振荡器由来自所述相位检测器的电压控制,在校准模式中所述可控振荡器由来自从所述可变分频器布置接收输入的校准模块的信号用数字方式控制。
因此,所属领域的技术人员将看出,根据本发明,可控振荡器能够由校准模块在校准模式中用数字方式控制。此允许实现粗调,从而使得输出频率的电压控制仅需要用于整个频率范围的较小子集内的微调。这又意味着可控振荡器的敏感度能够明显减少,这减少噪声问题。
在校准模式期间操作σ-δ调制器能确保充分分辨率可用于能够在可控振荡器上确证的控制,但在一组实施例中,σ-δ调制器经布置以在所述校准模式期间以不同于所述正常模式期间的模式操作。在一组此类示范性实施例中,σ-δ调制器经布置以在所述校准模式中以二级多段噪声塑形(MASH,例如MASH 1-1)操作,并在所述正常模式中以三级多段噪声塑形(例如,MASH 1-1-1)操作。这反映出本申请人了解到,尽管三级塑形带来低的带内噪声,但它带来将显著干扰校准的极高带外量化噪声。
校准模块可以经布置以在校准期间确定可控振荡器在给定时刻处是运行过快还是过慢,且因此确定从校准模块输出的数字校准信号是要求增加还是降低可控振荡器的频率。然而,本申请人已了解到,此布置将要求延伸于分频器布置与校准模块之间的数据总线,因此这将需要跨越这两个布置之间的不同时钟方案。在一组实施例中,本申请人已通过布置分频器布置以计数来自可控振荡器的脉冲,并将指示振荡器是运行过快还是过慢的信号输出到校准模块来解决此问题。这避免了越过时钟域的需要,因为它准许单线接口而非数据总线。在一组实施例中,分频器布置经布置以在从参考时钟接收到下一过渡边缘时确定其中含有的计数器的状态,并基于所述计数器状态确定可控振荡器频率是过高还是过低。
在一组实施例中,PLL是分数N PLL,亦即所施加划分因数能够变化以带来准确的所要频率。在一组此类示范性实施例中,分频器布置包括可变模数预缩放器(VMP)。分频器布置可以仅依赖于VMP,但在一组实施例中,还提供其它分频器。所述其它分频器可以是固定的,但在一组实施例中,它可以经改变以改变到不同回路频率。
在一组实施例中,PLL经布置以每当需要重置时进入所述校准模式。举例来说,其可以经布置以每当传输或接收新的数据包时,当传输器或接收器经布置以在不同频率通道上操作时,或当***将操作模式从接收改变到传输或反过来时进入所述校准模式。
在一组实施例中,校准模块经布置以执行对分搜索以用于进行数字优化校准。这意味着建立了(例如)多个较低有效位。在一组示范性实施例中,使用五位字。这意味着存在用于PLL的32种可能数字调谐校准,从而使得频率的电压控制仅需要在整个范围的1\32上变化频率,从而带来可控振荡器的敏感度的大大降低(但在实践中频带将通常重叠)。
校准模块优选地包括有限状态机。
在一组实施例中,锁相回路用于数字无线电传输器或接收器的频率合成器中。
附图说明
现将仅借助于实例参考附图来描述本发明的实施例,在附图中图1为体现本发明的锁相回路的示意图。
具体实施方式
图1中展示体现本发明的分数N锁相回路(PLL)。如同任何PLL,这是基于压控振荡器(VCO)102的,所述压控振荡器由相位检测器104经由低通滤波器106控制。在正常使用期间,相位检测器104导致VCO 102的频率进行较小调整,以便使馈送回的信号的相位(且因此频率)与参考时钟CK_REF对准。
可变模数预缩放器(variable modulus pre-scaler;VMP)电路108用于以P或P+1划分频率,这取决于它从其它DIVN分频器模块110中接收的控制信号,在馈送到相位检测器104之前所述分频器模块以其它整数N划分频率。因此,VCO 102的频率被控制到Fref*N*(nP+m(P+1)),其中Fref是参考晶体频率,且n和m是在给定时间周期内相应的计数P和P+1出现的相对比例。
分频器模块110由σ-δ调制器(sigma-delta modulator;SDM)112控制以确定上文所提及的N以及P和P+1计数的相对比例,因此确定精确频率。
经精确划分的平均频率信号被馈送到相位检测器104,所述相位检测器根据来自分频器110的信号与参考时钟输入信号CK_REF之间的任何失配产生输出信号以控制VCO102。
图1中还展示有限状态机(finite state machine;FSM)114。它从DIVN分频器模块110获得输入,并将输出信号提供到可控振荡器102、相位检测器104、SDM 112和DIVN模块110。
在正常使用中,VCO 102的频率经由低通滤波器106由来自相位检测器104的电压信号的改变控制。所述信号又由来自σ-δ调制器112的输出控制,所述σ-δ调制器经由可变调制器预缩放器108和DIVN模块110施加影响。因此,整个频率划分***于两个模块之间。预缩放器108具有可变模数,从而使得它能够取决于来自允许全范围的分数计数的DIVN110的控制信号以P或P+1进行划分。预缩放器108可以是异步或纹波计数器,但这不是必要的。DIVN模块110是计数器,它可以是同步计数器,所述同步计数器在经划分时钟上操作且以由其控制输入所确定的量N划分。所得频率划分因此能够表示为N*P+A,其中A表示在一个输出循环期间VMP 108以P+1划分多少次。
用于VMP 108的输入时钟是由VCO 102的输出提供。VMP 108产生传递到DIVN模块110的中间时钟。来自DIVN模块110的输出是传递到相位检测器104的时钟信号CK_O1。
然而,根据本发明,VCO并不跨越PLL能够产生的整个频率范围受控。实际上,VCO的频率仅能够借助于施加到其的电压在相对窄的频带内变化。
为了确定VCO 102操作的频带,在校准模式期间施加数字调谐。在由FSM起始的此模式中,FSM发出通过固定相位检测器103的输出信号电压而导致VCO 102的频率不再由其输出信号电压控制的控制信号。确切来说,在此模式中,可控振荡器102直接由能够产生用以设定VCO 102的频率的适当二进制控制字的FSM 114控制。控制字信号用于将电容器接入或接出VCO 102中的电路以便变更其基线频率。
在示范性实施例中,FSM 114产生到VCO 102的5位控制字,并从最高有效位到最低有效位进行对最紧密匹配所要频率的控制字的5循环对分搜索。在每一循环期间,调谐字中的一位是由DIVN模块110确定,所述模块当在参考时钟输入CK_REF上接收到过渡边缘时相比于预定预期状态监视其计数器的状态。如果计数过高,则VCO确定为运行过快,且如果计数过低,则VCO确定为运行过慢。DIVN模块110将单位输出发出到FSM 114,所述FSM使用此来适当地设定控制字位以设定VCO 102的频带。
由于计数确定是由分频器模块110自身而非FSM 114进行,因此不必提供越过相应时钟域的数据总线,从而实质上简化电路。
在校准期间,σ-δ调制器112必须继续操作以确保由分频器布置108、110施加的划分因数(亦即,上文描述中的N和A的值)能够变更,这能给予充分频率分辨率。否则,校准目标将限于参考时钟频率的倍数。在典型实例中,参考时钟频率可以是32MHz,然而校准过程的目标准确性大约为5MHz。SDM 112在校准期间是以不同分数N模式运行,以避免高电平的量化噪声并加速校准过程。具体来说,将分数模式从MASH 1-1-1改变到MASH1-1。此移除‘极端’计数值,且因此意味着分频器110并不需要运行许多循环来达到可靠结论(亦即,决定VCO 102是过快还是过慢)。举例来说,它可以在正常模式中从-1运行到+2,而非从-3运行到+4。
一旦已设定用于VCO 102的适当频带,***可以返回到正常模式,其中二进制控制字是固定的,VCO 102由相位检测器104的输出改变控制且SDM恢复到MASH 1-1-1。因此,在此模式中,VCO 102的频率由电压控制但仅跨越窄频带(例如,约为70MHz,而非可以是数百MHz的合成器的全范围)。这意味着相比VCO 102对于跨越整个范围改变其频率的所述电压摆幅原本必需的增益,其仅要求具有低得多的增益。这在使用中明显减少VCO对噪声的敏感度。
举例来说,可以在每次新的数据包待传输或接收时重复所述校准。
Claims (13)
1.一种锁相回路,其包括:
可控振荡器;
可变分频器布置,其从所述可控振荡器获得信号并以可变量划分所述信号以提供较低频率信号;
σ-δ调制器,其经布置以将控制输入提供到所述可变分频器布置;和
相位检测器,其由所述较低频率信号和参考时钟触发;
其中所述锁相回路经布置可以正常模式和校准模式操作,在正常模式中所述可控振荡器由来自所述相位检测器的电压控制,在校准模式中所述可控振荡器由来自从所述可变分频器布置接收输入的校准模块的信号用数字方式控制;
其中所述分频器布置经布置以计数来自所述可控振荡器的脉冲,并将指示所述振荡器是运行过快还是过慢的信号输出到所述校准模块;
其中所述σ-δ调制器经布置以在所述校准模式期间以不同于所述正常模式期间的模式操作。
2.根据权利要求1所述的锁相回路,其中所述σ-δ调制器经布置以在所述校准模式中以二级多段噪声塑形操作,并在所述正常模式中以三级多段噪声塑形操作。
3.根据权利要求2所述的锁相回路,其中所述分频器布置经布置以在从所述参考时钟接收到下一过渡边缘时确定其中含有的计数器的状态,并基于所述计数器状态确定所述可控振荡器频率是过高还是过低。
4.根据权利要求1所述的锁相回路,其中所述锁相回路为分数N锁相回路。
5.根据权利要求1所述的锁相回路,其中所述分频器布置包括可变模数预缩放器(VMP)。
6.根据权利要求5所述的锁相回路,其中所述分频器布置包括其它分频器。
7.根据权利要求6所述的锁相回路,其中所述其它分频器可以经改变以改变到不同回路频率。
8.根据权利要求1所述的锁相回路,所述锁相回路经布置以每当需要重置时进入所述校准模式。
9.根据权利要求8所述的锁相回路,其中所述锁相回路经布置以每当传输或接收新的数据包时,当所述传输器或接收器经布置以在不同频率通道上操作时,或当***将操作模式从接收改变到传输或反过来时进入所述校准模式。
10.根据权利要求1所述的锁相回路,其中所述校准模块经布置以执行对分搜索以用于进行数字优化校准。
11.根据权利要求1所述的锁相回路,其中所述校准模块包括有限状态机。
12.一种频率合成器,其包括根据任一前述权利要求所述的锁相回路。
13.一种数字无线电传输器或接收器,其包括根据权利要求12所述的频率合成器。
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GB1422351.5 | 2014-12-16 | ||
GB1422351.5A GB2533556A (en) | 2014-12-16 | 2014-12-16 | Oscillator calibration |
PCT/GB2015/053972 WO2016097707A1 (en) | 2014-12-16 | 2015-12-14 | Oscillator calibration |
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EP (1) | EP3235136B1 (zh) |
JP (1) | JP2018503309A (zh) |
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CN (1) | CN107113002B (zh) |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1433152A (zh) * | 2002-01-18 | 2003-07-30 | 诺基亚有限公司 | 具有正弦波发生器的小数分频合成器 |
CN1879304A (zh) * | 2003-10-03 | 2006-12-13 | 模拟设备股份有限公司 | 锁相环带宽校准电路及其实现方法 |
CN101218745A (zh) * | 2005-07-14 | 2008-07-09 | 慧国(上海)软件科技有限公司 | 频率合成器的自适应性频率校正器 |
CN102291125A (zh) * | 2010-06-15 | 2011-12-21 | 开曼晨星半导体公司 | 自动校准分数型锁相回路的快速锁相*** |
CN102868395A (zh) * | 2012-10-11 | 2013-01-09 | 广州润芯信息技术有限公司 | 锁相环频率综合器及开环频率粗调方法 |
CN104038215A (zh) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | 一种∑-△分数频率综合器用自动频率校准电路 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6545547B2 (en) * | 2000-08-18 | 2003-04-08 | Texas Instruments Incorporated | Method for tuning a VCO using a phase lock loop |
US6952125B2 (en) * | 2002-10-25 | 2005-10-04 | Gct Semiconductor, Inc. | System and method for suppressing noise in a phase-locked loop circuit |
US6903613B1 (en) * | 2002-12-20 | 2005-06-07 | Cypress Semiconductor Corporation | Voltage controlled oscillator |
US7590387B2 (en) * | 2005-03-18 | 2009-09-15 | Broadcom Corp. | High accuracy voltage controlled oscillator (VCO) center frequency calibration circuit |
EP2267900A1 (en) * | 2005-11-04 | 2010-12-29 | Skyworks Solutions, Inc. | High resolution auto-tuning for a voltage controlled oscillator |
US7538706B2 (en) * | 2007-09-25 | 2009-05-26 | Mediatek Inc. | Mash modulator and frequency synthesizer using the same |
KR101316890B1 (ko) * | 2007-11-08 | 2013-10-11 | 삼성전자주식회사 | 주파수 합성기의 주파수 보정장치 및 그 방법 |
US8461933B2 (en) * | 2010-10-26 | 2013-06-11 | Mediatek Inc. | Device and method for frequency calibration and phase-locked loop using the same |
US8587352B2 (en) | 2011-09-16 | 2013-11-19 | Infineon Technologies Austria Ag | Fractional-N phase locked loop |
GB2498946A (en) * | 2012-01-31 | 2013-08-07 | Texas Instruments Ltd | Fast start-up circuit for phase locked loop (PLL) |
US8953730B2 (en) * | 2012-04-20 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Auto frequency calibration for a phase locked loop and method of use |
US9385769B2 (en) * | 2014-12-05 | 2016-07-05 | Xilinx, Inc. | Phase-locked loop with an adjustable output divider |
KR102375949B1 (ko) * | 2015-01-02 | 2022-03-17 | 삼성전자주식회사 | 주파수 합성기의 출력을 제어하기 위한 장치 및 방법 |
-
2014
- 2014-12-16 GB GB1422351.5A patent/GB2533556A/en not_active Withdrawn
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- 2015-12-14 EP EP15813517.8A patent/EP3235136B1/en active Active
- 2015-12-14 CN CN201580068496.9A patent/CN107113002B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1433152A (zh) * | 2002-01-18 | 2003-07-30 | 诺基亚有限公司 | 具有正弦波发生器的小数分频合成器 |
CN1879304A (zh) * | 2003-10-03 | 2006-12-13 | 模拟设备股份有限公司 | 锁相环带宽校准电路及其实现方法 |
CN101218745A (zh) * | 2005-07-14 | 2008-07-09 | 慧国(上海)软件科技有限公司 | 频率合成器的自适应性频率校正器 |
CN102291125A (zh) * | 2010-06-15 | 2011-12-21 | 开曼晨星半导体公司 | 自动校准分数型锁相回路的快速锁相*** |
CN102868395A (zh) * | 2012-10-11 | 2013-01-09 | 广州润芯信息技术有限公司 | 锁相环频率综合器及开环频率粗调方法 |
CN104038215A (zh) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | 一种∑-△分数频率综合器用自动频率校准电路 |
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TW201633719A (zh) | 2016-09-16 |
WO2016097707A1 (en) | 2016-06-23 |
EP3235136B1 (en) | 2018-12-05 |
EP3235136A1 (en) | 2017-10-25 |
KR20170094431A (ko) | 2017-08-17 |
GB2533556A (en) | 2016-06-29 |
US20170346496A1 (en) | 2017-11-30 |
CN107113002A (zh) | 2017-08-29 |
JP2018503309A (ja) | 2018-02-01 |
US10230382B2 (en) | 2019-03-12 |
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