CN107099840B - A kind of preparation method of transient voltage suppressor silicon epitaxial wafer - Google Patents
A kind of preparation method of transient voltage suppressor silicon epitaxial wafer Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 71
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 71
- 239000010703 silicon Substances 0.000 title claims abstract description 71
- 230000001052 transient effect Effects 0.000 title claims abstract description 23
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 43
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 60
- 239000001257 hydrogen Substances 0.000 claims description 60
- 229910052739 hydrogen Inorganic materials 0.000 claims description 60
- 238000010926 purge Methods 0.000 claims description 56
- 239000007789 gas Substances 0.000 claims description 52
- 229910003822 SiHCl3 Inorganic materials 0.000 claims description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 16
- 238000009826 distribution Methods 0.000 claims description 16
- 239000002994 raw material Substances 0.000 claims description 15
- 238000005498 polishing Methods 0.000 claims description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 229910002804 graphite Inorganic materials 0.000 claims description 10
- 239000010439 graphite Substances 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 claims description 8
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 8
- 238000011109 contamination Methods 0.000 claims description 5
- 230000006698 induction Effects 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000006641 stabilisation Effects 0.000 claims description 5
- 238000011105 stabilization Methods 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 229910001385 heavy metal Inorganic materials 0.000 claims description 2
- 241000719178 Carangoides ruber Species 0.000 claims 1
- 238000007664 blowing Methods 0.000 claims 1
- 235000008429 bread Nutrition 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 5
- 239000003595 mist Substances 0.000 abstract description 5
- 238000000407 epitaxy Methods 0.000 abstract description 4
- 238000005457 optimization Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 6
- 238000005282 brightening Methods 0.000 description 3
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 3
- 229910052753 mercury Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- -1 phosphorus Alkane Chemical class 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/20—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Abstract
The invention discloses a kind of preparation methods of transient voltage suppressor silicon epitaxial wafer.The problem of this preparation method is adjusted by gas flowfield, pedestal thermal field and the optimization of epitaxy technique, overcomes thickness present in existing transient voltage suppressor silicon epitaxial wafer technique and resistivity evenness control.The control to substrate impurity self-diffusion process is realized by the optimization of epitaxy technique, ensure that the thickness of silicon epitaxial wafer and the high uniformity of resistivity, the defects of surface is without fault, dislocation, skid wire, mist.2% is respectively less than using the thickness and resistivity inhomogeneities of the silicon epitaxial wafer of this method preparation；The thickness mean value range of silicon epitaxial wafer is 6.10-6.25 μm, and resistivity mean value range is 1.25-1.35 Ω cm, to meet the requirement of transient voltage suppressor.
Description
Technical field
The present invention relates to the fabricating technology of semiconductor epitaxial material more particularly to a kind of transient voltage suppressors
With the preparation method of silicon epitaxial wafer.
Background technique
With the development of electronic information technology, semiconductor devices small, densification and multifunction, this will
It asks the response device time fast, meets the transmission of High-Speed Data Line, guarantee the glitch by multiple voltage and current again
Device performance will not deteriorate afterwards.Transient voltage suppressor is developed in this market application requirement, is a kind of
The high-efficiency of diode protects device, for protecting sensitive semiconductor device, keeps it broken from transient voltage surge
It is bad, with junction capacity is small, the response time is short, transient power is big, clamp voltage is easy to control, breakdown voltage deviation is small, leakage current
Small and high reliability, thus be widely used on voltage transient and carrying out surge protection.
Silicon epitaxial wafer is the key basic material for preparing transient voltage suppressor, thickness and the resistivity ginseng of epitaxial layer
Number decides the breakdown voltage and conducting resistance of device, especially thickness, the uniformity of resistivity has pole to the quality of device
For important influence.It is thinner thickness the characteristics of epitaxial layer as needed for transient voltage suppressor, but resistivity is higher.
Therefore the uniformity that slight self-diffusion of the impurity of substrate in solid phase and gas phase will be distributed the resistivity of epitaxial layer causes
It influences, to influence the capacitance parameter of device.Therefore the self-diffusion of substrate impurity is realized and is effectively inhibited, guarantee extension layer parameter
Uniformity be the key that successfully to prepare transient voltage suppressor silicon epitaxial wafer.
Summary of the invention
The purpose of the present invention is overcome existing transient voltage suppressor silicon epitaxial wafer present in the preparation process
The problem of thickness and resistivity evenness control by gas flowfield, is reacted the adjusting of thermal field and the optimization of epitaxy technique, is obtained
A kind of preparation method of transient voltage suppressor high uniformity silicon epitaxial wafer is obtained, so that meeting transient voltage inhibits two poles
The requirement of pipe.
The technical solution adopted by the present invention is that: a kind of preparation method of transient voltage suppressor silicon epitaxial wafer,
It is characterized in that there are following steps:
(1), first by 9 groups of the bottom end setting of the induction coil below rotation epitaxial furnace graphite base apart from adjustable
Adjusting rod jacks up or drags down the position of coil, spacing between each part of adjustment coil and graphite base, and then adjusts base
The thermal field distributing homogeneity of seat realizes the control to the uniformity of silicon epitaxial wafer thickness and resistivity；9 groups of adjusting rods are named respectively
For 4#-12#, it is -10 that wherein the scale value setting range of 4# adjusting rod, which is the scale value setting range of -6~-10,5# adjusting rod,
The scale value setting range of~-15,6# adjusting rod is that the scale value setting range of -25~-30,7# adjusting rod is -25~-30,
The scale value setting range of 8# adjusting rod is that the scale value setting range of 0~+3,9# adjusting rod is -25~-30,10# adjusting rod
Scale value setting range be the scale value setting range of -25~-30,11# adjusting rod be the scale value of 0~+3,12# adjusting rod
Setting range is 0~+3；
(2), extension furnace foundation seat is corroded using the HCl gas of purity >=99.99%, is completely removed residual on pedestal
Remaining deposited material, etching temperature are set as 1080-1100 DEG C, and HCl gas flow is set as 30-35 L/min, and etch period is set
It is set to 3-5 min；It regrows one layer of non-impurity-doped polysilicon to pedestal immediately after the completion of etching, growth raw material SiHCl3, gas
Body flow set is 5-6 L/min, and growth time is set as 5-6 min；
(3), it is packed into silicon monocrystalline substrate piece into extension furnace foundation seat piece hole, successively the nitrogen using purity >=99.999%
With hydrogen purge epitaxial furnace reaction cavity, gas flow is set as 100-120 L/min, and purge time is set as 8-10 min；
(4), it is polished using surface of the HCl gas to silicon monocrystalline substrate piece, HCl flow set is 1-3 L/min, is thrown
Light temperature is set as 1060-1080 DEG C, and polishing time is set as 1-3 min；
(5), the hydrogen of service life variable-flow purges epitaxial furnace reaction cavity, and substrate impurity is constantly diluted
And cavity is excluded, hydrogen flowing quantity variation range is set as 150-230 L/min, and hydrogen flowing quantity rises to 230 from 150 L/min
L/min, time are set as 1-2 min, and the gas purging of 230 L/min, the time is set as 3-5 min, then by hydrogen flowing quantity
150 L/min are dropped to from 230 L/min, the time is set as 1-2 min, the gas purging of 150 L/min, and the time is set as 1-
3 min complete a variable-flow purge, need to carry out 1-2 variable-flow purge in total；
(6), the air-flow on the air inlet of left, center, right three before outer layer growth, by rotating epitaxial furnace reaction cavity
Adjusting knob carrys out the intracorporal H of distribution cavity2Throughput, and then the intracorporal Flow Field Distribution of epitaxial furnace reaction chamber is adjusted, it realizes outside to silicon
Prolong the adjusting of piece the thickness uniformity, the throughput adjustable range of arranged on left and right sides air inlet is 19-30 L/min；
(7), SiHCl3As growth raw material, first in silicon monocrystalline substrate piece surface fast-growth intrinsic epitaxial layer, with suppression
The self-diffusion process of substrate impurity processed, hydrogen flowing quantity are set as 140-160 L/min, SiHCl3Flow set is 4-7 L/min,
Growth time is set as 40-60 sec, and growth temperature is set as 1060-1080 DEG C；
(8), epitaxial furnace reaction cavity is purged with the hydrogen of periodical variable-flow again, substrate impurity is further
Cavity is diluted and excludes, hydrogen flowing quantity variation range is set as 150-230 L/min, and hydrogen flowing quantity rises from 150 L/min
To 230 L/min, the time is set as 1-2 min, and the gas purging of 230 L/min, the time is set as 3-5 min, then by hydrogen
Throughput drops to 150 L/min from 230 L/min, and the time is set as 1-2 min, the gas purging of 150 L/min, and the time sets
It is set to 1-3 min, completes the process of variable-flow purging, needs to carry out 1-2 variable-flow purge in total；
(9), SiHCl is utilized3The growth of epitaxial layer is doped as growth raw material, growth temperature is set as 1060-
1080 DEG C, hydrogen flowing quantity is set as 140-160 L/min, SiHCl3Flow set is 5-6 L/min, and phosphine flow set is
113-117 sccm, SiHCl3Pipeline evacuation is first passed through in advance with phosphine, realizes the stabilization of gas concentration, it is anti-subsequently into epitaxial furnace
Cavity is answered to carry out outer layer growth, emptying time is set as 0.5-3.0min, and the growth time of epitaxial layer is set as
4min30sec-4min40sec；
(10), start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 100-120 L/min, according to
Secondary purging epitaxial furnace reaction cavity 10-12 min, then takes out silicon epitaxial wafer from pedestal.
Epitaxial furnace used in the present invention is the flat epitaxial furnace of PE3061D type normal pressure.
Silicon monocrystalline substrate piece used in the present invention uses the single-sided polishing piece of<111>crystal orientation, resistivity 0.002-0.004
Ω cm, the silicon monocrystalline substrate piece back side are coated with the back envelope oxide layer of 4000-6000.
When the present invention is polished after load using surface of the HCl gas to silicon monocrystalline substrate piece, HCl goes to surface
Except amount is 0.1-0.3 μm, to completely remove the heavy metal ion and contamination that are attached to silicon monocrystalline substrate piece surface.
The beneficial effects of the present invention are: a kind of preparation method of transient voltage suppressor silicon epitaxial wafer is provided,
It is adjusted by gas flowfield, pedestal thermal field and the optimization of epitaxy technique realizes the control to substrate impurity self-diffusion process,
It ensure that the high uniformity of silicon epitaxial wafer, the defects of surface is without fault, dislocation, skid wire, mist.Outside silicon using this method preparation
The thickness and resistivity inhomogeneities for prolonging piece are respectively less than 2%；The thickness Change in Mean range of the silicon epitaxial wafer of preparation is 6.10-
6.25 μm, resistivity Change in Mean range is 1.25-1.35 Ω cm, and the use for meeting transient voltage suppressor is wanted
It asks.
Detailed description of the invention
Fig. 1 is 5 distribution maps (right side) of 5 distribution maps (left side) of thickness and resistivity in the piece of embodiment 1；
Fig. 2 is 5 distribution maps (right side) of 5 distribution maps (left side) of thickness and resistivity in the piece of embodiment 2；
Fig. 3 is 5 distribution maps (right side) of 5 distribution maps (left side) of thickness and resistivity in the piece of embodiment 3.
Specific embodiment
Below in conjunction with attached drawing, detailed description of the preferred embodiments:
Outer layer growth equipment used in following embodiment of the present invention is the flat epitaxial furnace of PE3061D type normal pressure, extension
Furnace foundation seat revolving speed is controlled in 4 r/min.Silicon monocrystalline substrate piece uses the silicon single-sided polishing piece of<111>crystal orientation, resistivity 0.003
Ω cm, the silicon monocrystalline substrate piece back side are coated with 5000 back envelope oxide layer.
Embodiment 1
(1) bottom end of the induction coil below epitaxial furnace graphite base is equipped with 9 groups apart from adjustable adjusting rod, names respectively
For 4#-12#, the position of coil, each part of adjustment coil and graphite base are jacked up or dragged down first by rotation adjusting lever
Between spacing, and then improve the thermal field distributing homogeneity of pedestal, the scale value of 4# adjusting rod is set as -10,5# adjusting rod
The scale value that the scale value that scale value is set as -15,6# adjusting rod is set as -30,7# adjusting rod is set as -30,8# adjusting rod
Scale value be set as+3,9# adjusting rod scale value be set as -30,10# adjusting rod scale value be set as -30,11# adjusting
The scale value that the scale value of bar is set as+3,12# adjusting rod is set as+3.
(2) extension furnace foundation seat is corroded first with the HCl gas of purity >=99.99%, is completely removed residual on pedestal
Remaining deposited material, etching temperature are set as 1080 DEG C, and HCl gas flow is set as 35 L/min, and etch period is set as 3
min.It regrows one layer of non-impurity-doped polysilicon to pedestal immediately after the completion of etching, growth raw material SiHCl3, flow set 5
L/min, growth time are set as 5 min.
(3) be packed into silicon monocrystalline substrate piece into extension furnace foundation seat piece hole, successively using purity >=99.999% nitrogen and
Hydrogen purge epitaxial furnace reaction cavity, gas flow are set as 100 L/min, and purge time is 8 min.
(4) it is polished using surface of the HCl gas to silicon monocrystalline substrate piece, HCl flow set is 1 L/min, polishing
Temperature is set as 1070 DEG C, and polishing time is set as 1 min, and HCl is 0.2 μm to the removal amount on surface.
(5) hydrogen of service life variable-flow purges epitaxial furnace reaction cavity, and substrate impurity is constantly diluted
And cavity is excluded, hydrogen flowing quantity variation range is set as 150 ~ 230 L/min, and hydrogen flowing quantity rises to 230 from 150 L/min
L/min, time are set as 1 min, and the gas purging of 230 L/min, the time is set as 3 min, then by hydrogen flowing quantity from 230
L/min drops to 150 L/min, and the time is set as 1 min, the gas purging of 150 L/min, and the time is set as 1 min, completes
Variable-flow purge carries out 2 variable-flow purges in total.
(6) air-flow on the air inlet of left, center, right three before outer layer growth, by rotating epitaxial furnace reaction cavity
Adjusting knob carrys out the intracorporal H of distribution cavity2Throughput, and then the intracorporal Flow Field Distribution of epitaxial furnace reaction chamber is adjusted, it realizes outside to silicon
Prolong the adjusting of piece the thickness uniformity, the throughput of arranged on left and right sides air inlet is set as 19 L/min.
(7) SiHCl is used3As growth raw material, first in silicon monocrystalline substrate piece surface fast-growth intrinsic epitaxial layer, with
Inhibit the self-diffusion process of substrate impurity, hydrogen flowing quantity is set as 150 L/min, SiHCl3Flow set is 5 L/min, growth
Time is set as 40 sec, and growth temperature is set as 1070 DEG C.
(8) epitaxial furnace reaction cavity is purged with the hydrogen of periodical variable-flow again, substrate impurity is further
Cavity is diluted and excludes, hydrogen flowing quantity variation range is set as 150 ~ 230 L/min, and hydrogen flowing quantity rises from 150 L/min
To 230 L/min, the time is set as 1 min, and the gas purging of 230 L/min, the time is set as 3min, then by hydrogen flowing quantity
150 L/min are dropped to from 230 L/min, the time is set as 1 min, the gas purging of 150 L/min, and the time is set as 1
Min completes a variable-flow purge, carries out 2 variable-flow purges in total.
(9) SiHCl is utilized3The growth of epitaxial layer is doped as growth raw material, growth temperature is set as 1070 DEG C, hydrogen
Throughput is set as 150 L/min, SiHCl3Flow set is 5 L/min, and phosphine flow set is 115 sccm, SiHCl3With
Phosphine first passes through pipeline evacuation in advance, realizes the stabilization of gas concentration, carries out outer layer growth subsequently into epitaxial furnace reaction cavity,
Emptying time is set as 1min, the growth time of epitaxial layer is set as 4min30sec.
(10) start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 100 L/min, successively purged
10 min of epitaxial furnace reaction chamber, then takes out silicon epitaxial wafer from pedestal.
(11) it is measured using thickness of Fourier's infrared tester to silicon epitaxial wafer, records center point and four
Position away from 10 mm of edge amounts to the thickness of five test points, obtains thickness mean value and inhomogeneities, is surveyed using mercury probe CV
Examination instrument measures the resistivity of silicon epitaxial wafer, and records center point and four positions away from 10 mm of edge amount to five
The resistivity of test point obtains resistivity mean value and inhomogeneities.
Silicon epitaxial wafer surface-brightening made from embodiment 1, no road plan, fault, dislocation, skid wire, mist, orange peel, contamination etc.
Surface defect, thickness mean value are 6.12 μm, and inhomogeneities 1.53%, resistivity mean value is 1.33 Ω cm, and inhomogeneities is
1.55%, test results are shown in figure 1.
Embodiment 2
(1) bottom end of the induction coil below epitaxial furnace graphite base is equipped with 9 groups apart from adjustable adjusting rod, names respectively
For 4#-12#, the position of coil, each part of adjustment coil and graphite base are jacked up or dragged down first by rotation adjusting lever
Between spacing, and then improve the thermal field distributing homogeneity of pedestal, the scale value of 4# adjusting rod is set as the quarter of -8,5# adjusting rod
The scale value that the scale value that angle value is set as -10,6# adjusting rod is set as -30,7# adjusting rod is set as -28,8# adjusting rod
The scale value that the scale value that scale value is set as+2,9# adjusting rod is set as -28,10# adjusting rod is set as -28,11# adjusting rod
Scale value be set as the scale value of 0,12# adjusting rod and be set as 0.
(2) extension furnace foundation seat is corroded using the HCl gas of purity >=99.99%, completely removes the remnants on pedestal
Deposited material, etching temperature are set as 1090 DEG C, and HCl gas flow is set as 35 L/min, and HCl etch period is set as 3
min.It regrows one layer of non-impurity-doped polysilicon to pedestal immediately after the completion of etching, growth raw material SiHCl3, flow set 5
L/min, growth time are set as 6 min.
(3) be packed into silicon monocrystalline substrate piece into extension furnace foundation seat piece hole, successively using purity >=99.999% nitrogen and
Hydrogen purge epitaxial furnace reaction cavity, gas flow are set as 100 L/min, and purge time is set as 10 min.
(4) HCl polishing is carried out to the surface of silicon substrate film, HCl flow set is 1 L/min, and polish temperature is set as
1070 DEG C, polishing time is set as 1 min, and HCl is 0.2 μm to the removal amount on surface.
(5) hydrogen of service life variable-flow purges epitaxial furnace reaction cavity, and substrate impurity is constantly diluted
And cavity is excluded, hydrogen flowing quantity variation range is 150-230 L/min, and hydrogen flowing quantity rises to 230 L/ from 150 L/min
Min, time are set as 1 min, and the gas purging of 230 L/min, the time is set as 3 min, then by hydrogen flowing quantity from 230
L/min drops to 150 L/min, and the time is set as 1 min, the gas purging of 150 L/min, and the time is set as 1 min, completes
Variable-flow purge carries out 2 variable-flow purges in total.
(6) air-flow on the air inlet of left, center, right three before outer layer growth, by rotating epitaxial furnace reaction cavity
Adjusting knob carrys out the intracorporal H of distribution cavity2Throughput, and then the intracorporal Flow Field Distribution of epitaxial furnace reaction chamber is adjusted, it realizes outside to silicon
Prolong the adjusting of piece the thickness uniformity, the throughput of arranged on left and right sides air inlet is 21 L/min.
(7) SiHCl is used3As growth raw material, first in silicon monocrystalline substrate piece surface fast-growth intrinsic epitaxial layer, with
Inhibit the self-diffusion process of substrate impurity, hydrogen flowing quantity is set as 150 L/min, SiHCl3Flow set is 5 L/min, growth
Time is set as 40 sec, and growth temperature is set as 1070 DEG C.
(8) epitaxial furnace reaction cavity is purged with the hydrogen of periodical variable-flow again, substrate impurity is constantly dilute
Cavity is released and excludes, hydrogen flowing quantity variation range is set as 150 ~ 230 L/min, and hydrogen flowing quantity rises to from 150 L/min
230 L/min, time are set as 1 min, and the gas purging of 230 L/min, the time is set as 3 min, then by hydrogen flowing quantity
150 L/min are dropped to from 230 L/min, the time is set as 1 min, the gas purging of 150 L/min, and the time is set as 1
Min completes a variable-flow purge, carries out 2 variable-flow purges in total.
(9) SiHCl is utilized3The growth of epitaxial layer is doped as growth raw material, growth temperature is set as 1070 DEG C, hydrogen
Throughput is controlled in 150 L/min, SiHCl3Flow set is 5L/min, and phosphine flow set is 117 sccm, SiHCl3And phosphorus
Alkane first passes through pipeline evacuation in advance, realizes the stabilization of gas concentration, and emptying time is set as 1 min, and the growth time of epitaxial layer is set
It is set to 4min30sec.
(10) start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 100 L/min, successively purged
12 min of epitaxial furnace reaction cavity, then takes out silicon epitaxial wafer from pedestal.
(11) it is measured using thickness of Fourier's infrared tester to silicon epitaxial wafer, records center point and four
Position away from 10 mm of edge amounts to the thickness of five test points, obtains thickness mean value and inhomogeneities, is surveyed using mercury probe CV
Examination instrument measures the resistivity of silicon epitaxial wafer, and records center point and four positions away from 10 mm of edge amount to five
The resistivity of test point obtains resistivity mean value and inhomogeneities.
Silicon epitaxial wafer surface-brightening made from embodiment 2, no road plan, fault, dislocation, skid wire, mist, orange peel, contamination etc.
Surface defect, thickness mean value are 6.16 μm, and inhomogeneities 0.64%, resistivity mean value is 1.30 Ω cm, and inhomogeneities is
1.22%, test results are shown in figure 2.
Embodiment 3
(1) bottom end of the induction coil below epitaxial furnace graphite base is equipped with 9 groups apart from adjustable adjusting rod, names respectively
For 4#-12#, the position of coil, each part of adjustment coil and graphite base are jacked up or dragged down first by rotation adjusting lever
Between spacing, and then improve the thermal field distributing homogeneity of pedestal, the scale value of 4# adjusting rod is set as -10,5# adjusting rod
The scale value that the scale value that scale value is set as -10,6# adjusting rod is set as -27,7# adjusting rod is set as -27,8# adjusting rod
Scale value be set as+1,9# adjusting rod scale value be set as -28,10# adjusting rod scale value be set as -26,11# adjusting
The scale value that the scale value of bar is set as+2,12# adjusting rod is set as+2.
(2) extension furnace foundation seat is corroded using the HCl gas of purity >=99.99%, completely removes the remnants on pedestal
Deposited material, etching temperature are set as 1080 DEG C, and HCl gas flow is set as 35 L/min, and HCl etch period is set as 5
min.It regrows one layer of non-impurity-doped polysilicon to pedestal immediately after the completion of etching, growth raw material SiHCl3, flow set 5
L/min, growth time are set as 5 min.
(3) be packed into silicon monocrystalline substrate piece into extension furnace foundation seat piece hole, successively using purity >=99.999% nitrogen and
Hydrogen purge epitaxial furnace reaction cavity, gas flow are set as 100 L/min, and purge time is 8 min.
(4) it is polished using surface of the HCl gas to silicon monocrystalline substrate piece, HCl flow set is 1 L/min, polishing
Temperature is set as 1080 DEG C, and polishing time is set as 1 min, and HCl is 0.25 μm to the removal amount on surface.
(5) hydrogen of service life variable-flow purges epitaxial furnace reaction cavity, and substrate impurity is constantly diluted
And cavity is excluded, hydrogen flowing quantity variation range is set as 150-230 L/min, and hydrogen flowing quantity rises to 230 from 150 L/min
L/min, time are set as 1 min, and the gas purging of 230 L/min, the time is set as 3 min, then by hydrogen flowing quantity from 230
L/min drops to 150 L/min, and the time is set as 1min, the gas purging of 150 L/min, and the time is set as 1 min, completes
Variable-flow purge carries out 2 variable-flow purges in total.
(6) air-flow on the air inlet of left, center, right three before outer layer growth, by rotating epitaxial furnace reaction cavity
Adjusting knob carrys out the intracorporal H of distribution cavity2Throughput, and then the intracorporal Flow Field Distribution of epitaxial furnace reaction chamber is adjusted, it realizes outside to silicon
Prolong the adjusting of piece the thickness uniformity, the throughput of arranged on left and right sides air inlet is 22 L/min；
(7) SiHCl is used3For growth raw material, first in silicon monocrystalline substrate piece surface fast-growth intrinsic epitaxial layer, with suppression
The self-diffusion process of substrate impurity processed, hydrogen flowing quantity are set as 150 L/min, SiHCl3Flow set is 4L/min, when growth
Between be set as 40 sec, growth temperature is set as 1070 DEG C.
(8) epitaxial furnace reaction cavity is purged with the hydrogen of periodical variable-flow again, substrate impurity is further
Cavity is diluted and excludes, hydrogen flowing quantity variation range is set as 150-230 L/min, and hydrogen flowing quantity rises from 150 L/min
To 230 L/min, the time is set as 2 min, and the gas purging of 230 L/min, the time is set as 5 min, then by hydrogen stream
Amount drops to 150 L/min from 230 L/min, and the time is set as 2 min, the gas purging of 150 L/min, and the time is set as 3
Min completes the process of variable-flow purging, needs to carry out 2 variable-flow purges in total.
(9) SiHCl is utilized3The growth of epitaxial layer is doped as growth raw material, growth temperature is set as 1070 DEG C, hydrogen
Throughput is controlled in 140L/min, SiHCl3Flow set is 5 L/min, and phosphine flow set is 113 sccm, SiHCl3And phosphorus
Alkane first passes through pipeline evacuation in advance, realizes the stabilization of gas concentration, carries out outer layer growth, row subsequently into epitaxial furnace reaction cavity
The empty time is set as 1 min, and the growth time of epitaxial layer is set as 4min30sec.
(10) start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 100L/min, successively purged
Epitaxial furnace reaction cavity 10min, then takes out silicon epitaxial wafer from pedestal.
(11) it is measured using thickness of Fourier's infrared tester to silicon epitaxial wafer, records center point and four
Position away from 10 mm of edge amounts to the thickness of five test points, obtains silicon epitaxial wafer thickness mean value and inhomogeneities, utilizes mercury
Probe CV tester measures the resistivity of silicon epitaxial wafer, records center point and four positions away from 10 mm of edge,
The resistivity of total five test points, obtains silicon epitaxial wafer resistivity mean value and inhomogeneities.
Silicon epitaxial wafer surface-brightening made from embodiment 3, no road plan, fault, dislocation, skid wire, mist, orange peel, contamination etc.
Surface defect, thickness mean value are 6.21 μm, and inhomogeneities 0.39%, resistivity mean value is 1.32 Ω cm, and inhomogeneities is
0.63%, test results are shown in figure 3.
Compared with embodiment 1, embodiment 2, embodiment 3 passes through the gas flow for setting higher arranged on left and right sides air inlet
And 2 variable-flow purges are all made of before each outer layer growth, therefore obtained silicon epitaxial wafer inhomogeneities refers to
Mark optimal, inhomogeneities is less than 1%.Therefore, embodiment 3 is highly preferred embodiment of the present invention.
Claims (4)
1. a kind of preparation method of transient voltage suppressor silicon epitaxial wafer, which is characterized in that there is following steps:
(1), first by 9 groups of the bottom end setting of the induction coil below rotation epitaxial furnace graphite base apart from adjustable adjusting
Bar jacks up or drags down the position of coil, spacing between each part of adjustment coil and graphite base, and then adjusts pedestal
Thermal field distributing homogeneity realizes the control to the uniformity of silicon epitaxial wafer thickness and resistivity；9 groups of adjusting rods are respectively designated as
4#-12#, wherein the scale value setting range of 4# adjusting rod be the scale value setting range of -6~-10,5# adjusting rod be -10~-
The scale value setting range of 15,6# adjusting rods is that the scale value setting range of -25~-30,7# adjusting rod is -25~-30,8# tune
The scale value setting range of pole is the quarter that the scale value setting range of 0~+3,9# adjusting rod is -25~-30,10# adjusting rod
Angle value setting range is that the scale value setting range of -25~-30,11# adjusting rod is the scale value setting of 0~+3,12# adjusting rod
Range is 0~+3；
(2), extension furnace foundation seat is corroded using the HCl gas of purity >=99.99%, the remnants completely removed on pedestal are heavy
Product substance, etching temperature are set as 1080-1100 DEG C, and HCl gas flow is set as 30-35 L/min, and etch period is set as
3-5 min；It regrows one layer of non-impurity-doped polysilicon to pedestal immediately after the completion of etching, growth raw material SiHCl3, gas stream
Amount is set as 5-6 L/min, and growth time is set as 5-6 min；
(3), it is packed into silicon monocrystalline substrate piece into extension furnace foundation seat piece hole, successively the nitrogen and hydrogen using purity >=99.999%
Epitaxial furnace reaction cavity is swept in air-blowing, and gas flow is set as 100-120 L/min, and purge time is set as 8-10 min；
(4), it is polished using surface of the HCl gas to silicon monocrystalline substrate piece, HCl flow set is 1-3 L/min, polishing temperature
Degree is set as 1060-1080 DEG C, and polishing time is set as 1-3 min；
(5), the hydrogen of service life variable-flow purges epitaxial furnace reaction cavity, and substrate impurity is constantly diluted side by side
Except cavity, hydrogen flowing quantity variation range are set as 150-230 L/min out, hydrogen flowing quantity rises to 230 L/ from 150 L/min
Min, time are set as 1-2 min, and the gas purging of 230 L/min, the time is set as 3-5 min, then by hydrogen flowing quantity from
230 L/min drop to 150 L/min, and the time is set as 1-2 min, the gas purging of 150 L/min, and the time is set as 1-3
Min completes a variable-flow purge, needs to carry out 1-2 variable-flow purge in total；
(6), before outer layer growth, the air-flow on the air inlet of left, center, right three by rotating epitaxial furnace reaction cavity is adjusted
Knob carrys out the intracorporal H of distribution cavity2Throughput, and then the intracorporal Flow Field Distribution of epitaxial furnace reaction chamber is adjusted, it realizes to silicon epitaxial wafer
The adjusting of the thickness uniformity, the throughput adjustable range of arranged on left and right sides air inlet are 19-30 L/min；
(7), SiHCl3As growth raw material, first in silicon monocrystalline substrate piece surface fast-growth intrinsic epitaxial layer, to inhibit substrate
The self-diffusion process of impurity, hydrogen flowing quantity are set as 140-160 L/min, SiHCl3Flow set is 4-7 L/min, when growth
Between be set as 40-60 sec, growth temperature is set as 1060-1080 DEG C；
(8), epitaxial furnace reaction cavity is purged with the hydrogen of periodical variable-flow again, substrate impurity is further diluted
And cavity is excluded, hydrogen flowing quantity variation range is set as 150-230 L/min, and hydrogen flowing quantity rises to 230 from 150 L/min
L/min, time are set as 1-2 min, and the gas purging of 230 L/min, the time is set as 3-5 min, then by hydrogen flowing quantity
150 L/min are dropped to from 230 L/min, the time is set as 1-2 min, the gas purging of 150 L/min, and the time is set as 1-
3 min complete the process of variable-flow purging, need to carry out 1-2 variable-flow purge in total；
(9), SiHCl is utilized3The growth of epitaxial layer is doped as growth raw material, growth temperature is set as 1060-1080 DEG C,
Hydrogen flowing quantity is set as 140-160 L/min, SiHCl3Flow set is 5-6 L/min, and phosphine flow set is 113-117
Sccm, SiHCl3First pass through pipeline evacuation in advance with phosphine, realize the stabilization of gas concentration, subsequently into epitaxial furnace reaction cavity into
Row outer layer growth, emptying time are set as 0.5-3.0min, and the growth time of epitaxial layer is set as 4min30sec-
4min40sec；
(10), start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 100-120 L/min, successively blown
Epitaxial furnace reaction cavity 10-12 min is swept, then takes out silicon epitaxial wafer from pedestal.
2. a kind of preparation method of transient voltage suppressor silicon epitaxial wafer according to claim 1, feature exist
In epitaxial furnace used is the flat epitaxial furnace of PE3061D type normal pressure.
3. a kind of preparation method of transient voltage suppressor silicon epitaxial wafer according to claim 1, feature exist
In silicon monocrystalline substrate piece used uses the silicon single-sided polishing piece of<111>crystal orientation, and resistivity is 0.002-0.004 Ω cm, back
Bread is covered with the back envelope oxide layer of 4000-6000.
4. a kind of preparation method of transient voltage suppressor silicon epitaxial wafer according to claim 1, feature exist
In when being polished after load using surface of the HCl gas to silicon monocrystalline substrate piece, HCl is 0.1- to the removal amount on surface
0.3 μm, to completely remove the heavy metal ion and contamination that are attached to silicon monocrystalline substrate piece surface.
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Application publication date: 20170829 Assignee: CLP Jinghua (Tianjin) semiconductor materials Co.,Ltd. Assignor: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO.46 Research Institute Contract record no.: X2024980004262 Denomination of invention: A method for preparing silicon epitaxial wafers for transient voltage suppression diodes Granted publication date: 20190524 License type: Common License Record date: 20240415 |