CN107093586A - The encapsulating structure and method for packing of a kind of chip - Google Patents
The encapsulating structure and method for packing of a kind of chip Download PDFInfo
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- CN107093586A CN107093586A CN201710448280.6A CN201710448280A CN107093586A CN 107093586 A CN107093586 A CN 107093586A CN 201710448280 A CN201710448280 A CN 201710448280A CN 107093586 A CN107093586 A CN 107093586A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000012856 packing Methods 0.000 title claims abstract description 33
- 230000006698 induction Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000001681 protective effect Effects 0.000 claims abstract description 21
- 238000004806 packaging method and process Methods 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 238000005520 cutting process Methods 0.000 claims description 17
- 238000005728 strengthening Methods 0.000 claims description 17
- 239000003292 glue Substances 0.000 claims description 9
- 229910010272 inorganic material Inorganic materials 0.000 claims description 3
- 239000011147 inorganic material Substances 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims description 3
- 239000012780 transparent material Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 238000002834 transmittance Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 42
- 238000005538 encapsulation Methods 0.000 description 12
- 238000012545 processing Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 230000009467 reduction Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000009738 saturating Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000741 silica gel Substances 0.000 description 2
- 229910002027 silica gel Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of chip-packaging structure and method for packing, the encapsulating structure includes：Chip to be packaged, the chip to be packaged includes relative first surface and second surface；The first surface has the weld pad of induction zone first, and first weld pad is electrically coupled with the induction zone；Cover the enhancement layer of the first surface of the chip to be packaged；The solder-bump of the second surface of the chip to be packaged is arranged on, the solder-bump is electrically connected with first weld pad, and for being electrically connected with external circuit.Because the first surface of chip to be packaged increases enhancement layer, when being cut after protective substrate removal, the surface of chip to be packaged can be avoided to sustain damage and pollute, and the enhancement layer can also increase the intensity of structure to be packaged.
Description
Technical field
The present invention relates to the encapsulating structure and method for packing of technical field of manufacturing semiconductors, more particularly to a kind of chip.
Background technology
With the continuous development of scientific technology, increasing electronic equipment is originally widely used in daily life
And be that daily life and work bring huge facility among work, it is indispensable as current people
Important tool.
The development trend of electronic equipment is miniaturization and portability.Determine electronics miniaturization and portability one
Principal element is the encapsulation design of electronic equipment chips.Traditional chip packaging method is typically using wire bonding (Wire
Bonding) it is packaged, but developing rapidly with integrated circuit, longer lead causes product size to be unable to reach ideal
Requirement, therefore, wafer-level packaging (WLP：Wafer Level Package) gradually substitution wire bond package turn into it is a kind of compared with
For conventional method for packing.Wafer level packaging is that the skill for cutting into single chip after test again is packaged to full wafer wafer
Art, the chip size and nude film after encapsulation is completely the same.Wafer-level packaging has the following advantages that：Can be to multiple wafers simultaneously
Processing, packaging efficiency is high；The test of full wafer wafer is carried out before cutting, the test process in encapsulation is reduced, and reduction is tested into
This；Encapsulation chip has light, small, short, thin advantage.
When being packaged in existing wafer-level packaging method to chip, in order to protect chip surface in encapsulation process not
It is damaged and pollutes, it usually needs in crystal column surface one protective substrate of formation to protect wafer, encapsulates after terminating, in addition it is also necessary to
By protective substrate glass, the wafer after finally cutting encapsulation obtains the encapsulating structure of multiple simple grain chips.
However, after prior art in advance peels off protective substrate and wafer, still may in the processing steps such as follow-up cutting
Chip surface is caused to sustain damage and pollute, and the intensity of the encapsulating structure of chip is also weaker.
The content of the invention
In order to solve the above problems, the invention provides a kind of encapsulating structure of chip and method for packing, by treating
The first surface increase enhancement layer of chip is encapsulated, when being cut after protective substrate removal, chip to be packaged can be avoided
Surface sustains damage and polluted, and the enhancement layer can also increase the intensity of structure to be packaged.
To achieve these goals, the present invention provides following technical scheme：
A kind of encapsulating structure of chip, the encapsulating structure includes：
Chip to be packaged, the chip to be packaged includes relative first surface and second surface；The first surface
With induction zone and the first weld pad, first weld pad is electrically coupled with the induction zone；
Cover the enhancement layer of the first surface of the chip to be packaged；
It is arranged on the solder-bump of the second surface of the chip to be packaged, the solder-bump and first weld pad electricity
Connection, and for being electrically connected with external circuit.
It is preferred that, in above-mentioned encapsulating structure, the hardness of the enhancement layer is more than 6H.
It is preferred that, in above-mentioned encapsulating structure, the enhancement layer is organic material or inorganic material.
It is preferred that, in above-mentioned encapsulating structure, the chip to be packaged is capacitive induction chip, Jie of the enhancement layer
Electric constant is more than 3, and the enhancement layer is insulating materials.
It is preferred that, in above-mentioned encapsulating structure, the chip to be packaged is photosensitive cake core, and the enhancement layer is transparent material
Material.
It is preferred that, in above-mentioned encapsulating structure, the light transmittance of the enhancement layer is more than 80%.
It is preferred that, in above-mentioned encapsulating structure, the thickness range of the enhancement layer is 2 μm -40 μm, including endpoint value.
It is preferred that, in above-mentioned encapsulating structure, in addition to：The chip to be packaged is arranged on away from the enhancement layer side
Strengthening course, the strengthening course be located at the encapsulating structure outermost.
It is preferred that, in above-mentioned encapsulating structure, the compensation layer can be plastic packaging glue.
It is preferred that, in above-mentioned encapsulating structure, the second surface of the chip to be packaged is provided through described to be packaged
The via of chip, the via is used to expose first weld pad；
The solder-bump is electrically connected by the wiring layer again being arranged in the via with first weld pad.
It is preferred that, in above-mentioned encapsulating structure, the via is the bilayer step hole of exposure first weld pad；
The via includes：The groove of the chip second surface to be packaged is arranged on, the depth of groove is less than described
The thickness of chip to be packaged；In the groove, and through the through hole of the chip to be packaged, the through hole and described first
Weld pad is corresponded, and the through hole is used to expose corresponding first weld pad.
It is preferred that, in above-mentioned encapsulating structure, the via is the inverted trapezoidal hole of exposure first weld pad；
The via is on the direction for pointing to the second surface by the first surface, and the aperture of the via gradually increases
Greatly.
It is preferred that, in above-mentioned encapsulating structure, the via is the straight hole of exposure first weld pad.
It is preferred that, in above-mentioned encapsulating structure, the chip side wall to be packaged has oblique cut, and the oblique cut makes
Obtain the second surface and be less than the first surface, with the first weld pad described in expose portion；
The solder-bump is electrically connected by being arranged on the wiring layer again on the oblique cut surface with first weld pad.
Present invention also offers a kind of method for packing of chip, the method for packing includes：
A wafer is provided, the wafer includes the chip to be packaged of multiple array arrangements；Each described chip to be packaged
With relative first surface and second surface；The first surface has induction zone and the first weld pad, first weldering
Pad is electrically coupled with the induction zone；The first surface of all chips to be packaged is located at the same side of the wafer；
Enhancement layer is formed on the surface of the wafer side, the enhancement layer covers the first of all chips to be packaged
Surface；
The enhancement layer is fitted fixation with a protective substrate；
Solder-bump is formed on the surface of the wafer opposite side, the second surface of each chip to be packaged is all provided with
The solder-bump is equipped with, the solder-bump is electrically connected with first weld pad, and for being electrically connected with external circuit；
The wafer and the enhancement layer are split by cutting technique, the encapsulation knot of multiple chips to be packaged is formed
Structure；
Peel off the protective substrate.
It is preferred that, it is described that the enhancement layer is fitted fixed include with a protective substrate in above-mentioned method for packing：
The enhancement layer is fitted fixation with the protective substrate by UV glue.
It is preferred that, in above-mentioned method for packing, before cutting technique is carried out, in addition to：
Strengthening course is formed away from the side of the enhancement layer in the wafer, the strengthening course is located at the encapsulating structure
Outermost.
It is preferred that, in above-mentioned method for packing, the surface in the wafer opposite side, which forms solder-bump, to be included：
Run through the via of the wafer in the second surface formation of each chip to be packaged, the via is used to reveal
Go out first weld pad；
Form the insulating barrier for covering the chip second surface to be packaged and the via sidewall, the insulating layer exposing
First weld pad；
Form the wiring layer again for covering the via bottom and the insulating barrier；
The solder-bump, the solder-bump and the sensing of the chip to be packaged are formed in the layer surface that connects up again
Area is oppositely arranged.
It is preferred that, in above-mentioned method for packing, the second surface formation in each chip to be packaged runs through
The via of the wafer includes：
The bilayer step hole of exposure first weld pad is formed in the second surface of the chip to be packaged；
The via includes：The groove of the chip second surface to be packaged is arranged on, the depth of groove is less than described
The thickness of chip to be packaged；In the groove, and through the through hole of the chip to be packaged, the through hole and described first
Weld pad is corresponded, and the through hole is used to expose corresponding first weld pad.
It is preferred that, in above-mentioned method for packing, the second surface formation in each chip to be packaged runs through
The via of the wafer includes：
The inverted trapezoidal hole of exposure first weld pad is formed in the second surface of the chip to be packaged；
The via is on the direction for pointing to the second surface by the first surface, and the aperture of the via gradually increases
Greatly.
It is preferred that, in above-mentioned method for packing, the second surface formation in each chip to be packaged runs through
The via of the wafer includes：
The straight hole of exposure first weld pad is formed in the second surface of the chip to be packaged.
It is preferred that, in above-mentioned method for packing, the surface in the wafer opposite side, which forms solder-bump, to be included：
In the side wall formation oblique cut of the chip to be packaged, the oblique cut causes the second surface to be less than institute
First surface is stated, with exposure first weld pad；
The insulating barrier for the second surface for covering the oblique cut and the chip to be packaged is formed, the insulating barrier is sudden and violent
Reveal first weld pad；
Form the wiring layer again for covering first weld pad and the insulating barrier；
The solder-bump, the solder-bump and the sensing of the chip to be packaged are formed in the layer surface that connects up again
Area is oppositely arranged.
The chip-packaging structure and method for packing provided by foregoing description, technical solution of the present invention is to be packaged
The first surface of chip sets enhancement layer, and solder-bump is set in second surface, passes through the first of solder-bump and first surface
Weld pad is electrically connected, in order to be electrically connected with external circuit.It can be seen that, the first surface that technical solution of the present invention passes through chip to be packaged
Increase enhancement layer, when being cut after protective substrate removal, the surface of chip to be packaged can be avoided to sustain damage and dirty
Dye, and the enhancement layer can also increase the intensity of structure to be packaged.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is a kind of structural representation of the encapsulating structure of chip provided in an embodiment of the present invention；
Fig. 2 is the structural representation of the encapsulating structure of another chip provided in an embodiment of the present invention；
Fig. 3 is the structural representation of the encapsulating structure of another chip provided in an embodiment of the present invention；
Fig. 4 is the structural representation of the encapsulating structure of another chip provided in an embodiment of the present invention；
Fig. 5 is a kind of schematic flow sheet of method for packing provided in an embodiment of the present invention；
Fig. 6-Figure 14 b are a kind of technological principle schematic diagram of method for packing provided in an embodiment of the present invention；
Figure 15-Figure 18 is the technological principle schematic diagram of another method for packing provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
It should be noted that the purpose for providing these accompanying drawings is to help to understand embodiments of the invention, without answering
It is construed to the improper restriction to the present invention.For the sake of becoming apparent from, size is not necessarily to scale shown in figure, may be put
Greatly, reduce or other changes.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.In addition,
Fisrt feature described below second feature it " on " structure can be formed as direct contact including the first and second features
Embodiment, embodiment of the other feature formation between the first and second features, such first and second can also be included
Feature may not be direct contact.
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
With reference to Fig. 1, Fig. 1 is a kind of structural representation of the encapsulating structure of chip provided in an embodiment of the present invention, the encapsulation
Structure includes：Chip 10 to be packaged, the chip 10 to be packaged includes relative first surface and second surface；Covering is described
The enhancement layer 30 of the first surface of chip 10 to be packaged；It is arranged on the solder-bump 127 of the second surface of the chip to be packaged.
Wherein, the first surface has induction zone A and the first weld pad 200, first weld pad 200 and the sensing
Area A is electrically coupled.First weld pad 200, which is arranged on, to be surrounded in the encapsulation region B of the induction zone A；The solder-bump 127 and described the
One weld pad 200 is electrically connected, and for being electrically connected with external circuit.
The hardness of the enhancement layer 30 is more than 6H.In encapsulating structure described in the embodiment of the present invention, in chip 10 to be packaged
First surface sets the enhancement layer 300 that hardness is more than 6H so that encapsulating structure hardness is higher, and mechanical strength is big.
The enhancement layer 30 can be organic material or inorganic material.Enhancement layer 30 can be by hardening as described
The silica gel of reason.Silica gel after solidification has preferable temperature tolerance, weatherability and electrical insulation properties, ensure that encapsulating structure
With longer service life.
The induction zone of the chip to be packaged 10 is provided with the pixel 100 of multiple array arrangements.The chip to be packaged
10 can be capacitive induction chip, such as can be fingerprint recognition chip.Now, the dielectric constant of the enhancement layer 30 is more than 3,
And the enhancement layer 30 is insulating materials, capacitance variations recognize finger print information caused by being touched according to finger.Now, touched in finger
When touching the enhancement layer 30 on induction zone A surfaces, pixel 100 is used to recognize finger print information according to capacitance variations.
In other embodiment, the chip 10 to be packaged can also be photosensitive cake core, now, for the ease of pixel
100 sensing optical informations, it is transparent material to set the enhancement layer 30.Now, the chip to be packaged 10 can be image sensing
Chip, the pixel 100 is used to sense by the incident optical information of transparent enhancement layer 30, is generated and schemed according to the optical information
As information.When the chip 10 to be packaged is photosensitive cake core, in order to ensure image quality, the saturating of the enhancement layer 30 is set
Light rate is more than 80%.
In order to ensure that enhancement layer has preferable sealing effectiveness, the thickness range for setting the enhancement layer 30 is 2 μm of -40 μ
M, including endpoint value, effectively to isolate steam, protect pixel 100.
General, when being packaged to chip 10 to be packaged, in order to obtain the encapsulating structure of lower thickness, it is necessary to treat
The second surface for encapsulating chip 10 carries out reduction processing, specifically, can pass through the modes pair such as mechanical lapping or chemical etching
The second surface of chip 10 to be packaged carries out reduction processing.But, the machinery of the chip to be packaged 10 after reduction processing is strong
Degree is weaker.In order to further enhance the mechanical strength of encapsulating structure, the encapsulating structure also includes being arranged on the chip to be packaged
10 deviate from the strengthening course of the side of enhancement layer 30, and the strengthening course is located at the outermost of the encapsulating structure.Not shown in Fig. 1
The strengthening course.
In encapsulating structure described in the embodiment of the present invention, the mechanical strength of strengthening course is more than the strong of the substrate of chip 10 to be packaged
Degree.It can to treat that the thickness of sealing chip 10 is thinner by being thinned, and mechanical strength is increased by strengthening course, it is to be packaged reducing
While 10 thickness of chip, it is ensured that its encapsulating structure has preferable mechanical strength.That is, being sealed described in the embodiment of the present invention
Assembling structure, relative to encapsulating structure of the prior art, can further increase reduction processing reduces the thickness of chip 10 to be packaged
Degree so that the thickness of chip 10 to be packaged is thinner, the machinery after reduction processing is compensated by the more preferable strengthening course of mechanical strength strong
Degree, it is possible to achieve encapsulating structure it is lightening.Optionally, the strengthening course can be plastic packaging glue.
The second surface of the chip to be packaged 10 is provided through the via of the chip to be packaged 10, and the via is used
In exposing first weld pad 200, in order to realize the electrical connection of solder-bump 127 and first weld pad 200.
In the embodiment shown in fig. 1, the via is bilayer step via, and now the via is described including being arranged on
The groove K1 of the second surface of chip 10 to be packaged and in the groove K1, and through the through hole of the chip 10 to be packaged
K2.Groove K1 depth is less than the thickness of chip 10 to be packaged, not through chip 10 to be packaged；Formed on the basis of groove K1
Through hole K2, runs through the chip 10 to be packaged, to expose first weld pad 200 by through hole K2.The through hole K2 with it is described
First weld pad 200 is corresponded, and the through hole K2 is used to expose corresponding first weld pad 200.
As shown in figure 1, the solder-bump 127 passes through the wiring layer again 124 and described first that is arranged in the via
Weld pad 200 is electrically connected.
Also there is insulating barrier 123 between the wiring layer again 124 and the chip to be packaged 10.The insulating barrier 123 covers
The side wall of the via is built, and exposes the bottom of the via, in order to which the weld pad 200 of wiring layer 124 and first is electrically connected again.Institute
State again bottom and the insulating barrier 123 that wiring layer 124 covers the via.Solder-bump 127 is located at the insulating barrier 123
Surface.Specifically, being additionally provided with solder mask 125 on the surface of wiring layer again 124, the surface of solder mask 125, which has, is provided with weldering
The opening of projection 127 is connect, in order to set solder-bump 127 so that the electricity of wiring layer again 124 at solder-bump 127 and opening
Connection.
With reference to Fig. 2, Fig. 2 is the structural representation of the encapsulating structure of another chip provided in an embodiment of the present invention, Fig. 2 institutes
Show that encapsulating structure is with encapsulating structure difference shown in Fig. 1, in encapsulating structure shown in Fig. 2, the via is exposure described first
The inverted trapezoidal hole K3 of weld pad 200.The opening of the inverted trapezoidal via K3 is more than its bottom surface.Perpendicular to the chip 10 to be packaged
Direction on, the tangent plane of the via is inverted trapezoidal hole K3.Now, the via is pointing to described second by the first surface
On the direction on surface, the aperture of the via gradually increases.The via can be truncation centrum or terrace with edge.
With reference to Fig. 3, Fig. 3 is the structural representation of the encapsulating structure of another chip provided in an embodiment of the present invention, Fig. 3 institutes
Show that encapsulating structure is with encapsulating structure difference shown in Fig. 1, in encapsulating structure shown in Fig. 3, the via is exposure described first
The straight hole K4 of weld pad 200.On the direction perpendicular to the chip 10 to be packaged, the tangent plane of the via is straight hole K4, is
Rectangle.Specifically, straight hole K4 can be cylindrical or prismatic via.Now, the via refers to by the first surface
To on the direction of the second surface, the aperture of the via is gradually constant.The via can for circular hole or delthyrium or
Square hole etc..
It is that first weld pad 200 is exposed by via, in order to cause in the encapsulating structure shown in Fig. 1-Fig. 3
Solder-bump 127 is electrically connected with the first weld pad 200 by wiring layer 124 again.In other embodiments, via is not provided with also may be used
To cause solder-bump 127 to be electrically connected with the first weld pad 200, as shown in Figure 4.
With reference to Fig. 4, Fig. 4 is the structural representation of the encapsulating structure of another chip provided in an embodiment of the present invention, Fig. 3 institutes
Show that encapsulating structure is with encapsulating structure difference shown in Fig. 1, in encapsulating structure shown in Fig. 3, the side wall tool of chip 10 to be packaged
There is oblique cut Q, the oblique cut Q causes the second surface to be less than the first surface, with described in expose portion first
Weld pad 200；The solder-bump 127 is by being arranged on the wiring layer again 124 on the oblique cut Q surfaces and first weld pad
200 electrical connections.On the direction perpendicular to the chip 10 to be packaged, the side wall of chip 10 to be packaged has oblique cut Q.
The oblique cut Q can be formed by etching or laser cutting or mechanical lapping.
By foregoing description, in encapsulating structure described in the embodiment of the present invention, in the first surface of chip 10 to be packaged
Enhancement layer 30 is set, solder-bump 127 is set in second surface, passes through solder-bump 127 and the first weld pad 200 of first surface
Electrical connection, in order to be electrically connected with external circuit.Shown in formed during encapsulating structure, pass through the of chip 10 to be packaged
One surface increases enhancement layer 30, when being cut after protective substrate removal, can avoid the surface of chip 10 to be packaged by
Damage and pollution, and the enhancement layer 30 can also increase the intensity of structure to be packaged.
Based on above-mentioned encapsulating structure embodiment, another embodiment of the present invention additionally provides a kind of method for packing, the encapsulation
Method is as shown in figure 5, Fig. 5 is a kind of schematic flow sheet of method for packing provided in an embodiment of the present invention, and the method for packing is used for
The encapsulating structure described in above-described embodiment is formed, the method for packing includes：
Step S11：There is provided a wafer 21 as shown in Fig. 6 and Fig. 7, the wafer treating including multiple array arrangements is sealed
Cartridge chip 10.
Wherein, Fig. 7 is sectional drawing of the wafer shown in Fig. 6 in PP ' directions, and wafer 21 has relative first surface and the
Two surfaces.Wafer 21 includes the chip to be packaged 10 of multiple array arrangements.Each chip 10 to be packaged has multiple for pixel
Point 100.Pixel 100 is located at first surface.There is cutting raceway groove 22, in order to follow-up between adjacent chip to be packaged 10
Cutting process is carried out in cutting technique.
Each described chip 10 to be packaged has relative first surface and second surface.The first surface has
The induction zone A and encapsulation region B for surrounding the induction zone A.The encapsulation region B, which has, is used for the first weld pad 200 that circuit is interconnected,
First weld pad 200 is electrically coupled with the induction zone A.The first surface of all chips to be packaged is located at the wafer 21
The same side.In the embodiment of the present invention, first weld pad 200 is electrically coupled mark first weld pad 200 with the induction zone A
Electrically connected with multiple electrical parts in the induction zone A.
Step S12：As shown in figure 8, forming enhancement layer 30 on the surface of the side of wafer 21, the enhancement layer 30 is covered
The first surface of all chips 10 to be packaged.
The enhancement layer 30 can be formed by injection (molding) technique of semiconductor packaging process.
Step S13：As shown in figure 9, the enhancement layer 30 is fitted fixation with a protective substrate 20.
It is described that the enhancement layer 30 is fitted fixed include with a protective substrate 20 in the step：By UV glue 31 by institute
State enhancement layer 30 to fit with the protective substrate 20 fixation, in order to the stripping of follow-up glue-line 31 and the enhancement layer 30.Using
UV glue 31 with UV light-sensitive characteristics fixes the enhancement layer 30 and the protective substrate as interim bonded layer, when UV light is saturating
When overprotection substrate 20 is irradiated to UV glue 31, UV glue 31 will lose viscosity, in order to will be by the enhancement layer 30 and the protection
Substrate 20 is separated.
Step S14：Solder-bump is formed on the surface of the wafer opposite side.
The second surface of each chip to be packaged is provided with the solder-bump, the solder-bump with it is described
First weld pad is electrically connected, and for being electrically connected with external circuit.
In step S14, the surface in the wafer opposite side, which forms solder-bump, to be included：
First, each chip to be packaged second surface formation through the wafer via, the via
For exposing first weld pad.Illustrated exemplified by forming encapsulating structure shown in Fig. 1, now, as shown in Figure 10, it is described
The second surface formation of each chip to be packaged includes through the via of the wafer：In the chip 10 to be packaged
Second surface forms the bilayer step hole of exposure first weld pad.Now the via includes being arranged on the chip to be packaged
The groove K1 of 10 second surfaces and in the groove K1, and through the through hole K2 of the chip 10 to be packaged.Groove K1
Depth be less than chip 10 to be packaged thickness, not through chip 10 to be packaged；Through hole K2 is formed on the basis of groove K1, is led to
Through hole K2 is crossed through the chip 10 to be packaged, to expose first weld pad 200.The through hole K2 and first weld pad
200 correspond, and the through hole K2 is used to expose corresponding first weld pad 200.
Further, as shown in figure 11, formed and cover the second surface of chip 10 to be packaged and the via sidewall
Insulating barrier 123, the insulating barrier 123 exposes first weld pad 200.
Further, as shown in figure 12, wiring layer 124 again of the covering via bottom and the insulating barrier 123 are formed.
Finally, as shown in figure 13, the solder-bump 127, the solder-bump are formed on the surface of wiring layer again 124
127 are oppositely arranged with the induction zone of the chip 10 to be packaged.Covering is initially formed before the solder-bump 127 is formed described
The solder mask 125 of wiring layer 124 again, solder mask 125 has opening, is open for exposed portion wiring layer 124 again, is opened described
The solder-bump 127 is formed at mouthful.
Step S15：A as shown in figure 14, along the cutting raceway groove 22 of the wafer, splits the wafer by cutting technique
And the enhancement layer, form the encapsulating structure of multiple chips to be packaged.
Step S16：As shown in fig. 14b, the protective substrate 20 is peeled off.
For Figure 10-Figure 14 b illustrated embodiments, final rear formation encapsulating structure as shown in Figure 1.
In other embodiment, the second surface formation in each chip to be packaged is through the wafer
The second surface that via is included in the chip to be packaged forms the inverted trapezoidal hole of exposure first weld pad, the via by
The first surface is pointed on the direction of the second surface, and the aperture of the via gradually increases.The via can be to cut
Push up centrum or terrace with edge.Now, encapsulating structure as shown in Figure 2 is formed after cutting.
In other embodiment, the second surface formation in each chip to be packaged is through the wafer
The second surface that via is included in the chip to be packaged forms the straight hole for exposing first weld pad, and the via is by described
First surface is pointed on the direction of the second surface, and the aperture of the via is gradually constant.The via can for circular hole or
Delthyrium or square hole etc..Now, encapsulating structure as shown in Figure 3 is formed after cutting.
In Figure 10-Figure 14 illustrated embodiments, welding projection is realized by setting the via through chip 10 to be packaged
127 and first weld pad 200 electrical connection.In other embodiments, can also be realized by oblique cut welding projection 127 with
The electrical connection of first weld pad 200, now in step S14, the surface in the wafer opposite side, which forms solder-bump, to be included：
First, as shown in figure 15, the enhancement layer 30 is fitted with the protective substrate 20 after fixing, waits to seal described
Side wall formation the oblique cut Q, the oblique cut Q of cartridge chip 10 cause the second surface to be less than the first surface, with
Exposure first weld pad 200.
Then, as shown in figure 16, the second surface of the covering oblique cut Q and the chip to be packaged 10 is formed
Insulating barrier 123, the insulating barrier 123 exposes first weld pad 200.
Further, as shown in figure 17, connecting up again for covering first weld pad 200 and the insulating barrier 123 is formed
Layer 124.
Finally, as shown in figure 18, the solder-bump 127, the solder-bump are formed on the surface of wiring layer again 124
127 are oppositely arranged with the induction zone A of the chip 10 to be packaged.Equally, it is initially formed and covers before the solder-bump 127 is formed
The solder mask 125 of the lid wiring layer 124 again, solder mask 125 is open for exposed portion wiring layer 124 again with opening,
The solder-bump 127 is formed at the opening.Enhancement layer 30 is cut along cutting raceway groove.After cutting, form as shown in Figure 4
Encapsulating structure.
In order to further strengthen the mechanical strength of encapsulating structure, method for packing described in the embodiment of the present invention also includes：Institute
State wafer and form strengthening course away from the side of the enhancement layer.Specific strengthening course can be located at chip to be packaged and insulating barrier it
Between, or covering solder mask, positioned at the outer surface of encapsulating structure.
By foregoing description, method for packing described in the embodiment of the present invention can be used for being formed described in above-described embodiment
Encapsulating structure, packaging technology is simple, low manufacture cost, and the encapsulating structure of formation has stronger mechanical strength.
The embodiment of each in this specification is described by the way of progressive, and what each embodiment was stressed is and other
Between the difference of embodiment, each embodiment identical similar portion mutually referring to.For being encapsulated disclosed in embodiment
For method, because it is corresponding with encapsulating structure disclosed in embodiment, so description is fairly simple, related part is referring to envelope
Assembling structure appropriate section illustrates.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (22)
1. a kind of encapsulating structure of chip, it is characterised in that including：
Chip to be packaged, the chip to be packaged includes relative first surface and second surface；The first surface has
Induction zone and the first weld pad, first weld pad are electrically coupled with the induction zone；
Cover the enhancement layer of the first surface of the chip to be packaged；
The solder-bump of the second surface of the chip to be packaged is arranged on, the solder-bump is electrically connected with first weld pad
Connect, and for being electrically connected with external circuit.
2. encapsulating structure according to claim 1, it is characterised in that the hardness of the enhancement layer is more than 6H.
3. encapsulating structure according to claim 1, it is characterised in that the enhancement layer is organic material or inorganic material
Material.
4. encapsulating structure according to claim 1, it is characterised in that the chip to be packaged is capacitive induction chip,
The dielectric constant of the enhancement layer is more than 3, and the enhancement layer is insulating materials.
5. encapsulating structure according to claim 1, it is characterised in that the chip to be packaged is photosensitive cake core, described
Enhancement layer is transparent material.
6. encapsulating structure according to claim 5, it is characterised in that the light transmittance of the enhancement layer is more than 80%.
7. encapsulating structure according to claim 1, it is characterised in that the thickness range of the enhancement layer is 2 μm -40 μm,
Including endpoint value.
8. encapsulating structure according to claim 1, it is characterised in that also include：The chip to be packaged is arranged on to deviate from
The strengthening course of the enhancement layer side, the strengthening course is located at the outermost of the encapsulating structure.
9. encapsulating structure according to claim 8, it is characterised in that the compensation layer can be plastic packaging glue.
10. encapsulating structure according to claim 1, it is characterised in that the second surface of the chip to be packaged is provided with
Through the via of the chip to be packaged, the via is used to expose first weld pad；
The solder-bump is electrically connected by the wiring layer again being arranged in the via with first weld pad.
11. encapsulating structure according to claim 10, it is characterised in that the via is double for exposure first weld pad
Layer stepped hole；
The via includes：The groove of the chip second surface to be packaged is arranged on, the depth of groove is waited to seal less than described
The thickness of cartridge chip；In the groove, and through the through hole of the chip to be packaged, the through hole and first weld pad
Correspond, the through hole is used to expose corresponding first weld pad.
12. encapsulating structure according to claim 10, it is characterised in that the via falls for exposure first weld pad
Trapezoidal hole；
The via is on the direction for pointing to the second surface by the first surface, and the aperture of the via gradually increases.
13. encapsulating structure according to claim 10, it is characterised in that the via is straight for exposure first weld pad
Hole.
14. encapsulating structure according to claim 1, it is characterised in that the chip side wall to be packaged has oblique cut,
The oblique cut causes the second surface to be less than the first surface, with the first weld pad described in expose portion；
The solder-bump is electrically connected by being arranged on the wiring layer again on the oblique cut surface with first weld pad.
15. a kind of method for packing of chip, it is characterised in that including：
A wafer is provided, the wafer includes the chip to be packaged of multiple array arrangements；Each described chip to be packaged has
Relative first surface and second surface；The first surface has induction zone and the first weld pad, first weld pad with
The induction zone is electrically coupled；The first surface of all chips to be packaged is located at the same side of the wafer；
Enhancement layer is formed on the surface of the wafer side, the enhancement layer covers the first table of all chips to be packaged
Face；
The enhancement layer is fitted fixation with a protective substrate；
Solder-bump is formed on the surface of the wafer opposite side, the second surface of each chip to be packaged is provided with
The solder-bump, the solder-bump is electrically connected with first weld pad, and for being electrically connected with external circuit；
The wafer and the enhancement layer are split by cutting technique, the encapsulating structure of multiple chips to be packaged is formed；
Peel off the protective substrate.
16. method for packing according to claim 15, it is characterised in that described to paste the enhancement layer and a protective substrate
Closing fixation includes：
The enhancement layer is fitted fixation with the protective substrate by UV glue.
17. method for packing according to claim 15, it is characterised in that before cutting technique is carried out, in addition to：
Strengthening course is formed away from the side of the enhancement layer in the wafer, the strengthening course is located at the outermost of the encapsulating structure
Side.
18. method for packing according to claim 15, it is characterised in that the surface in the wafer opposite side is formed
Solder-bump includes：
Run through the via of the wafer in the second surface formation of each chip to be packaged, the via is used to expose institute
State the first weld pad；
The insulating barrier for covering the chip second surface to be packaged and the via sidewall is formed, described in the insulating layer exposing
First weld pad；
Form the wiring layer again for covering the via bottom and the insulating barrier；
The solder-bump, the solder-bump and the induction zone phase of the chip to be packaged are formed in the layer surface that connects up again
To setting.
19. method for packing according to claim 18, it is characterised in that described the of each chip to be packaged
The formation of two surfaces includes through the via of the wafer：
The bilayer step hole of exposure first weld pad is formed in the second surface of the chip to be packaged；
The via includes：The groove of the chip second surface to be packaged is arranged on, the depth of groove is waited to seal less than described
The thickness of cartridge chip；In the groove, and through the through hole of the chip to be packaged, the through hole and first weld pad
Correspond, the through hole is used to expose corresponding first weld pad.
20. method for packing according to claim 18, it is characterised in that described the of each chip to be packaged
The formation of two surfaces includes through the via of the wafer：
The inverted trapezoidal hole of exposure first weld pad is formed in the second surface of the chip to be packaged；
The via is on the direction for pointing to the second surface by the first surface, and the aperture of the via gradually increases.
21. method for packing according to claim 18, it is characterised in that described the of each chip to be packaged
The formation of two surfaces includes through the via of the wafer：
The straight hole of exposure first weld pad is formed in the second surface of the chip to be packaged.
22. method for packing according to claim 15, it is characterised in that the surface in the wafer opposite side is formed
Solder-bump includes：
In the side wall formation oblique cut of the chip to be packaged, the oblique cut causes the second surface to be less than described the
One surface, with exposure first weld pad；
Form the insulating barrier for the second surface for covering the oblique cut and the chip to be packaged, the insulating layer exposing institute
State the first weld pad；
Form the wiring layer again for covering first weld pad and the insulating barrier；
The solder-bump, the solder-bump and the induction zone phase of the chip to be packaged are formed in the layer surface that connects up again
To setting.
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| CN201710448280.6A CN107093586B (en) | 2017-06-14 | 2017-06-14 | Packaging structure and packaging method of chip |
| US15/950,302 US10541186B2 (en) | 2017-06-14 | 2018-04-11 | Chip package and chip packaging method |
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| CN201710448280.6A CN107093586B (en) | 2017-06-14 | 2017-06-14 | Packaging structure and packaging method of chip |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107863363A (en) * | 2017-11-20 | 2018-03-30 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of chip and preparation method thereof |
| CN108010890A (en) * | 2017-12-29 | 2018-05-08 | 苏州晶方半导体科技股份有限公司 | Chip-packaging structure and method |
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| CN108063126A (en) * | 2017-12-29 | 2018-05-22 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and method for packing of a kind of chip |
| CN109192706A (en) * | 2018-09-07 | 2019-01-11 | 苏州晶方半导体科技股份有限公司 | A kind of chip-packaging structure and chip packaging method |
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| WO2019128398A1 (en) * | 2017-12-29 | 2019-07-04 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and manufacturing method therefor |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102163582A (en) * | 2010-02-12 | 2011-08-24 | 精材科技股份有限公司 | Chip package |
| CN104201115A (en) * | 2014-09-12 | 2014-12-10 | 苏州晶方半导体科技股份有限公司 | Wafer-level fingerprint recognition chip packaging structure and method |
| CN105244339A (en) * | 2015-10-10 | 2016-01-13 | 苏州晶方半导体科技股份有限公司 | Packaging method for image sensor chip and packaging structure |
| CN207250481U (en) * | 2017-06-14 | 2018-04-17 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure of chip |
-
2017
- 2017-06-14 CN CN201710448280.6A patent/CN107093586B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102163582A (en) * | 2010-02-12 | 2011-08-24 | 精材科技股份有限公司 | Chip package |
| CN104201115A (en) * | 2014-09-12 | 2014-12-10 | 苏州晶方半导体科技股份有限公司 | Wafer-level fingerprint recognition chip packaging structure and method |
| CN105244339A (en) * | 2015-10-10 | 2016-01-13 | 苏州晶方半导体科技股份有限公司 | Packaging method for image sensor chip and packaging structure |
| CN207250481U (en) * | 2017-06-14 | 2018-04-17 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure of chip |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107863363A (en) * | 2017-11-20 | 2018-03-30 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure of chip and preparation method thereof |
| CN108010929A (en) * | 2017-11-29 | 2018-05-08 | 苏州晶方半导体科技股份有限公司 | A kind of method for packing of image sensing chip |
| CN108010890A (en) * | 2017-12-29 | 2018-05-08 | 苏州晶方半导体科技股份有限公司 | Chip-packaging structure and method |
| CN108022898A (en) * | 2017-12-29 | 2018-05-11 | 苏州晶方半导体科技股份有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN108063126A (en) * | 2017-12-29 | 2018-05-22 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and method for packing of a kind of chip |
| WO2019128398A1 (en) * | 2017-12-29 | 2019-07-04 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and manufacturing method therefor |
| CN110837146A (en) * | 2018-08-17 | 2020-02-25 | 张家港康得新光电材料有限公司 | Optical waveguide structure, processing method thereof, ambient light sensor and electronic product |
| CN109192706B (en) * | 2018-09-07 | 2024-04-12 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure and chip packaging method |
| CN109192706A (en) * | 2018-09-07 | 2019-01-11 | 苏州晶方半导体科技股份有限公司 | A kind of chip-packaging structure and chip packaging method |
| CN109411377A (en) * | 2018-11-07 | 2019-03-01 | 苏州晶方半导体科技股份有限公司 | A kind of ultra-thin supplied materials encapsulating method and structure |
| WO2020094096A1 (en) * | 2018-11-07 | 2020-05-14 | 苏州晶方半导体科技股份有限公司 | Method for encapsulating ultrathin incoming material |
| CN109411377B (en) * | 2018-11-07 | 2020-07-21 | 苏州晶方半导体科技股份有限公司 | Ultrathin incoming material packaging method and packaging structure |
| WO2020094095A1 (en) * | 2018-11-07 | 2020-05-14 | 苏州晶方半导体科技股份有限公司 | Ultra-thin incoming material packaging method and packaging structure |
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