CN107093581B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Semiconductor device, manufacturing method thereof and electronic device Download PDF

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CN107093581B
CN107093581B CN201610089201.2A CN201610089201A CN107093581B CN 107093581 B CN107093581 B CN 107093581B CN 201610089201 A CN201610089201 A CN 201610089201A CN 107093581 B CN107093581 B CN 107093581B
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CN107093581A (en
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徐建华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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  • Power Engineering (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, and forming a high-K gate dielectric layer on the semiconductor substrate; and forming a covering layer on the high-K gate dielectric layer, wherein the covering layer comprises a first covering layer and a second covering layer which are stacked, the first covering layer comprises nitrogen elements and metal elements, and the second covering layer comprises the nitrogen elements, the metal elements and silicon elements. The semiconductor device formed by the manufacturing method comprises the covering layer positioned between the work function layer and the high-K grid dielectric layer, the covering layer adopts a lamination layer consisting of a columnar crystal structure and an amorphous film structure, and the amorphous film structure has a better blocking effect on the diffusion of O and Al compared with the columnar crystal structure, so that the reliability and the performance of the device are improved.

Description

Semiconductor device, manufacturing method thereof and electronic device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
In the fabrication process of next generation integrated circuits, a high-k metal gate process is typically employed for the fabrication of Metal Oxide Semiconductor (MOS) gates.
No matter the metal gate is first or last, aluminum diffusion is one of the main problems affecting the reliability and performance of the device, for example, the reliability of Time Dependent Dielectric Breakdown (TDDB), Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), etc. is negatively affected, and aluminum diffusion also affects the mobility of carriers and reduces the performance of the device.
Therefore, a new method is needed to solve the above technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, and forming a high-K gate dielectric layer on the semiconductor substrate;
and forming a covering layer on the high-K gate dielectric layer, wherein the covering layer comprises a first covering layer and a second covering layer which are stacked, the first covering layer comprises nitrogen elements and metal elements, and the second covering layer comprises the nitrogen elements, the metal elements and silicon elements.
Further, the first covering layer is a TiN film, and the second covering layer is a TiSiN film.
Further, the first covering layer is deposited firstly, and then the second covering layer is deposited.
Further, the thickness of the first cover layer is greater than or equal to the thickness of the second cover layer.
Further, the thickness of the second cover layer is one third of the total thickness of the cover layer, and the thickness of the first cover layer is two thirds of the total thickness of the cover layer.
Furthermore, the total thickness of the covering layer is 10-30 angstroms.
Further, the first covering layer is formed by deposition through a physical vapor deposition method or an atomic layer deposition method, and the second covering layer is formed by deposition through the atomic layer deposition method.
Further, the first covering layer is of a columnar crystal structure, and the second covering layer is of an amorphous film.
Further, after forming the cover layer, the method further comprises the steps of: and sequentially forming a work function layer, a diffusion barrier layer and a conductive layer on the covering layer.
Another aspect of the present invention provides a semiconductor device, including: the semiconductor device comprises a semiconductor substrate, a high-K gate dielectric layer formed on the semiconductor substrate, and a covering layer formed on the high-K gate dielectric layer, wherein the covering layer comprises a first covering layer and a second covering layer which are stacked, the first covering layer comprises nitrogen elements and metal elements, and the second covering layer comprises nitrogen elements, metal elements and silicon elements.
Further, the first covering layer is a TiN film, and the second covering layer is a TiSiN film.
Further, the second cover layer is formed on the first cover layer.
Further, the thickness of the first cover layer is greater than or equal to the thickness of the second cover layer.
Further, the thickness of the second cover layer is one third of the total thickness of the cover layer, and the thickness of the first cover layer is two thirds of the total thickness of the cover layer.
Further, the thickness of the covering layer is 10-30 angstroms.
Further, the first covering layer is of a columnar crystal structure, and the second covering layer is of an amorphous film.
In another aspect, the present invention provides an electronic device including the semiconductor device.
The semiconductor device formed by the manufacturing method comprises the covering layer positioned between the work function layer and the high-K grid dielectric layer, the covering layer adopts a lamination layer consisting of a columnar crystal structure and an amorphous film structure, and the amorphous film structure has a better blocking effect on the diffusion of O and Al compared with the columnar crystal structure, so that the reliability and the performance of the device are improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention;
FIG. 2 is a flow chart illustrating steps in a method of fabricating a semiconductor device according to an embodiment of the present invention;
fig. 3 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In the high-K metal gate process, a TiN capping layer is often formed on the high-K gate dielectric layer, and the TiN capping layer is located between the high-K gate dielectric layer and the metal gate work function layer as a diffusion barrier layer to block Al, and for advanced technologies below 28nm node, a physical vapor deposition process (for 28nm and 20nm) or a chemical vapor deposition process (for 16nm and 14nm) is widely used to fabricate the TiN capping layer. However, for very thin pure TiN capping layers (less than 20 angstroms) there is insufficient barrier to Al and O diffusion, which tends to negatively impact device performance.
The present invention provides a new semiconductor device comprising a capping layer between the work function layer and the high-K gate dielectric layer, the capping layer employing a stack of a columnar crystalline structure and an amorphous thin film structure, wherein the amorphous thin film structure has a better barrier effect against the diffusion of O and Al than the columnar crystalline structure, thereby improving the reliability and performance of the device.
A detailed description of an embodiment of the semiconductor device of the present invention is provided below with reference to fig. 1, where fig. 1 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
As an example, as shown in fig. 1, the semiconductor device of the present invention includes a semiconductor substrate (not shown), a high-K gate dielectric layer 101 formed on the semiconductor substrate, and a capping layer 102 formed on the high-K gate dielectric layer 101, wherein the capping layer 102 includes a first capping layer 1021 and a second capping layer 1022 which are stacked, the first capping layer 1021 includes a nitrogen element and a metal element, and the second capping layer 1022 includes a nitrogen element, a metal element, and a silicon element.
The semiconductor substrate in the present invention may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. An isolation structure is also formed in the semiconductor substrate, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Various well structures and channel layers on the surface of the substrate are also formed in the semiconductor substrate. Generally, the ion doping conductivity type of the well (well) structure is the same as that of the channel layer, but the concentration of the well (well) structure is lower than that of the gate channel layer, the ion implantation depth is wider, and the depth of the well (well) structure is required to be larger than that of the isolation structure. For simplicity, the illustration is omitted.
Optionally, an interface layer (not shown) is further formed between the high-K gate dielectric layer 101 and the semiconductor substrate, the interface layer is made of silicon oxide (SiOx), and the interface layer is formed to improve the interface characteristics between the high-K gate dielectric layer 101 and the semiconductor substrate. The IL layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. The interfacial layer may be formed using a suitable process such as thermal oxidation, CVD, ALD, or PVD. The interfacial layer has a thickness in the range of 5 angstroms to 10 angstroms.
high-K gate dielectric layer 101 has a K value (dielectric constant) of usually 3.9 or more, and is made of a material including hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like, preferably hafnium oxide, zirconium oxide, or aluminum oxide. The thickness of the K gate dielectric layer 101 ranges from 10 angstroms to 30 angstroms, which is merely exemplary and other suitable thickness values are also applicable to the present invention.
Illustratively, a capping layer 102 is formed on the high-K gate dielectric layer 101, wherein the capping layer 102 includes a first capping layer 1021 and a second capping layer 1022 which are stacked, the first capping layer 1021 includes a nitrogen element and a metal element, the second capping layer 1022 includes a nitrogen element, a metal element and a silicon element, and optionally, the thickness of the capping layer is 10 to 30 angstroms.
Further, the second cover layer 1022 is formed on the first cover layer 1021. The first cladding layer 1021 may have a columnar crystal structure, and the second cladding layer 1022 mainly has an amorphous film structure, and the amorphous film has a better barrier effect on diffusion of Al and O than the columnar crystal structure.
Further, the material of the first cover layer 1021 may be MoN, WN, TixN1-x, TaN or other suitable thin film layers, and the material of the second cover layer 1022 may be TiSiN film, TaSiN film or other suitable thin film layers.
In one example, the thickness of the first cover layer 1021 is greater than or equal to the thickness of the second cover layer 1022, for example, the thickness of the second cover layer 1022 is one third of the total thickness of the cover layer 102, and the thickness of the first cover layer 1021 is two thirds of the total thickness of the cover layer 102.
In one example, a work function layer 103, a diffusion barrier layer 104, and a conductive layer 105 are also sequentially formed on the capping layer 102.
Depending on the type of device, the work function layer 103 is made of different materials, for example, for a PMOS device, the work function layer 103 is a P-type work function metal layer, the P-type work function metal layer is a PMOS work function metal tunable layer, and the material of the P-type work function metal layer (PWF) may be selected from but not limited to TixN1-x, TaC, MoN, TaN, or other suitable thin film layers. The thickness of the P-type work function metal layer ranges from 10 angstroms to 580 angstroms; for an NMOS device, the work function layer 103 is an N-type work function metal layer, the N-type work function metal layer (NWF) is an NMOS work function metal tunable layer, and the material of the N-type work function metal layer may be selected from, but not limited to, TaC, Ti, Al, TixAl1-x or other suitable thin film layers. The thickness of the N-type workfunction metal layer ranges from 10 to 80 angstroms.
Alternatively, the diffusion barrier layer 104 may be a silicon-containing layer, a carbon-containing layer, a nitrogen-containing layer, a hydrogen-containing layer, or a metal or metal compound layer. The material of the metal or metal compound layer is, for example, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten nitride, an alloy thereof, or a composition thereof. In one embodiment, the diffusion barrier layer 104 is TiN. In addition, the diffusion barrier layer 104 may also include multiple layers.
The material of the conductive layer 105 is not particularly limited, and a conductive material and a metal compound having one or more selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al may be used. In one embodiment, W metal is used as the conductive material of the conductive layer 105.
In summary, the capping layer of the semiconductor device of the present invention employs a stack of a columnar crystal structure and an amorphous thin film structure, wherein the amorphous thin film structure has a better barrier effect against diffusion of O and Al than the columnar crystal structure, and thus the semiconductor device of the present invention has excellent reliability and performance.
In order to obtain the foregoing semiconductor device structure, the present invention further provides a method for manufacturing a semiconductor device, as shown in fig. 2, the method mainly includes:
in step S201, providing a semiconductor substrate on which a high-K gate dielectric layer is formed;
in step S202, a capping layer of a predetermined thickness is formed on the high-K gate dielectric layer, wherein the capping layer includes a first capping layer and a second capping layer that are stacked, the first capping layer includes a nitrogen element and a metal element, and the second capping layer includes a nitrogen element, a metal element, and a silicon element.
Further, a second covering layer is located above the first covering layer, the first covering layer may be a columnar crystal structure, and the second covering layer is an amorphous film.
The semiconductor device formed by the manufacturing method comprises the covering layer positioned between the work function layer and the high-K grid dielectric layer, the covering layer adopts a lamination layer consisting of a columnar crystal structure and an amorphous film structure, and the amorphous film structure has a better blocking effect on the diffusion of O and Al compared with the columnar crystal structure, so that the reliability and the performance of the device are improved.
Example one
A method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described in detail below with reference to fig. 1.
According to the first embodiment of the present invention, the method for manufacturing a semiconductor device of the present invention specifically includes the steps of:
first, a semiconductor substrate is provided on which a high-K gate dielectric layer 101 is formed.
Specifically, the semiconductor substrate in the present invention may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. An isolation structure is also formed in the semiconductor substrate, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Various well structures and channel layers on the surface of the substrate are also formed in the semiconductor substrate. Generally, the ion doping conductivity type of the well (well) structure is the same as that of the channel layer, but the concentration of the well (well) structure is lower than that of the gate channel layer, the ion implantation depth is wider, and the depth of the well (well) structure is required to be larger than that of the isolation structure.
An interfacial layer (not shown) may optionally be formed on the surface of the semiconductor substrate prior to forming high-K gate dielectric layer 101.
The Interface (IL) layer is formed of a material including silicon oxide (SiOx) and is formed to improve the interface characteristics between the high-k gate dielectric layer and the semiconductor substrate. The interface layer 101 may also be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. The interfacial layer may be formed using a thermal oxidation process such as dry oxygen oxidation, wet oxygen oxidation, high pressure oxidation, or a suitable process such as CVD, ALD, or PVD. The thickness of the interfacial layer may illustratively be
Figure BDA0000925254110000081
high-K gate dielectric layer 101 has a K value (dielectric constant) of usually 3.9 or more, and is made of a material including hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like, preferably hafnium oxide, zirconium oxide, or aluminum oxide. The thickness of the K gate dielectric layer 101 ranges from 10 angstroms to 30 angstroms, which is merely exemplary and other suitable thickness values are also applicable to the present invention.
The method for forming the high-K gate dielectric layer 101 may use any conventional technique known to those skilled in the art, such as a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, and the thickness thereof is 15 to 60 angstroms.
Next, a capping layer 102 of a predetermined thickness is formed on the high-K gate dielectric layer 101, wherein the capping layer 101 includes a first capping layer 1021 and a second capping layer 1022 which are stacked, the first capping layer 1021 includes a nitrogen element and a metal element, and the second capping layer 1022 includes a nitrogen element, a metal element, and a silicon element.
Further, a first cladding layer 1021 is deposited first, and then a second cladding layer 1022 is deposited to cover the first cladding layer 1021. The first cladding layer 1021 may have a columnar crystal structure, and the second cladding layer 1022 mainly has an amorphous film structure, and the amorphous film has a better barrier effect on diffusion of Al and O than the columnar crystal structure.
Further, the material of the first cover layer 1021 may be MoN, WN, TixN1-x, TaN or other suitable thin film layers, and the material of the second cover layer 1022 may be TiSiN thin film, TaSiN thin film or other suitable thin film layers, in this embodiment, the material of the first cover layer 1021 is TiN thin film, and the material of the second cover layer 1022 is TiSiN thin film.
In one example, the thickness of the first cover layer 1021 is greater than or equal to the thickness of the second cover layer 1022, for example, the thickness of the second cover layer 1022 is one third of the total thickness of the cover layer 102, and the thickness of the first cover layer 1021 is two thirds of the total thickness of the cover layer 102.
It is worth mentioning that, because the resistivity of the TiSiN film is higher than that of a pure TiN film, the thickness of the TiSiN film is controlled as much as possible in this step, so that the thickness of the TiSiN film is as thin as possible, which not only can realize the blocking effect on O and Al, but also can not cause negative influence on the performance of the device, for example, the thickness of the TiSiN film is one third of the total thickness of the covering layer, and the remaining two thirds of the total thickness is the TiN film.
According to different technical nodes, a suitable deposition method can be selected to form the first covering layer and the second covering layer, and illustratively, the first covering layer can be deposited by a physical vapor deposition method or an atomic layer deposition method, and the second covering layer can be deposited by an atomic layer deposition method.
Next, a work function layer 103, a diffusion barrier layer 104, and a conductive layer 105 may be sequentially formed on the capping layer 102.
Depending on the type of device, the work function layer 103 is made of different materials, for example, for a PMOS device, the work function layer 103 is a P-type work function metal layer, the P-type work function metal layer is a PMOS work function metal tunable layer, and the material of the P-type work function metal layer (PWF) may be selected from but not limited to TixN1-x, TaC, MoN, TaN, or other suitable thin film layers. The thickness of the P-type work function metal layer ranges from 10 angstroms to 580 angstroms; for an NMOS device, the work function layer 103 is an N-type work function metal layer, the N-type work function metal layer (NWF) is an NMOS work function metal tunable layer, and the material of the N-type work function metal layer may be selected from, but not limited to, TaC, Ti, Al, TixAl1-x or other suitable thin film layers. The thickness of the N-type workfunction metal layer ranges from 10 to 80 angstroms. The work function layer 103 may be deposited using a suitable process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD).
Alternatively, the diffusion barrier layer 104 may be a silicon-containing layer, a carbon-containing layer, a nitrogen-containing layer, a hydrogen-containing layer, or a metal or metal compound layer. The material of the metal or metal compound layer is, for example, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten nitride, an alloy thereof, or a composition thereof. In one embodiment, the diffusion barrier layer 104 is TiN. The diffusion barrier layer 104 is formed by a process such as PVD, ALD, spin-on deposition or other suitable methods. In addition, the diffusion barrier layer 104 may also include multiple layers.
The material of the conductive layer 105 is not particularly limited, and a conductive material and a metal compound having one or more selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al may be used. In one embodiment, W metal is used as the conductive material of the conductive layer 105. The conductive layer 105 may be formed using a suitable process such as CVD, ALD, or PVD. Thus, the main process of manufacturing the metal gate is completed.
It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above steps, but also other steps as needed before, during or after the above steps, which are included in the scope of the method for manufacturing the semiconductor device.
In summary, according to the manufacturing method of the present invention, the capping layer between the work function layer and the high-K gate dielectric layer is formed, and the capping layer adopts a stacked layer composed of a columnar crystal structure and an amorphous thin film structure, wherein the amorphous thin film structure has a better barrier effect on diffusion of O and Al than the columnar crystal structure, and thus, reliability and performance of the device are improved.
Example two
Another embodiment of the present invention provides an electronic device, which includes a semiconductor device, where the semiconductor device is the semiconductor device described above, or a semiconductor device manufactured by the manufacturing method of the semiconductor device described in the first embodiment.
The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, and a PSP, or may be an intermediate product having the semiconductor device, for example: a mobile phone mainboard with the integrated circuit, and the like.
The electronic device also has the advantages described above, since the included semiconductor device has higher performance and reliability.
Wherein figure 3 shows an example of a mobile telephone handset. The mobile phone handset 200 is provided with a display portion 202, operation buttons 203, an external connection port 204, a speaker 205, a microphone 206, and the like, which are included in a housing 201.
The mobile phone handset comprises the semiconductor device or the semiconductor device manufactured by the manufacturing method of the semiconductor device according to the embodiment one, and the semiconductor device comprises a covering layer positioned between a work function layer and a high-K gate dielectric layer, wherein the covering layer adopts a lamination layer consisting of a columnar crystal structure and an amorphous film structure, and the amorphous film structure has a better blocking effect on the diffusion of O and Al compared with the columnar crystal structure, so that the reliability and the performance of the device are improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (13)

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, and forming a high-K gate dielectric layer on the semiconductor substrate;
forming a capping layer on the high-K gate dielectric layer, wherein the capping layer includes a first capping layer and a second capping layer that are stacked, the first capping layer includes a nitrogen element and a metal element, the second capping layer includes a nitrogen element, a metal element, and a silicon element,
firstly, depositing to form the first covering layer, then depositing to form the second covering layer,
the first covering layer is of a columnar crystal structure, and the second covering layer is of an amorphous film.
2. The method of claim 1, wherein the first capping layer is a TiN film and the second capping layer is a TiSiN film.
3. The method of claim 1, wherein a thickness of the first cladding layer is equal to or greater than a thickness of the second cladding layer.
4. The method of claim 3, wherein the second cover layer has a thickness that is one-third of a total thickness of the cover layer, and the first cover layer has a thickness that is two-thirds of the total thickness of the cover layer.
5. The method of claim 1, wherein the total thickness of the capping layer is 10 to 30 angstroms.
6. The method of claim 1, wherein the first capping layer is deposited using a physical vapor deposition method or an atomic layer deposition method and the second capping layer is deposited using an atomic layer deposition method.
7. The method of claim 1, wherein after forming the capping layer, further comprising the steps of: and sequentially forming a work function layer, a diffusion barrier layer and a conductive layer on the covering layer.
8. A semiconductor device, comprising: the semiconductor device comprises a semiconductor substrate, a high-K gate dielectric layer formed on the semiconductor substrate, and a covering layer formed on the high-K gate dielectric layer, wherein the covering layer comprises a first covering layer and a second covering layer which are stacked, the first covering layer comprises nitrogen elements and metal elements, the second covering layer comprises nitrogen elements, metal elements and silicon elements, the first covering layer is formed by deposition firstly, the second covering layer is formed by deposition secondly, the second covering layer is formed on the first covering layer, the first covering layer is in a columnar crystal structure, and the second covering layer is an amorphous film.
9. The semiconductor device according to claim 8, wherein the first capping layer is a TiN film and the second capping layer is a TiSiN film.
10. The semiconductor device according to claim 8, wherein a thickness of the first clad layer is equal to or greater than a thickness of the second clad layer.
11. The semiconductor device according to claim 10, wherein a thickness of the second clad layer is one third of a total thickness of the clad layers, and a thickness of the first clad layer is two thirds of the total thickness of the clad layers.
12. The semiconductor device according to claim 8, wherein a thickness of the capping layer is 10 to 30 angstroms.
13. An electronic device characterized by comprising the semiconductor device according to any one of claims 8 to 12.
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CN101136328A (en) * 2006-08-29 2008-03-05 东部高科股份有限公司 Gate electrode of semiconductor device and method of forming same
CN104051252A (en) * 2013-03-11 2014-09-17 中芯国际集成电路制造(上海)有限公司 Preparation method of high-K metal gate structure

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CN101136328A (en) * 2006-08-29 2008-03-05 东部高科股份有限公司 Gate electrode of semiconductor device and method of forming same
CN104051252A (en) * 2013-03-11 2014-09-17 中芯国际集成电路制造(上海)有限公司 Preparation method of high-K metal gate structure

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