CN107068692A - Display device, array base palte and its manufacture method - Google Patents
Display device, array base palte and its manufacture method Download PDFInfo
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- CN107068692A CN107068692A CN201710261623.8A CN201710261623A CN107068692A CN 107068692 A CN107068692 A CN 107068692A CN 201710261623 A CN201710261623 A CN 201710261623A CN 107068692 A CN107068692 A CN 107068692A
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims abstract description 71
- 239000010409 thin film Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000059 patterning Methods 0.000 claims abstract description 26
- 238000009413 insulation Methods 0.000 claims abstract description 17
- 239000011248 coating agent Substances 0.000 claims description 40
- 238000000576 coating method Methods 0.000 claims description 40
- 230000003064 anti-oxidating effect Effects 0.000 claims description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 238000003860 storage Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 description 5
- 239000000306 component Substances 0.000 description 4
- 230000006978 adaptation Effects 0.000 description 2
- 230000009194 climbing Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
The disclosure provides a kind of display device, array base palte and its manufacture method.The manufacture method of the array base palte of the disclosure includes：Being formed on underlay substrate at least includes the gate metal layer in thin film transistor region and power line area；Grid is formed in thin film transistor region by patterning processes and power line is formed in power line area, and thickness of the thickness less than power line of grid；Gate insulation layer, active layer and the Source and drain metal level of stacking are formed in thin film transistor region by patterning processes, to obtain thin film transistor (TFT).
Description
Technical field
This disclosure relates to display technology field, in particular to a kind of display device, array base palte and array base palte
Manufacture method.
Background technology
At present, with display panel extensive use, requirement of the people to product quality also more and more higher.Array base palte, makees
For the core component of display panel, its quality is directly related to the quality of final products.Existing array base palte typically all has thin
Film transistor, when forming the grid of thin film transistor (TFT), it is necessary to be initially formed gate metal layer on the glass substrate, then passes through photoetching
Technique forms grid in gate metal layer；But the gate metal layer is not only used for forming grid, may be used also by photoetching process
To be formed with grid with power line of layer etc. simultaneously.
For power line, in order to reduce line resistance, it is ensured that pressure drop is, it is necessary to ensure that it has larger thickness；But due to
Metal heat endurance is poorer than glass, and the larger metal of thickness needs to discharge internal stress in high-temperature technology so that in metal level
Contract and form multiple raised " koppies ", that is, " hillock " phenomenon occur；These " koppies " may pierce gate insulation
Layer, causes the metal of gate insulation layer both sides short circuit occur, causes thin film transistor (TFT) to be difficult to normal work, so as to influence array base palte
And the normal work of display panel, and metal is thicker, the incidence of " hillock " phenomenon is higher, so that the yield of product is big
Width is reduced.
It should be noted that information is only used for strengthening the reason of background of this disclosure disclosed in above-mentioned background section
Solution, therefore can include not constituting the information to prior art known to persons of ordinary skill in the art.
The content of the invention
The purpose of the disclosure is the manufacture method for providing a kind of display device, array base palte and array base palte, Jin Erzhi
One or more problem caused by few limitation and defect overcome to a certain extent due to correlation technique.
According to an aspect of this disclosure there is provided a kind of manufacture method of array base palte, including：
Being formed on underlay substrate at least includes the gate metal layer in thin film transistor region and power line area；
Grid is formed in the thin film transistor region by patterning processes and power line, and institute are formed in the power line area
The thickness for stating grid is less than the thickness of the power line；
By patterning processes gate insulation layer, active layer and the source and drain metal of stacking are formed in the thin film transistor region
Layer, to obtain thin film transistor (TFT).
In a kind of exemplary embodiment of the disclosure, the gate metal layer also includes storage capacitance area, the array
The manufacture method of substrate also includes：
Capacitance electrode is formed in the storage capacitance area by patterning processes, the thickness of the capacitance electrode is less than the electricity
The thickness of source line.
In a kind of exemplary embodiment of the disclosure, the gate metal layer also includes grid line area, the array base palte
Manufacture method also include：
The zone of intersection for including intersecting on grid line, the grid line with signal wire is formed in the grid line area by patterning processes,
The thickness of the grid line of the zone of intersection is less than the thickness of the power line.
In a kind of exemplary embodiment of the disclosure, after the grid is formed, formed before the gate insulation layer, institute
Stating the manufacture method of array base palte also includes：
Antioxidation coating is formed on the underlay substrate including the grid；
By patterning processes formation antioxidation coating pattern, the antioxidation coating pattern is at least covered in the gate metal layer
Thickness is less than the region of the thickness of the power line, and any thickness is less than institute in the antioxidation coating and the gate metal layer
The thickness sum for stating the region of power line is less than the thickness of the power line.
It is described grid to be formed in the thin film transistor region and in the electricity in a kind of exemplary embodiment of the disclosure
Yuan Xian areas, which form power line, to be included：
The coating photoresist layer in the gate metal layer；
Using intermediate tone mask version the photoresist layer is exposed and developed, with least obtain removing completely area, and
The corresponding reserved area in power line area and half reserved area corresponding with the thin film transistor region；
The gate metal layer that the complete removal area exposes is removed using etching technics；
The photoresist of half reserved area is removed using cineration technics, exposes the gate metal of the thin film transistor region
Layer；
The gate metal layer of the thin film transistor region is thinned using etching technics；
The photoresist layer of the reserved area is removed using stripping technology.
According to an aspect of this disclosure there is provided a kind of array base palte, including：
Underlay substrate；
Power line, on the underlay substrate；
Thin film transistor (TFT), on the underlay substrate, and the thin film transistor (TFT) include grid, it is gate insulation layer, active
Layer, Source and drain metal level, the grid are set with the power line with layer, and thickness of the thickness less than the power line of the grid
Degree.
In a kind of exemplary embodiment of the disclosure, the array base palte also includes：
Storage capacitance, the storage capacitance includes capacitance electrode, the capacitance electrode on the underlay substrate and with
The grid is set with layer, and thickness of the thickness less than the power line of the capacitance electrode.
In a kind of exemplary embodiment of the disclosure, the array base palte also includes：
Grid line, is set, the grid line includes the zone of intersection on the underlay substrate and with the grid with layer；
Signal wire, intersects above the grid line and in the zone of intersection with the grid line, and with the zone of intersection
The thickness of the grid line is less than the thickness of the power line.
In a kind of exemplary embodiment of the disclosure, the array base palte also includes：
Antioxidation coating pattern, between the gate metal layer and the gate insulation layer, the antioxidation coating pattern is extremely
The region that thickness in the gate metal layer is less than the thickness of the power line, and the antioxidation coating and the grid are covered less
Any thickness is less than the thickness of the thickness sum less than the power line in the region of the power line on metal level.
According to an aspect of this disclosure, a kind of display device, including：
Array base palte described in above-mentioned any one.
Manufacture method, array base palte and the display device of disclosure array base palte, can be by making in gate metal layer not
With region there are different thickness to improve product yield, and avoid influenceing the line resistance of power line；It, can pass through composition for tool
Technique forms grid in thin film transistor region and power line is formed in power line area, and thickness of the thickness less than power line of grid
Degree.So as to can both avoid the thickness for reducing power line, it is ensured that the line resistance and pressure drop of power line, the thickness of grid can be reduced again
Degree, to prevent " koppie ", i.e. " hillock " phenomenon occur in grid, so as to ensure the normal work of thin film transistor (TFT).By
This, can improve the yield of product.
It should be appreciated that the general description of the above and detailed description hereinafter are only exemplary and explanatory, not
The disclosure can be limited.
Brief description of the drawings
Accompanying drawing herein is merged in specification and constitutes the part of this specification, shows the implementation for meeting the disclosure
Example, and be used to together with specification to explain the principle of the disclosure.It should be evident that drawings in the following description are only the disclosure
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 is the flow chart of the manufacture method of disclosure array base palte.
Fig. 2 is the flow chart for realizing step S120 method in Fig. 1.
Fig. 3 is the corresponding structural representations of step S110 in Fig. 2.
Fig. 4 is the corresponding structural representations of step S1201 in Fig. 2.
Fig. 5 is the corresponding structural representations one of step S1202 in Fig. 2.
Fig. 6 is the corresponding structural representations two of step S1202 in Fig. 2.
Fig. 7 is the corresponding structural representations of step S1203 in Fig. 2.
Fig. 8 is the corresponding structural representations of step S1204 in Fig. 2.
Fig. 9 is the corresponding structural representations of step S1205 in Fig. 2.
Figure 10 is the corresponding structural representations of step S1206 in Fig. 2.
Figure 11 for disclosure array base palte manufacture method in antioxidation coating structural representation.
Figure 12 is the structural representation of the thin film transistor (TFT) of disclosure array base palte.
Figure 13 is the thin film transistor (TFT) of disclosure array base palte and the structural representation of capacitance electrode.
Figure 14 is the grid line of disclosure array base palte and the structural representation of signal wire.
Embodiment
Example embodiment is described more fully with referring now to accompanying drawing.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment those skilled in the art is comprehensively conveyed to.Described feature, knot
Structure or characteristic can be combined in one or more embodiments in any suitable manner.There is provided permitted in the following description
Many details are so as to provide fully understanding for embodiment of this disclosure.It will be appreciated, however, by one skilled in the art that can
Omit one or more in the specific detail to put into practice the technical scheme of the disclosure, or others side can be used
Method, constituent element, device, step etc..In other cases, be not shown in detail or describe known solution a presumptuous guest usurps the role of the host to avoid and
So that each side of the disclosure thickens.
Although using the term of relativity in this specification, such as " on ", " under " come describe a component of icon for
The relativeness of another component, but these terms are used in this specification merely for convenient, for example with reference to the accompanying drawings described in
The direction of example.Be appreciated that, if making it turn upside down the upset of the device of icon, describe " on " component general
Can turn into " under " component.When certain structure other structures " on " when, it is possible to refer to that certain structural integrity is formed at other knots
On structure, or refer to certain structure " direct " and be arranged in other structures, or refer to certain structure be arranged on by another structure " indirect " it is other
In structure.
Term "the" and " described " to represent to exist one or more elements/part/etc.；Term " comprising " and
" having " to represent it is open be included look like and refer to key element/part/except listing in addition to waiting also
May be present other key element/part/etc..
A kind of manufacture method of array base palte is provide firstly in this example embodiment, available for manufacture OLED
(Organic Light-Emitting Diode, Organic Light Emitting Diode) display device such as display device or liquid crystal display device
Array base palte, such as Fig. 1, the manufacture method of the array base palte of present embodiment may comprise steps of：
Step S110, formed on underlay substrate and at least to include the gate metal layer in thin film transistor region and power line area；
Step S120, formed by patterning processes in the thin film transistor region and grid and form electricity in the power line area
Source line, and thickness of the thickness less than the power line of the grid；
Step S130, by patterning processes the thin film transistor region formed stacking gate insulation layer, active layer and
Source and drain metal level, to obtain thin film transistor (TFT).
The manufacture method of the array base palte of present embodiment, can by patterning processes thin film transistor region formed grid simultaneously
Power line, and thickness of the thickness less than power line of grid are formed in power line area.So as to can both avoid reducing power line
Thickness, it is ensured that the line resistance and pressure drop of power line, can reduce the thickness of grid, to prevent " koppie " occur in grid, i.e., again
" hillock " phenomenon, so as to ensure the normal work of thin film transistor (TFT).Thus, the yield of product can be improved.
Below, each step to the manufacture method of array base palte in this example embodiment is further detailed.
In step s 110, such as Fig. 3, being formed on underlay substrate 1 at least includes thin film transistor region and power line area
Gate metal layer 2.
In the present embodiment, gate metal layer 2 can be formed on underlay substrate by methods such as chemical vapor depositions, but
It is not limited, can also be using other methods formation gate metal layer 2；The gate metal layer 2 can be divided into multiple regions,
And at least include thin film transistor region and power line area；Wherein, the grid of thin film transistor (TFT) can be located in the thin film transistor region,
And the power line of array base palte can be located in power line area.
In the step s 120, such as Figure 10, grid 21 is formed in the thin film transistor region and described by patterning processes
Power line area forms power line 22, and thickness of the thickness less than the power line 22 of the grid 21.
In the present embodiment, the method for forming above-mentioned grid 21 and power line 22 can be led to using intermediate tone mask version
Cross patterning processes and form grid 21 in above-mentioned thin film transistor region, meanwhile, form power line 22 in power line area.For example,
Such as Fig. 2 and Fig. 4~Fig. 7, S1201~step can be comprised the steps by forming the method for above-mentioned grid 21 and power line 22
1206, but Fig. 4~Fig. 7 is only the schematic diagram of the technical process and the thickness relationship of the two that reflect grid 21 and power line 22, and
The restriction to its position relationship and annexation is not constituted, wherein：
In step S1201, such as Fig. 4, the coating photoresist layer 3 in the gate metal layer 2.
Photoresist layer 3 can be positive photoresist or negative photoresist；And can be to being formed with before coating photoresist layer 3
The underlay substrate 1 of gate metal layer 2 is cleaned, and removes surface particle, it is to avoid impurity is disturbed.
In step S1202, such as Fig. 5 and Fig. 6 is exposed and shown using intermediate tone mask 4 pairs of photoresist layers 3 of version
Shadow, at least to obtain removing area, reserved area corresponding with the power line area and corresponding with the thin film transistor region completely
Half reserved area；Wherein, Fig. 5 shows to be exposed using intermediate tone mask 4 pairs of photoresist layers 3 of version；Fig. 6 shows the photoetching after development
Glue-line 3.
Intermediate tone mask version 4 at least includes alternatively non-transparent district, full transparent area and semi-opaque region；If photoresist layer 3 uses positivity
Photoresist, in exposure, alternatively non-transparent district is corresponding with above-mentioned power supply area, and semi-opaque region is corresponding with thin film transistor region, full transparent area
It is corresponding with the region that need not retain；Halftoning mask plate 4 can be irradiated using ultraviolet light, make the photoresist of alternatively non-transparent district
Layer 3 does not dissolve in developer solution, and the photoresist layer 3 of semi-opaque region is incompletely dissolved in developer solution, and the photoresist layer 3 of full transparent area can be entirely molten
In developer solution；After being developed by developer solution, above-mentioned complete removal area, reserved area and half reserved area is formed, and retain
The thickness of the photoresist layer 3 in area is more than the thickness of the photoresist layer 3 of half reserved area.If photoresist layer 3 uses negative photoresist, half
The location swap of the alternatively non-transparent district of tone mask plate 4 and full transparent area, concrete principle has been known, and will not be described in detail herein.
In step S1203, such as Fig. 7 removes the gate metal layer 2 that the complete removal area exposes using etching technics.
Above-mentioned etching technics can use dry etching or wet etching, and the gate metal layer 2 that area exposes is removed by complete
Remove, thin film transistor region and power line area are included in the region of reservation.
In step S1204, such as Fig. 8 removes the photoresist layer 3 of half reserved area using cineration technics, exposes described
The gate metal layer 2 of thin film transistor region.
Because the thickness of the photoresist layer 3 of reserved area is more than the thickness of the photoresist layer 3 of half reserved area, thus removing half
After the photoresist layer 3 of reserved area, the photoresist layer 3 of reserved area can be thinned so that the gate metal layer 2 in power line area is still by light
Photoresist layer 3 is covered, and the gate metal layer 2 of thin film transistor region is exposed.
In step S1205, the gate metal layer 2 of the thin film transistor region is thinned using etching technics by such as Fig. 9.
The thickness of the gate metal layer 2 of thin film transistor region can be thinned using dry etching or wet etching, power line
The gate metal layer 2 in area will not be then thinned due to the covering of photoresist layer 3.
In step S1206, such as Figure 10 removes the photoresist layer 3 of the reserved area using stripping technology.
After step S1206 is completed, grid 21 and power line 22 are can obtain, and the thickness of grid 21 is less than power line 22
Thickness, so as to prevent grid 21 from " hillock " phenomenon occur, and can avoid the line of boost source line 22 from hindering, advantageously ensure that
The pressure drop of power line 22.
It should be noted that brilliant in the film by patterning processes described in above-mentioned step S1201~step 1206
Body area under control forms grid 21 and the method for forming power line 22 in the power line area, is merely illustrative, composition pair
The restriction of the disclosure, it can also use other embodiment, will not be repeated here.
In step s 130, such as Figure 12, the gate insulation layer of stacking is formed in the thin film transistor region by patterning processes
5th, active layer 6 and Source and drain metal level 7, to obtain thin film transistor (TFT).
In the present embodiment, the method for forming above-mentioned gate insulation layer 5, active layer 6 and Source and drain metal level 7 refers to this
The conventional method in field, will not be described in detail herein.
In the present embodiment, such as Figure 13, gate metal layer 2 can also include storage capacitance area, above-mentioned array base palte
Manufacture method can also include：
Capacitance electrode 23 is formed in the storage capacitance area by patterning processes, the thickness of capacitance electrode 23 is less than power line
22 thickness；The thickness of the capacitance electrode 23 can be identical with the thickness of grid 21, and capacitance electrode 23 can pass through one with grid 21
Secondary patterning processes are formed, and specific embodiment refers to above-mentioned steps S1201~step S1206, will not be repeated here；Certainly,
The thickness of capacitance electrode 23 is also greater than grid 21, but less than the thickness of power line 22, so as to avoid in capacitance electrode
Occur " hillock " phenomenon at 23, advantageously ensure that the normal work of storage capacitance, further improve product yield.
In the present embodiment, such as Figure 14, gate metal layer 2 can also include grid line area, the manufacture of above-mentioned array base palte
Method can also include：
The zone of intersection for including intersecting on grid line 24, grid line 24 with signal wire 8 is formed in the grid line area by patterning processes,
The thickness of the grid line 24 of the zone of intersection is less than the thickness of power line 22.Wherein it is possible to only make the grid line 24 of the zone of intersection
Thickness is identical with the thickness of grid 21, and the thickness in other regions of grid line 24 can also be made also identical with the thickness of grid 21；Letter
Number line 8 can be used for thin film transistor (TFT) input drive signal.
Grid line 24 can be formed with grid 21 by a patterning processes, and specific embodiment refers to above-mentioned steps S1201
~step S1206, will not be repeated here；Certainly, the thickness of the grid line 24 of the zone of intersection is also greater than grid 21, but less than electricity
The thickness of source line 22.So as to avoid the grid line 24 in the zone of intersection from " hillock " phenomenon occur, prevent grid line 24 with
Signal wire 8 is short-circuit because of " hillock " phenomenon；Meanwhile, the thickness reduction of the grid line 24 of the zone of intersection, it is possible to decrease signal wire 8
Climbing difficulty in the zone of intersection, prevents signal wire 8 to be broken because the gradient of climbing is excessive, advantageously ensures that the He of signal wire 8
The normal work of grid line 24, further improves product yield.
In the present embodiment, such as Figure 11~Figure 14, after grid 21 is formed, formed before gate insulation layer 5, above-mentioned array
The manufacture method of substrate can also include：
Antioxidation coating 9 is formed on the underlay substrate 1 including grid 21；
By patterning processes formation antioxidation coating pattern, the antioxidation coating pattern at least covers thick in gate metal layer 2
Degree is less than the region of the thickness of power line 22, and any thickness is less than the area of power line 22 in antioxidation coating 9 and gate metal layer 2
The thickness sum in domain is less than the thickness of power line 22.
The material of above-mentioned antioxidation coating 9 can be metal, such as molybdenum, but be not limited, and can also be that others can be led
Electric and not oxidizable material；Above-mentioned antioxidation coating pattern can not only cover thickness in gate metal layer 2 and be less than power line 22
Thickness region, the other regions for the gate metal layer 2 that power line 22 etc. is remained can also be covered.Gate metal layer 2
The region that upper thickness is less than power line 22 can include above-mentioned grid 21, capacitance electrode 23 and the grid line 24 of the zone of intersection, to protect
Even if card is after antioxidation coating pattern is formed, above-mentioned grid 21, capacitance electrode 23 and the three of grid line 24 of the zone of intersection it is respective
Thickness of the thickness still less than power line 22.It can play anti-oxidation by above-mentioned antioxidation coating pattern, and further avoid the occurrence of
" hillock " phenomenon.
In the present embodiment, it can include above by the method for patterning processes formation antioxidation coating pattern：
After above-mentioned steps S1204 is completed, carry out before above-mentioned steps S1205, deposition once covers gate insulator 2
Antioxidation coating 9；
After above-mentioned steps S1206 has been carried out, thickness is less than the oxygen in the region of the thickness of power line 22 in gate metal layer 2
Change layer 9 to be removed, the antioxidation coating 9 of covering gate insulator 2 can be deposited again, and remove and step 1202 using photoetching process
In the corresponding antioxidation coating 9 in complete removal area, to obtain antioxidation coating pattern.
Certainly, it can also be above by the method for patterning processes formation antioxidation coating pattern：Carrying out above-mentioned steps
After S1206, redeposition covering gate metal layer 2 antioxidation coating 9, and by photoetching process remove with it is complete in step 1202
The corresponding antioxidation coating 9 in area is removed, to obtain antioxidation coating pattern.
It should be noted that although each step of method in the disclosure is described with particular order in the accompanying drawings,
This does not require that or implied must perform these steps according to the particular order, or have to carry out the step shown in whole
Desired result could be realized.It is additional or alternative, it is convenient to omit some steps, multiple steps are merged into a step and held
OK, and/or by a step execution of multiple steps etc. are decomposed into.
This example embodiment also provides a kind of array base palte, such as Figure 11~Figure 14, and the array base palte of present embodiment can
With including underlay substrate 1, power line 22 and thin film transistor (TFT).
In the present embodiment, power line 22 can be on underlay substrate 1.
In the present embodiment, thin film transistor (TFT) can be on underlay substrate 1, and the thin film transistor (TFT) can include grid
Pole 21, gate insulation layer 4, active layer 5, Source and drain metal level 6, grid 21 are set with power line 22 with layer, and the thickness of grid 21 is small
In the thickness of power line 22.
In the present embodiment, above-mentioned array base palte can also include storage capacitance, and the storage capacitance includes capacitance electrode
23, capacitance electrode 23 is set on underlay substrate 1 and with layer with grid 21, and the thickness of capacitance electrode 23 is less than power line 22
Thickness.
In the present embodiment, the array base palte also includes grid line 24 and signal wire 8, and grid line 24 can be located at underlay substrate
Set on 1 and with grid 21 with layer, grid line 24 includes the zone of intersection；
Signal wire 8 in the zone of intersection can intersect located at the top of grid line 24 and with grid line, and with the grid line of the zone of intersection
24 thickness is less than the thickness of power line 22；Signal wire 8 can be used for thin film transistor (TFT) input drive signal.
In the present embodiment, the array base palte can also include antioxidation coating pattern, and the antioxidation coating pattern can be set
Between gate metal layer 2 and gate insulation layer 4, and the antioxidation coating pattern at least covers thickness in gate metal layer 2 and is less than
Any thickness is less than the thickness in the region of power line 22 on the region of the thickness of power line 22, and antioxidation coating 9 and gate metal layer 2
Spend the thickness that sum is less than power line 22.
It should be noted that the details of the array base palte each several part of this example embodiment refers to above-mentioned array base palte
The embodiment of manufacture method, will not be repeated here.
This example embodiment also provides a kind of display device, and the display device of present embodiment can include any of the above-described
Array base palte described in embodiment.
The array base palte and display device of disclosure example embodiment, because the thickness of the grid 21 of thin film transistor (TFT) is small
In the thickness of power line 22, so as to can both avoid reducing the thickness of power line 22, it is ensured that the line resistance and pressure drop of power line 22, again
It can prevent from causing " koppie " occur in grid 21 because the thickness of grid 21 is excessive, i.e. " hillock " phenomenon, so as to ensure
The normal work of thin film transistor (TFT).Thus, the yield of product can be improved.
Those skilled in the art will readily occur to its of the disclosure after considering specification and putting into practice invention disclosed herein
Its embodiment.The application is intended to any modification, purposes or the adaptations of the disclosure, these modifications, purposes or
Person's adaptations follow the general principle of the disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.Description and embodiments are considered only as exemplary, and the true scope of the disclosure and spirit are by appended
Claim is pointed out.
Claims (10)
1. a kind of manufacture method of array base palte, it is characterised in that including：
Being formed on underlay substrate at least includes the gate metal layer in thin film transistor region and power line area；
Grid is formed in the thin film transistor region by patterning processes and power line, and the grid are formed in the power line area
The thickness of pole is less than the thickness of the power line；
Gate insulation layer, active layer and the Source and drain metal level of stacking are formed in the thin film transistor region by patterning processes, with
Obtain thin film transistor (TFT).
2. the manufacture method of array base palte according to claim 1, it is characterised in that the gate metal layer also includes depositing
Capacitive region is stored up, the manufacture method of the array base palte also includes：
Capacitance electrode is formed in the storage capacitance area by patterning processes, the thickness of the capacitance electrode is less than the power line
Thickness.
3. the manufacture method of array base palte according to claim 1 or 2, it is characterised in that the gate metal layer is also wrapped
Grid line area is included, the manufacture method of the array base palte also includes：
The zone of intersection for including intersecting on grid line, the grid line with signal wire is formed in the grid line area by patterning processes, it is described
The thickness of the grid line of the zone of intersection is less than the thickness of the power line.
4. the manufacture method of array base palte according to claim 1, it is characterised in that after the grid is formed, is formed
Before the gate insulation layer, the manufacture method of the array base palte also includes：
Antioxidation coating is formed on the underlay substrate including the grid；
By patterning processes formation antioxidation coating pattern, the antioxidation coating pattern at least covers thickness in the gate metal layer
It is less than the electricity less than any thickness on the region of the thickness of the power line, and the antioxidation coating and the gate metal layer
The thickness sum in the region of source line is less than the thickness of the power line.
5. the manufacture method of array base palte according to claim 1, it is characterised in that described in the thin film transistor region
Forming grid and forming power line in the power line area includes：
The coating photoresist layer in the gate metal layer；
Using intermediate tone mask version the photoresist layer is exposed and developed, with least obtain removing completely area, with it is described
The corresponding reserved area in power line area and half reserved area corresponding with the thin film transistor region；
The gate metal layer that the complete removal area exposes is removed using etching technics；
The photoresist of half reserved area is removed using cineration technics, exposes the gate metal layer of the thin film transistor region；
The gate metal layer of the thin film transistor region is thinned using etching technics；
The photoresist layer of the reserved area is removed using stripping technology.
6. a kind of array base palte, it is characterised in that including：
Underlay substrate；
Power line, on the underlay substrate；
Thin film transistor (TFT), on the underlay substrate, and the thin film transistor (TFT) includes grid, gate insulation layer, active layer, source
Metal level is leaked, the grid is set with the power line with layer, and thickness of the thickness less than the power line of the grid.
7. array base palte according to claim 6, it is characterised in that the array base palte also includes：
Storage capacitance, the storage capacitance includes capacitance electrode, the capacitance electrode on the underlay substrate and with it is described
Grid is set with layer, and thickness of the thickness less than the power line of the capacitance electrode.
8. the array base palte according to claim 6 or 7, it is characterised in that the array base palte also includes：
Grid line, is set, the grid line includes the zone of intersection on the underlay substrate and with the grid with layer；
Signal wire, intersects above the grid line and in the zone of intersection with the grid line, and with described in the zone of intersection
The thickness of grid line is less than the thickness of the power line.
9. array base palte according to claim 8, it is characterised in that the array base palte also includes：
Antioxidation coating pattern, between the gate metal layer and the gate insulation layer, the antioxidation coating pattern at least covers
Cover the region that thickness in the gate metal layer is less than the thickness of the power line, and the antioxidation coating and the gate metal
Any thickness is less than the thickness of the thickness sum less than the power line in the region of the power line on layer.
10. a kind of display device, it is characterised in that including：
Array base palte described in any one of claim 6~9.
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| CN107068692B (en) | 2020-12-18 |
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