CN107037350A - IC test structure with monitoring chain and test lead - Google Patents
IC test structure with monitoring chain and test lead Download PDFInfo
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- CN107037350A CN107037350A CN201610849441.8A CN201610849441A CN107037350A CN 107037350 A CN107037350 A CN 107037350A CN 201610849441 A CN201610849441 A CN 201610849441A CN 107037350 A CN107037350 A CN 107037350A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
The present invention relates to the IC test structure with monitoring chain and test lead.The aspect of the present invention provides a kind of integrated circuit (integrated circuit；IC) test structure.IC structures according to the present invention may include：Chain is monitored, its first end is electrically connected with by a plurality of plain conductor respectively in one of them of the first metal layer level and second metal layer level and the second end, wherein, the first metal layer level is spaced vertically apart from the second metal layer grade；First test lead, positioned at the first metal layer level in and extend in a first direction, wherein, first test lead is electrically insulated with the monitoring chain；And second test lead, extend in second metal layer level and in a second direction, wherein, second test lead is electrically insulated with the monitoring chain and first test lead, and wherein, the first direction is different from the second direction.
Description
Technical field
Theme disclosed herein is related to for integrated circuit (integrated circuit；IC method) and test
Structure.Especially, aspect of the invention is related to measurable IC chip and its component (such as metal level layer and interlayer therein Jie
Electric matter) reliability test and monitoring structure.
Background technology
Each IC of specific device can be filled by billions of interconnection on one or more chips of semiconductor substrate materials
Put such as transistor, resistor, capacitor and diode composition.The quality and feasibility of product including IC can be at least partly
Dependent on to manufacture the IC and the wherein technology of the structure of various assemblies.IC manufacture may include two stages：Front end work
Skill (front-end-of-line；FEOL) manufacture method and backend process (back-end-of-line；BEOL) manufacturer
Method.FEOL is generally included to be implemented on wafer until and including first " metal level " of formation (namely fills several semiconductors
Put the plain conductor linked together) manufacture manufacture method.BEOL generally includes the system to be formed after the first metal layer level
Manufacture method is made, includes the formation of all subsequent metal levels.In order that manufactured device have larger scalability and
Precision, can change the number of metal level to be adapted to specific application, for example, provide four to six metal levels, or another
The metal level of up to 16 or more is provided in outer example.
Two or more metals level can be by using vertical metal wire (also referred to as " via ") electrically interconnection.Except it
Beyond its intermetallic metal level, each via may pass through one or more interlayer dielectric material regions.Via can bring great system
Challenge is made, because single fracture contact or electrical short can influence the operation of whole product.Therefore, including such as interlayer dielectric
In the case that matter is extremely thin and in the case of a large amount of vias, Accurate Prediction or possible outstanding with signal display chip level crash rate
To be important.Traditional test structure may include plain conductor conductive chain that is long and interweaving.The test structure of these types may be
High resistance simultaneously causes crash rate to be over-evaluated, because test electric current has similar magnitude to " leakage " electric current.Substituting test structure may
It is more sensitive to curent change, but may be because the difference of its fabric is without testing worst-case.
The content of the invention
The first aspect of the present invention provides a kind of integrated circuit (integrated circuit；IC) test structure, the survey
Examination structure includes：Monitor chain, its first end by respectively be located at the first metal layer level and second metal layer level one of them in
A plurality of plain conductor and the second end be electrically connected with, wherein, the first metal layer level grade is spaced vertically apart from the second metal layer；The
One test lead, in the first metal layer level and is extended in a first direction, wherein, first test lead and the monitoring chain
It is electrically insulated；And second test lead, extend in second metal layer level and in a second direction, wherein, second survey
Examination wire is electrically insulated with the monitoring chain and first test lead, and wherein, the first direction is different from the second direction.
The second aspect of the present invention provides a kind of integrated circuit (IC) test structure, and the test structure includes：Chain is monitored, its
First end passes through a plurality of plain conductor and second respectively in one of them of the first metal layer level and second metal layer level
End is electrically connected with, wherein, the first metal layer level is spaced vertically apart from second metal layer level；First test lead, positioned at this
One metal level is interior and extends in a first direction, wherein, first test lead is electrically insulated with the monitoring chain；And second survey
Wire is tried, is extended in second metal layer level and in a second direction, wherein, the first direction is different from the second direction；
Interconnecting through-hole, and first test lead and wherein one electric property coupling of second test lead, and from the first metal layer
Level extends to second metal layer level.
The 3rd aspect of the present invention provides a kind of integrated circuit (IC) test structure, and the test structure includes：Chain is monitored, its
First end passes through a plurality of plain conductor and second respectively in one of them of the first metal layer level and second metal layer level
End is electrically connected with, wherein, the first metal layer level is spaced vertically apart from second metal layer level；A plurality of first test lead, respectively
Positioned at the first metal layer level in and extend in a first direction, wherein, respectively a plurality of first test lead and the monitoring chain are electrical
Insulate and be laterally positioned between the two of which of a plurality of plain conductor；And a plurality of second test lead, respectively positioned at this
Extend in two metal levels and in a second direction, wherein, respectively a plurality of second test lead is electrically insulated and horizontal with the monitoring chain
To between the two of which positioned at a plurality of plain conductor, and wherein, the first direction is different from the second direction.
Brief description of the drawings
This of the present invention will be better understood from the detailed description for the various aspects of the invention made with reference to the accompanying drawings
A little and further feature, those accompanying drawings show various embodiments of the present invention, wherein：
Plan view of the IC test structures of Fig. 1 display foundation embodiments of the invention in plane X-Y.
The phantom of the IC test structures in plane X-Z of Fig. 2 displays according to embodiments of the invention.
Another phantom of the IC test structures of Fig. 3 display foundation embodiments of the invention in plane X-Z.
Another plan view of IC test structures in plane X-Y of Fig. 4 displays according to embodiments of the invention.
Another plan view of IC test structures in plane X-Y of Fig. 5 displays according to embodiments of the invention.
It should be noted that the accompanying drawing of the present invention is not necessarily drawn to scale.Those accompanying drawings are intended to only show the typical state of the present invention
Sample, therefore should not be considered as limiting the scope of the invention.In those accompanying drawings, similar reference is represented between those accompanying drawings
Similar element.
Embodiment
The various aspects of the present invention can provide integrated circuit (IC) test structure, and the structure is provided to the quick of wrong or defect
Perception, and the various test status of test (for example whether there is via to via and/or via to breakdown of conducting wires) energy
Power.In one embodiment, the IC test structures according to the present invention may include monitoring chain (as a component), and its first end is led to
Cross the plain conductor respectively in first or the second metal layer level of the IC and the second end is electrically connected with.It is used herein
Term " monitoring chain " is often referred to the electronic circuit being made up of the plain conductor and via in two or more metals hierarchical layers,
And it may be structured to include serpentine configuration.Monitoring chain with serpentine configuration may include for example horizontal and/or vertically coat it
The part of its circuit element, so as to provide and other circuit elements are neighbouring and the circuit that electrically isolates.In the situation of material failure
Under, the monitoring chain in same material may disconnect and therefore produce zero current when being subjected to test voltage.IC this first
And second metal layer level can be mutually perpendicular to separate, and the monitoring chain can be set as snakelike monitoring chain in itself, wherein, for example, this
Plain conductor in one metal level is extended in a first direction respectively, and each plain conductor in second metal layer level can be distinguished
Extend along different second directions.In addition to the monitoring chain, the IC test structures may also include in the first metal layer level
But the one or more the first test leads being electrically insulated with the monitoring chain so that first test lead be basically parallel to this
The plain conductor extension of the monitoring chain in two metal levels.The IC structures may also include in second metal layer level simultaneously
The one or more the second test leads for extending along the second direction but being electrically insulated with the monitoring chain and first test lead.
Fig. 1 is refer to, it shows the plan view of the IC test structures 10 according to embodiments of the invention.IC test structures
10 can be located in IC chip 12, and can include wherein in multiple layers, these layers at least two layers of the IC chip is respectively set to the
One and second metal layer level.In Fig. 1 (adding Fig. 4 and 5), the element in the first metal layer level M1 is without intersecting hachure table
Show, and the element in second metal layer level MN is represented with intersecting hachure.The sectional view of metal level M1, MN is provided in figure
In 2 and 3, and other places are discussed herein, to further illustrate.As the metal level of direct neighbor or with centre
Metal and insulator level (Fig. 1 omissions) are therebetween, and first and second metal level M1, MN can be mutually perpendicular to separate (for example
Along " Z " axle shown in Fig. 2 and 3).
IC test structures 10 may include monitoring chain 14, and the monitoring chain extends between the end 18 of first end 16 and second, with shape
Portion into the continuous circuits with serpentine path, including the first metal layer level M1 and second metal layer level MN of IC chip 12
Point.First end 16 can be with the electric property coupling of the first testing cushion 20, and the second end 18 can be with the electric property coupling of the second testing cushion 22.Although the
One end 16 and the first testing cushion 20 are illustrated within second metal layer level MN and the second end 18 and the second testing cushion 22 are shown as
In the first metal layer level M1, it is to be understood that, monitoring chain 14 can begin and end with identical metal level, but in its portion
Divide and extend through different metal levels.Monitoring chain 14 may include a plurality of plain conductor 24, and respectively the plain conductor can be by arbitrarily working as
Electrical conductive material composition that is preceding known or developing later, including such as copper (Cu), aluminium (Al), silver-colored (Ag), golden (Au), its combination
Deng.During operation, test electric current and/or voltage can put on monitoring chain 14, to produce electrical response.From monitoring chain 14 and
The electrical response produced by other current-carrying parts of IC test structures 10 discussed herein may include and IC chip 12
When the related any type information of state, such as particular lead or circuit disconnect, resistance variations betide when or where etc..
The structure problem of the signable IC chip 12 of any change of the response in test process, such as fracture or warpage.Accordingly, with respect to
The electrical information of circuit can be used to determine whether IC chip 12 is damaged during manufacture and/or after deployment.For example pass through compiling
About each circuit and/or the response data of wire in IC chip 12, what compiling was obtained from each tested part of IC chip 12
Response data can perform the processing of test result, to point out when electrical Behavioral change occurs, and then point out that electrically interruption is
No is electrical short or material failure because in such as specific region.
One group of plain conductor 24 can be formed and be located at and be electrically insulated or semiconductor material layer (such as semi-conducting material or electrical
Insulating dielectric materials area) in, so that plain conductor 24 is transmitted electricity between the other electrical conductive structures being in contact with it.Positioned at first
Plain conductor 24 in metal level M1 can extend (such as parallel to Y-axis) in the first direction, and positioned at second metal layer level MN
Interior plain conductor 24 can extend along the second direction (such as parallel to X-axis) different from the first direction.Although this first with
Example is shown as being substantially orthogonal to each other second direction in Fig. 1, it is to be understood that, first and second direction can relative to each other with
Any nonparallel angular orientation.Plain conductor in different metal level (such as first and second metal level M1, MN)
24 can extend the via 26 between first and second metal level M1, MN and be electrically connected with each other by being respectively perpendicular.Via 26
Can be by being constituted with the electrical conductive material of each identical of plain conductor 24, or can be by one or more different conductive material groups
Into.Via 26 is shown with different intersecting hachures, is extended vertically into indicating each via 26 in IC chip 12.In an implementation
In example, each via 26 may include the conducting metal (such as copper) of arbitrary standards, thereon with lining material (not shown), such as nitrogen
Change tantalum.
Although monitoring chain 14 can effectively measure short circuit and open circuit in for example whole IC chip 12, first and second end
16th, the length of the monitoring chain 14 between 18 can influence to monitor sensitiveness of the chain 14 to curent change, so as to whether to cause defect
The excessive pessimistic measurement occurred.For these attributes of compensation monitoring chain 14, IC test structures 10 may include to be located in IC chip 12
At least one the first test leads 28 and at least one the second test leads 30.One or more the first test leads 28 can
In the first metal layer level M1, it is orientated along the first direction, that is, parallel to plain conductor 24.One or more the first survey
Examination wire 28 can also be electrically insulated with monitoring chain 14, to make the behavior of electric current therein and voltage during testing independently of monitoring
Chain 14.In the case of including a plurality of first test lead 28, the first ridge wire 32 can be by each first test lead 28 and first
The electric property coupling of test lead pad 34, to measure the electric current between such as the one or more the first test leads 28 and monitoring chain 14
And/or voltage drop.First ridge wire 32 can substantially along the second direction (such as parallel to X-axis) or perpendicular to and/or be different from
The other direction extension in the direction of the first test lead 28.In the case of including a plurality of second test lead 30, IC test knots
Structure 10 may include the second ridge wire 36 with the electric property coupling of the second test lead pad 38.Second ridge wire 36 can be along the first direction
(such as parallel to Y-axis) extension, or can prolong in addition along the direction perpendicular to and/or different from the second test lead 30
Stretch.Each second test lead 30 can electrically disconnect with the one or more the first test leads 28 and monitoring chain 14, so that second surveys
Examination conductor pads 38 can be used to the electric current and/or voltage row between the test lead 30 of measurement one or more the second and monitoring chain 14
For.
In one embodiment, the one or more the first test lead 28, the first ridge wire 32 and/or the first test leads
Pad 34 can be located in identical metal level (such as the first metal layer level M1) respectively.Second test lead 30, the second ridge wire
36 and/or second test lead pad 38 can be located at respectively in different metal level (such as second metal layer level MN).One or
First and second a plurality of test lead 28,30 can be extended laterally between respective wire is to 24 respectively, and be kept and plain conductor
24 electrically disconnect.Configured with this, one or more first and second test lead 28,30 can extend across in monitoring chain 14
Intermetallic metal level, so as to amount of space needed for reducing IC test structures 10 and provide extra test form.First and
Two test leads 28,30 can be each without the via (such as via 26) being electrically connected, so that first and second is surveyed
Examination wire 28,30 may make up the self-contained testing element in single metal level (such as first or second metal layer level M1, MN).
During operation, in addition to by monitoring the overall attribute for measuring IC chip 12 of chain 14, by first and second testing cushion 20,
22 and/or first and second test lead pad 34,38 on apply test voltage and measure the specific part of IC chip 12, can test
Failure in IC chip 12 whether there is.
Fig. 2 is refer to, it shows the partially cut-away side view of IC test structures 10.First and second metal level M1, MN can
It is spaced from each other by one or more intermetallic metal levels 40 (being respectively labeled as such as M2, M3, M4, M5, MN-1).Such as symbol M N
And as M1 is implied, the number of metal level can be according to selected implementation and times of backend process (BEOL) manufacture method
It is intended to ask and change.IC test structures 10 may also comprise the interlayer dielectric 42 between each intermetallic metal level 40.Each layer
Between dielectric medium 42 may include that one or more are electrically insulated material, include but is not limited to：Silicon nitride (Si3N4), silica
(SiO2), it is fluorinated SiO2(FSG), hydrogenation siloxicon (SiCOH), porous SiC OH, boron-phosphorus-silicate glass (BPSG), sesquialter
Siloxanes, including silicon (Si), carbon (C), carbon (C) doping oxide (namely organic silicic acid of oxygen (O) and/or hydrogen (H) atom
Salt), thermosetting polyarylene ethers, SiLK (a kind of polyarylether that can be obtained from Dow Chemical) includes what can be obtained from JSR companies
The spin coating silicon-carbon of polymeric material, other low-ks (<3.9) material, or its layer.In certain embodiments, it should also manage
Solution, different interlayer dielectrics 42 can be made up of the different materials with corresponding differing dielectric constant.In one embodiment, one
Individual or multiple vias 26 can extend to adjacent metal level from a metal level, so that the first metal layer level M1 is (such as minimum
Metal level) in one or more plain conductor 24 can with second metal layer level MN (the highest metal levels of such as IC chip 12
Level) in one or more plain conductor 24 be electrically connected with.
Fig. 3 is refer to, it shows another phantom of the IC test structures 10 in one embodiment of the present of invention.
In figure 3, interlayer dielectric 42 is represented by dotted lines, setting can parameter to be indicated between first and second metal level M1, MN
Purpose intermetallic metal level 40 and dielectric layer 42.Monitoring chain 14, which can be formed, extends through first and second metal level M1, MN
Each plain conductor 24 for monitoring chain 14 is coupled together by circuit, via 26.In the first metal layer level M1, one or more the
One test lead 28 can be laterally positioned between one group of first plain conductor 24, and can be extended laterally into and/or be gone out the flat of the page
Face.Similarly, the second test lead 30 can be laterally positioned between one group of second plain conductor 30 in second metal layer level MN, and
It can extend laterally into and/or go out the plane of the page.
Referring now to Fig. 4, it shows the embodiment of the IC test structures 10 with supernumerary structure feature.Especially, monitor
Chain 14 can optionally included between first and second end 16,18 of monitoring chain 14 with monitoring chain 14 in electrical contact one or
Multiple middle testing cushions 50.Each middle testing cushion 50 can be located in identical metal level and (for example be located at first or second respectively
In metal level M1, MN) or can be located in different metal levels.For example, any via 26 in IC chip 12 and/or
After interlayer dielectric 42 (Fig. 2,3) failure, by reducing the total voltage drop on monitoring chain 14 and/or allowing partial test to monitor
Chain 14, middle testing cushion 50 can provide extra test function in IC test structures 10.By increasing the survey in IC chip 12
The number of component is tried, and in the case where first and second test lead 28,30 keeps being electrically insulated with monitoring chain 14, middle pad
50 can allow to carry out the specific part of IC chip 12 together with the first and/or second test lead pad 34,38 electrical short and/
Or leak-testing.
Fig. 5 is refer to, it shows another embodiment of IC test structures 10.IC structures 10 may include first end for example
The monitoring chain 14 that 16 the first testing cushion 20 and second testing cushion 22 at the second end 18 are electrically connected with.Except one or more the first and
Beyond second test lead 28,30, IC test structures 10 may include interconnecting through-hole 52, the interconnecting through-hole by each test lead 28,
30 are electrically connected with another metal level.For example, interconnecting through-hole 52 can survey one or more the first of the first metal layer level M1
The part for trying wire 28 and second metal layer level MN is electrically connected with, while interconnecting through-hole 52 can be by one of second metal layer level MN
Or the part of a plurality of second test lead 30 and the first metal layer level M1 is electrically connected with.Although interconnecting through-hole 52 can be by one or many
First and second test lead 28,30 of bar is electrically connected with other metal levels, but each test lead 28,30 can be with monitoring chain 14
Holding is electrically insulated, to avoid the formation of electrical short or merge independent test element.For example, as shown in Figure 5, interconnecting through-hole 52
First and/or second can be contacted in the position of not vertical neighbouring test lead 28,30 or the plain conductor 24 for monitoring chain 14
Test lead 28,30.Among other things, the interconnecting through-hole 52 being included in IC test structures 50 can allow in IC structures 10
Via to via is tested, so as to provide extra material stress or failure measurement.
As the other embodiments of IC test structures 10, interconnecting through-hole 52 is accessible to be located at such as two articles corresponding the respectively
One or second between test lead 28,30 and first and second a plurality of test lead 28,30 of extension substantially parallel with its its
In one, to increase the versatility and coverage rate of IC test structures 10.It is also understood that if appropriate, Fig. 4 and 5 can be combined
Shown in embodiment, so as in single implementation in the lump provide in the middle of testing cushion 50 (Fig. 4) with interconnecting through-hole 52.In addition,
Some test leads 28,30 can not have interconnecting through-hole 50 thereon, to keep monitoring chain 14 to be led with the first and/or second test
Electrically isolating between line 28,30.
Embodiments of the invention specifically described herein can provide several technologies and commercial benefit, and some of them are shown herein
Example explanation.For measurement electrical short, open circuit and/or other attributes such as dielectric reliability, the single implementation of IC test structures 10
Example can be provided for example, by monitoring chain 14, the one or more the first test leads 28 and the one or more the second test leads 30
Multiple test sources, while reducing the parasitic voltage drops in monitoring chain 14 and other test devices.In addition, being surveyed by first and second
The ability of the state of the independent monitoring IC chip 12 of examination wire 28,30, which can be provided, effectively to be determined in monitoring chain 14 or (in general) IC
The position of electrical short or structure failure (for example monitor chain 14 and produce null response (such as no-voltage or electric current)) in chip 12
The test structure put.It is also understood that the electricity for providing combinational logic can be combined according to the test performed by embodiments of the invention
Road is implemented and/or used.For example, design and the predetermined attribute of structure according to IC test structures 10, with IC test structures 10
The logic circuit or equality testing device of electric property coupling can provide boolean properties to test such as specific region or level dielectric
The presence or absence of material breakdown.
Method disclosed herein and structure provide interlayer dielectric material (such as interlayer between just such as metal level
Dielectric medium 42) the factor such as number/width test IC chip 12 domain feasibility structure.Especially, IC test structures 10 can be
Can test structure including being provided in the region of the IC chip 12 of high concentration via (such as via 26).By using herein
Described IC test structures 10, the attribute of proposed IC chip 12 can be measured during manufacture and/or later, to determine for example
Produce the size or physical attribute of the interlayer dielectric 42 of large domain feasibility.If for example, monitoring chain 14 is in specific region
Interrupt or be broken, then one or more first and second test lead 28,30 can be used to taking correct action or design modification
It is previously determined ad-hoc location or set of locations that failure occurs.
Term used herein is only in order at the purpose of explanation specific embodiment, is not intended to the limitation present invention.Remove
Explicitly pointed out in addition in non-context, otherwise singulative " one " and "the" used herein are also intended to include plural number
Form.In addition, it will be appreciated that term " comprising " shows the feature, entirety, step, operation, element when being used in this specification
And/or the presence of component, but do not preclude the presence or addition of one or more of the other feature, entirety, step, operation, element, group
Part, and/or its group.
All means or step in the claim add corresponding construction, material, action and the equivalent of functional element
It is intended to the arbitrary structures, material or action for including performing the function with reference to specific claimed other claimed elements.
The explanation of the present invention is used for example and illustration purpose, and is not intended to exposure that is exhaustive or being limited to disclosed form.Many is repaiied
Change and change will for it would be apparent to one of skill in the art that, without departing from the scope of the present invention and spirit.Embodiment
It is chosen and explanation with best interpretations the present invention principle and practical application, and make one of ordinary skill in the art it will be appreciated that
The present invention has the different change for being adapted to considered application-specific for different embodiments.
Claims (20)
1. a kind of IC test structure, including：
Chain is monitored, its first end passes through a plurality of gold respectively in one of them of the first metal layer level and second metal layer level
Belong to wire and the second end is electrically connected with, wherein, the first metal layer level is spaced vertically apart from second metal layer level；
First test lead, positioned at the first metal layer level in and extend in a first direction, wherein, first test lead with should
Monitoring chain is electrically insulated；And
Second test lead, extends in second metal layer level and in a second direction, wherein, second test lead is with being somebody's turn to do
Monitoring chain and first test lead are electrically insulated, and wherein, the first direction is different from the second direction.
2. IC test structure as claimed in claim 1, wherein, first test lead includes being located at first metal
Wherein one, and wherein of a plurality of first test lead extended in level and along the first direction, respectively a plurality of first survey
Examination wire is electrically connected with the first ridge wire for extending and being located in the first metal layer level along the second direction.
3. IC test structure as claimed in claim 2, wherein, at least one of of a plurality of first test lead
Between the two of which for being laterally positioned in a plurality of plain conductor.
4. IC test structure as claimed in claim 2, wherein, second test lead includes being located at second metal
Wherein one, and wherein of a plurality of second test lead extended in level and along the second direction, respectively a plurality of second survey
Examination wire is electrically connected with the second ridge wire for extending and being located in second metal layer level along the first direction.
5. IC test structure as claimed in claim 5, wherein, at least one of of a plurality of second test lead
Between the two of which for being laterally positioned in a plurality of plain conductor.
6. IC test structure as claimed in claim 1, is additionally included in the first end and second end of the monitoring chain
Between testing cushion with the monitoring chain electric property coupling.
7. IC test structure as claimed in claim 1, wherein, respectively first and second test lead does not have and it
The via of electric connection.
8. IC test structure as claimed in claim 1, wherein, at least one intermetallic metal level is by first metal
Level is separated with second metal layer level.
9. a kind of IC test structure, including：
Chain is monitored, its first end passes through a plurality of gold respectively in one of them of the first metal layer level and second metal layer level
Belong to wire and the second end is electrically connected with, wherein, the first metal layer level is spaced vertically apart from second metal layer level；
First test lead, positioned at the first metal layer level in and extend in a first direction, wherein, first test lead with should
Monitoring chain is electrically insulated；And
Second test lead, extends in second metal layer level and in a second direction, wherein, the first direction is different from should
Second direction；
Interconnecting through-hole, and first test lead and wherein one electric property coupling of second test lead, and from first gold medal
Category level extends to second metal layer level.
10. IC test structure as claimed in claim 9, wherein, first test lead includes being located at first gold medal
Wherein one, and wherein of a plurality of first test lead for belonging in level and extending along the first direction, respectively this plurality of first
Test lead is electrically connected with the first ridge wire for extending and being located in the first metal layer level along the second direction.
11. IC test structure as claimed in claim 10, wherein, the interconnecting through-hole and a plurality of first test lead
Wherein one electric property coupling, and be laterally positioned between the two of which of a plurality of test lead.
12. IC test structure as claimed in claim 10, wherein, the interconnecting through-hole includes its of multiple interconnecting through-holes
In one, wherein one coupling of each the plurality of interconnecting through-hole and a plurality of first test lead, and wherein, this plurality of first
At least one of of test lead does not have the interconnecting through-hole being electrically connected.
13. IC test structure as claimed in claim 10, wherein, a plurality of first test lead it is at least one of
Bar is laterally positioned between the two of which of a plurality of plain conductor.
14. IC test structure as claimed in claim 10, wherein, second test lead includes being located at second gold medal
Wherein one, and wherein of a plurality of second test lead for belonging in level and extending along the second direction, respectively this plurality of second
Test lead is electrically connected with the second ridge wire for extending and being located in second metal layer level along the first direction.
15. IC test structure as claimed in claim 9, is additionally included in the first end and second end of the monitoring chain
Between testing cushion with the monitoring chain electric property coupling.
16. IC test structure as claimed in claim 9, wherein, at least one intermetallic metal level is by first gold medal
Category level is separated with second metal layer level.
17. a kind of IC test structure, including：
Chain is monitored, its first end passes through a plurality of gold respectively in one of them of the first metal layer level and second metal layer level
Belong to wire and the second end is electrically connected with, wherein, the first metal layer level is spaced vertically apart from second metal layer level；
A plurality of first test lead, in the first metal layer level and is extended in a first direction respectively, wherein, respectively this plurality of the
One test lead and the monitoring chain are electrically insulated and are laterally positioned between the two of which of a plurality of plain conductor；And
A plurality of second test lead, extends in second metal layer level and in a second direction respectively, wherein, respectively this plurality of the
Two test leads and the monitoring chain are electrically insulated and are laterally positioned between the two of which of a plurality of plain conductor, and wherein,
The first direction is different from the second direction.
18. IC test structure as claimed in claim 17, in addition to：
First ridge wire, is electrically connected with the first metal layer level and with a plurality of first test lead, wherein, this first
Ridge wire extends along the second direction；And
Second ridge wire, is electrically connected with second metal layer level and with a plurality of second test lead, wherein, this second
Ridge wire extends along the first direction.
19. IC test structure as claimed in claim 17, in addition to multiple interconnecting through-holes, respectively with first test
Wherein one electric property coupling of wire and second test lead, and extend to the second metal layer from the first metal layer level
Level.
20. IC test structure as claimed in claim 17, wherein, respectively a plurality of first test lead and this plurality of
Two test leads do not have the via being electrically connected.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/862,587 | 2015-09-23 | ||
| US14/862,587 US9435852B1 (en) | 2015-09-23 | 2015-09-23 | Integrated circuit (IC) test structure with monitor chain and test wires |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107037350A true CN107037350A (en) | 2017-08-11 |
| CN107037350B CN107037350B (en) | 2019-10-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610849441.8A Expired - Fee Related CN107037350B (en) | 2015-09-23 | 2016-09-23 | IC test structure with monitoring chain and test lead |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9435852B1 (en) |
| CN (1) | CN107037350B (en) |
| TW (1) | TWI601222B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109698138A (en) * | 2018-12-24 | 2019-04-30 | 上海华力集成电路制造有限公司 | Semiconductor failure assignment test unit and its failure positioning method |
| CN111524874A (en) * | 2019-02-01 | 2020-08-11 | 三星电子株式会社 | Test structure and evaluation method for semiconductor photoetching registration |
| CN111722089A (en) * | 2020-07-01 | 2020-09-29 | 无锡中微亿芯有限公司 | High-efficiency testing method based on hierarchical testing vector |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9799575B2 (en) | 2015-12-16 | 2017-10-24 | Pdf Solutions, Inc. | Integrated circuit containing DOEs of NCEM-enabled fill cells |
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| KR20200122673A (en) | 2019-04-18 | 2020-10-28 | 삼성전자주식회사 | Pattern disign and method for inspecting the pattern disign |
| US11682595B2 (en) | 2020-09-23 | 2023-06-20 | Western Digital Technologies, Inc. | System and method for warpage detection in a CMOS bonded array |
| CN114244402A (en) * | 2022-01-11 | 2022-03-25 | 哲弗智能***（上海）有限公司 | Test tool |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1049151A2 (en) * | 1999-04-30 | 2000-11-02 | Mitsubishi Gas Chemical Company, Inc. | Method of producing a ball grid array type printed wiring board having excellent heat diffusibility and printed wiring board |
| US6202191B1 (en) * | 1999-06-15 | 2001-03-13 | International Business Machines Corporation | Electromigration resistant power distribution network |
| CN1475030A (en) * | 2000-11-09 | 2004-02-11 | Lm��������绰��˾ | Integrated circuit inductor structure and non-destructive etch depth measurement |
| CN1612333A (en) * | 2003-10-29 | 2005-05-04 | 台湾积体电路制造股份有限公司 | Bonding pad structure |
| CN1649154A (en) * | 2004-01-26 | 2005-08-03 | 雅马哈株式会社 | Semiconductor wafer and its producing method |
| CN1806178A (en) * | 2003-06-09 | 2006-07-19 | Jsr株式会社 | Anisotropic conductive connector and wafer inspection device |
| CN101278237A (en) * | 2005-09-30 | 2008-10-01 | 先进微装置公司 | Structure and method for simultaneously determining an overlay accuracy and pattern placement error |
| CN102044464A (en) * | 2009-10-14 | 2011-05-04 | 格罗方德半导体公司 | Methods relating to capacitive monitoring of layer characteristics during back end-of-the-line processing |
| CN102445649A (en) * | 2010-10-13 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Test structure for semiconductor chip and method for measuring dielectric characteristic |
| US8717059B2 (en) * | 2011-08-31 | 2014-05-06 | Texas Instruments Incorporated | Die having wire bond alignment sensing structures |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6362634B1 (en) | 2000-01-14 | 2002-03-26 | Advanced Micro Devices, Inc. | Integrated defect monitor structures for conductive features on a semiconductor topography and method of use |
| US6576923B2 (en) | 2000-04-18 | 2003-06-10 | Kla-Tencor Corporation | Inspectable buried test structures and methods for inspecting the same |
| US7969564B2 (en) | 2002-10-03 | 2011-06-28 | Applied Materials Israel, Ltd. | System and method for defect localization on electrical test structures |
| US7198963B2 (en) | 2003-04-16 | 2007-04-03 | Kla-Tencor Technologies Corporation | Methodologies for efficient inspection of test structures using electron beam scanning and step and repeat systems |
| US7026175B2 (en) | 2004-03-29 | 2006-04-11 | Applied Materials, Inc. | High throughput measurement of via defects in interconnects |
| WO2007079477A2 (en) | 2006-01-03 | 2007-07-12 | Applied Materials Israel, Ltd | Apparatus and method for test structure inspection |
| US7679384B2 (en) | 2007-06-08 | 2010-03-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Parametric testline with increased test pattern areas |
| US9069015B2 (en) * | 2012-07-12 | 2015-06-30 | Technoprobe S.P.A. | Interface board of a testing head for a test equipment of electronic devices and corresponding probe head |
| US8623673B1 (en) | 2012-08-13 | 2014-01-07 | International Business Machines Corporation | Structure and method for detecting defects in BEOL processing |
| US9059052B2 (en) | 2013-05-16 | 2015-06-16 | International Business Machines Corporation | Alternating open-ended via chains for testing via formation and dielectric integrity |
-
2015
- 2015-09-23 US US14/862,587 patent/US9435852B1/en active Active
-
2016
- 2016-07-28 TW TW105123871A patent/TWI601222B/en not_active IP Right Cessation
- 2016-09-23 CN CN201610849441.8A patent/CN107037350B/en not_active Expired - Fee Related
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1049151A2 (en) * | 1999-04-30 | 2000-11-02 | Mitsubishi Gas Chemical Company, Inc. | Method of producing a ball grid array type printed wiring board having excellent heat diffusibility and printed wiring board |
| US6202191B1 (en) * | 1999-06-15 | 2001-03-13 | International Business Machines Corporation | Electromigration resistant power distribution network |
| CN1475030A (en) * | 2000-11-09 | 2004-02-11 | Lm��������绰��˾ | Integrated circuit inductor structure and non-destructive etch depth measurement |
| CN1806178A (en) * | 2003-06-09 | 2006-07-19 | Jsr株式会社 | Anisotropic conductive connector and wafer inspection device |
| CN1612333A (en) * | 2003-10-29 | 2005-05-04 | 台湾积体电路制造股份有限公司 | Bonding pad structure |
| CN1649154A (en) * | 2004-01-26 | 2005-08-03 | 雅马哈株式会社 | Semiconductor wafer and its producing method |
| CN101278237A (en) * | 2005-09-30 | 2008-10-01 | 先进微装置公司 | Structure and method for simultaneously determining an overlay accuracy and pattern placement error |
| CN102044464A (en) * | 2009-10-14 | 2011-05-04 | 格罗方德半导体公司 | Methods relating to capacitive monitoring of layer characteristics during back end-of-the-line processing |
| CN102445649A (en) * | 2010-10-13 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Test structure for semiconductor chip and method for measuring dielectric characteristic |
| US8717059B2 (en) * | 2011-08-31 | 2014-05-06 | Texas Instruments Incorporated | Die having wire bond alignment sensing structures |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109698138A (en) * | 2018-12-24 | 2019-04-30 | 上海华力集成电路制造有限公司 | Semiconductor failure assignment test unit and its failure positioning method |
| CN109698138B (en) * | 2018-12-24 | 2021-06-15 | 上海华力集成电路制造有限公司 | Semiconductor failure positioning test unit and failure positioning method thereof |
| CN111524874A (en) * | 2019-02-01 | 2020-08-11 | 三星电子株式会社 | Test structure and evaluation method for semiconductor photoetching registration |
| CN111524874B (en) * | 2019-02-01 | 2024-05-17 | 三星电子株式会社 | Test structure and evaluation method for semiconductor photoetching alignment |
| CN111722089A (en) * | 2020-07-01 | 2020-09-29 | 无锡中微亿芯有限公司 | High-efficiency testing method based on hierarchical testing vector |
| CN111722089B (en) * | 2020-07-01 | 2022-03-22 | 无锡中微亿芯有限公司 | High-efficiency testing method based on hierarchical testing vector |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107037350B (en) | 2019-10-01 |
| TWI601222B (en) | 2017-10-01 |
| US9435852B1 (en) | 2016-09-06 |
| TW201712772A (en) | 2017-04-01 |
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