CN107017256B - 半导体器件中的局部互连件及其制造方法 - Google Patents

半导体器件中的局部互连件及其制造方法 Download PDF

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CN107017256B
CN107017256B CN201611187265.2A CN201611187265A CN107017256B CN 107017256 B CN107017256 B CN 107017256B CN 201611187265 A CN201611187265 A CN 201611187265A CN 107017256 B CN107017256 B CN 107017256B
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source
drain
gate
semiconductor device
forming
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CN107017256A (zh
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赖瑞尧
杨世海
陈盈燕
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了半导体器件及其制造方法。半导体器件包括：具有第一栅极、第一源极和第一漏极的第一晶体管、具有第二栅极、第二源极和第二漏极的第二晶体管，分隔第一晶体管和第二晶体管的隔离区，以及将第一源极和第一漏极的至少一个连接至第二源极和第二漏极的至少一个的局部互连件。局部互连件与第一源极和第一漏极的至少一个的表面、第二源极和第二漏极的至少一个的表面、隔离区的一部分的表面接触。

Description

半导体器件中的局部互连件及其制造方法
技术领域
本发明的实施例涉及用于制造半导体器件的方法，更具体地，涉及用于连接源极/漏极区的局部互连件的结构以及制造方法。
背景技术
随着具有复杂布局结构的半导体器件的尺寸的减小，研发了将源极/漏极区连接至另一源极/漏极区的局部互连件。局部互连件是设置在第一金属布线层下面的导电层，并且连接具有相对短距离的各元件。在标准单元设计中，局部互连件加强了设计灵活性，并且减小了标准单元的尺寸。需要提供更具灵活性和更高可靠性的局部互连件的结构和制造工艺。
发明内容
根据本发明的一个方面，提供了一种半导体器件，包括：第一晶体管，具有第一栅极、第一源极和第一漏极；第二晶体管，具有第二栅极、第二源极和第二漏极；隔离区，由绝缘材料形成，并且分隔所述第一晶体管和所述第二晶体管；以及局部互连件，将所述第一源极和所述第一漏极中的至少一个连接至所述第二源极和所述第二漏极中的至少一个，其中：所述局部互连件与所述第一源极和所述第一漏极中的所述至少一个的表面、所述第二源极和所述第二漏极中的所述至少一个的表面、所述隔离区的一部分的表面接触。
根据本发明的另一方面，提供了一种半导体器件，包括：源/漏极区，在第一方向上延伸；隔离区，分隔所述源/漏极区；第一栅极图案，在第一方向上延伸；第二栅极图案，在所述第一方向上延伸；第三栅极图案，在所述第一方向上延伸，并且在所述第一方向上与所述第二栅极图案对准；以及局部互连件，其中：所述第二栅极图案的一端与所述第三栅极图案的一端相对同时之间具有间隔，所述局部互连件与所述源/漏极区中的至少一个的表面和所述隔离区的表面中的至少一个表面接触，以及所述局部互连件在第二方向上延伸并且穿过所述间隔，所述第二方向与所述第一方向交叉。
根据本发明的又一方面，提供了一种制造半导体器件的方法，所述方法包括：在衬底中形成隔离区；在所述衬底上方形成第一晶体管结构和第二晶体管结构，所述第一晶体管结构包括第一栅极、设置在所述第一栅极上方的第一覆盖绝缘层、设置在所述第一栅极的侧面上和所述第一覆盖绝缘层的侧面上的第一侧壁间隔件、第一源极和第一漏极，所述第二晶体管结构包括第二栅极、设置在所述第二栅极上方的第二覆盖绝缘层、设置在所述第二栅极的侧面和所述第二覆盖绝缘层的侧面上的第二侧壁间隔件，第二源极和第二漏极；在所述第一晶体管结构和所述第二晶体管结构之间形成第一绝缘层；在所述第一绝缘层中形成开口，以露出所述第一源极和所述第一漏极中的至少一个的表面，所述第二源极和所述第二漏极中的至少一个的表面，以及所述隔离区的一部分的表面；用导电材料填充所述开口以形成局部互连件。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。需要强调的是，根据行业的标准实践，各个部件未按比例绘制，并且仅用于说明目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A和图1B至图12示出了根据本发明的一个实施例的说明半导体器件的按序制造工艺的示例性视图。
图13A至图13C示出了根据本发明的各个方面的半导体器件的示意性布局结构。
具体实施方式
以下公开内容提供了许多不同的实施例或实例以实现本发明的不同特征。下面将描述元件和布置的特定实例以简化本发明。当然这些仅是实例并不旨在限定。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件所需的性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简化和清楚，可以以不同的尺寸任意地绘制各个部件。
此外，为便于描述，空间相对术语如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等在本文可用于描述附图中示出的一个元件或部件与另一个(或另一些)元件或部件的关系。空间相对术语旨在包括除了附图中所示的方位之外，在使用中或操作中的器件的不同方位。装置可以其他方式定向(旋转90度或在其他方位上)，本文使用的空间相对描述符可同样地作相应解释。另外，术语“由...制成”可以意为“包括”或者“由...组成”。
图1A和图1B至图12示出了根据本发明的一个实施例的说明半导体器件的按序制造工艺的示例性视图。在这些图中，为了简化省略了一些层/部件。应该理解，可以在这些图所示的工艺之前、期间和之后提供额外的操作，并且对于本方法的额外实施例，下述的一些操作可以替换或删除。操作/工艺的顺序可交换。
图1A和图1B示出了根据本发明的一个实施例的半导体器件的按序制造工艺的一个阶段。图1A示出了平面(顶视)图，并且图1B示出了沿着图1A的线X1-X1的截面图。
如图1A和图1B所示，被隔离绝缘区15(诸如，浅沟槽隔离)分隔开的作为有源区的鳍结构10N和10P形成在衬底的上方(未示出)。在本实施例中，鳍结构10N用于N型鳍式场效应晶体管(FinFET)，鳍结构10P用于P型FinFET。在其他实施例中，鳍结构10N和10P都用于相同导电类型FinFET。
例如，衬底是具有杂质浓度在约1×1015cm-3至约1×1018cm-3范围内的p型硅衬底。在其他的实施例中，衬底是具有杂质浓度在约1×1015cm-3至约1×1018cm-3范围内的n型硅衬底。可选地，衬底可以包括：其他元素半导体，诸如锗；化合物半导体，包括诸如SiC和SiGe的IV-IV族化合物半导体、诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的III-V族化合物半导体；或它们的组合。在一个实施例中，衬底是SOI(绝缘体上硅)衬底的硅层。
例如，鳍结构通过沟槽蚀刻(trench-etching)衬底形成。
隔离绝缘区15包括通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的一层或多层绝缘材料，诸如氧化硅、氮氧化硅或氮化硅。隔离绝缘层可以由旋涂玻璃(SOG)、SiO、SiON、SiOCN和/或掺杂氟的硅酸盐玻璃(FSG)的一层或多层形成。
在鳍结构上方形成隔离绝缘区之后，执行平坦化操作，以去除隔离绝缘区的一部分。平坦化操作可以包括化学机械抛光(CMP)和/或回蚀工艺。然后，进一步去除(开槽)隔离绝缘区，从而露出鳍结构的上部区域。
用于伪栅极和伪绝缘层(未示出)的伪层20形成在鳍结构10N、10P和隔离绝缘区15的上方。在图1A中，省略了伪层20(透明的)。例如，伪层20是通过化学汽相沉积(CVD)形成的多晶硅层。然后在伪层20上方形成硬掩模图案30。在一些实施例中，伪层20的厚度在约10nm至约35nm的范围内，并且硬掩模图案30的厚度在约50nm至约200nm的范围内。
硬掩模图案30包括一个或多个介电材料层。一个或多个介电材料的毯式层形成在伪层20的上方，并且执行包括光刻和干蚀刻的图案化操作，以获得硬掩模图案30。在一个实施例中，硬掩模图案30包括氧化硅层和设置在氧化硅层上的氮化硅层。在其他实施例中，氧化硅层设置在氮化硅层上。
接下来，如图2A和2B所示，硬掩模图案30的一些被分成多个块，每个块对应于一个伪栅极图案。图2A示出了平面(顶视)图，并且图2B示出了沿着图2A的线X1-X1的截面图。在图2A中，省略了伪层20(透明的)。
如图3A和图3B所示，通过采用分开的硬掩模图案30，伪层20被图案化为伪栅电极25。图3A示出了平面(顶视)图，并且图3B示出了沿着图3A的线X1-X1的截面图。在其他实施例中，伪层被图案化，然后将图案化的伪层分成多块。然而，在这种情况下，分开图案化的伪层可能需要针对高纵宽比图案的蚀刻。
然后，如图4A至图4C所示，在具有硬掩模图案30的图案化的伪栅电极25的上方形成用于侧壁间隔件的毯式层40。图4A示出了平面(顶视)图，并且图4B示出了沿着图4A的线X1-X1的截面图，并且图4C示出了沿着图4A的线X2-X2的截面图。
毯式层40包括通过低压CVD(LPCVD)、等离子体CVD或原子层沉积(ALD)形成的一个或多个绝缘材料(诸如，SiO2、SiN、SiCN、SiON、SiOCN)层，如图4B和图4C所示，毯式层共形地形成在具有硬掩模图案30的图案化的伪栅电极25、鳍结构和隔离绝缘区15的上方。在一个实施例中，氮化物基的绝缘材料用作毯式层40，具有的厚度在约5nm至约10nm范围内。
然后，如图5A至图5C所示，执行各向异性蚀刻，以在具有硬掩模图案30的图案化的伪栅电极25的侧壁上形成侧壁间隔件45。图5A示出了平面(顶视)图，图5B示出了沿着图5A的线X1-X1的截面图，以及图5C示出了沿着图5A的线X2-X2的截面图。
如图6A至图6C所示，在形成侧壁间隔件之后，形成源/漏极区50N、50P。图6A示出了平面(顶视)图，图6B示出了沿着图6A的线X1-X1的截面图，以及图6C示出了沿着图6A的线X2-X2的截面图。在本发明中，源极和漏极可以互换。
使未被伪栅电极覆盖的鳍结构凹进至隔离绝缘区的上部表面之下。然后，通过使用外延生长方法在凹进的鳍结构上方形成源/漏极区50N、50P。源/漏极区可以包括对沟道区施加应力的应变材料。当鳍结构是Si时，应变材料的实例是用于n型FinFET的SiC、SIP或SiCP，和用于p型FinFET的SiGe。在其他实施例中，通过离子注入形成源/漏极区。例如，由Ti、Ni、Ta、Co或W形成的硅化物层形成在源/漏极区中。
在形成源/漏极结构之后，绝缘层60形成在伪栅电极结构的上方。绝缘层60包括一层或多层的介电材料。在本实施例中，使用氧化硅或基于氧化硅的绝缘材料。然后，如图7A至图7C所示，执行诸如CMP的平坦化操作以去除绝缘层60和硬掩模图案30的在伪栅电极25上的上部。图7A示出了形成金属栅极图案之后的平面(顶视)图，图7B示出了沿着图7A的线X1-X1的截面图，以及图7C示出了沿着图7A的线X2-X2的截面图。在图7A中，省略了绝缘层60。
在平坦化操作之后，去除伪栅电极结构(伪栅电极和伪绝缘层)，以形成栅极间隔。然后，如图8A至图8C所示，在栅极间隔中，形成包括金属栅电极70和诸如高k介电层的栅介电层(未示出)的金属栅极结构。图8A示出了形成金属栅极图案之后的平面(顶视)图，图8B示出了沿着图8A的线X1-X1的截面图，以及图8C示出了沿着图8A的线X2-X2的截面图。在图8A中，省略了绝缘层60。
金属栅极70包括一个或多个金属材料层，诸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi、CoSi、其他导电材料。金属栅极70可通过CVD、化学汽相沉积(PVD)、ALD或电镀制成。栅极介电层(未示出)包括一个或多个金属氧化物(诸如高k金属氧化物)层。用于高k介电质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物和/或它们的混合物。可以通过CVD、PVD或ALD制成栅极介电层。在一些实施例中，一个或多个功函调节层(未示出)介于栅极介电层与金属栅极70之间。功函调节层由导电材料(诸如，TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或者这些材料的两种或多种的多层)制成。对于n型FET，TaN、TiAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种用作功函调节层，而对于p型FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co中的一种或多种用作功函调节层。
然后，如图9A至图9C所示，使金属栅电极70凹进并且形成覆盖绝缘层80。图9A示出了在形成金属栅极图案之后的平面(顶视)图，图9B示出了沿着图9A的线X1-X1的截面图，以及图9C示出了沿着图9A的线X2-X2的截面图。在图9A中，省略了绝缘层60。覆盖绝缘层80包括一层或多层绝缘材料，例如，SiO2、SiN、SiON、SiCN和SiOCN。在本实施例中，SiN或氮化硅基材料用作覆盖绝缘层80。通过CVD和执行平坦化操作(例如，CMP)沉积绝缘材料的毯式层来形成覆盖绝缘层80。
如图10A至图10C所示，在形成覆盖绝缘层80之后，在绝缘层60中形成开口65。图10A示出了在形成金属栅极图案之后的平面(顶视)图，图10B示出了沿着图10A的线X1-X1的截面图，以及图10C示出了沿着图10A的线X2-X2的截面图。在图10A中，省略了绝缘层60，并且由虚线示出了开口65的***。
通过图案化绝缘层60，源/漏极区50P和50N的至少一部分的表面和隔离区域的一部分的表面在开口65中露出。
在本实施例中，侧壁间隔件45和覆盖绝缘层80由氮化硅基材料(例如，SiN)制成，而绝缘层60由氧化硅基的材料(例如，SiO2)制成。因此，在绝缘层60的氧化蚀刻期间，源/漏极区50N、50P以自对准的方式露出而没有破坏金属栅电极70。在绝缘层60的氧化蚀刻期间，可以蚀刻隔离绝缘区15的上表面。
如图11A至图11D所示，在开口65中，填充导电材料以形成局部互连件90。图11A示出了在形成金属栅极图案之后的平面(顶视)图，图11B示出了沿着图11A的线X1-X1的截面图，图11C示出了沿着图11A的线X2-X2的截面图，以及图11D示出了沿着图11A的线Y1-Y1的截面图。在图11A中，省略了绝缘层60。
在图10A至图10C的结构上方形成一个或多个金属材料(诸如，钨、钛、钴和镍或它们的硅化物、或其他合适的材料)层，并且执行诸如CMP方法的平坦化操作，从而获得图11A至图11D的结构。通过金属材料填充开口65，从而形成连接源/漏极区50N与源/漏极区50P的局部互连件90。
如图11B至图11D所示，局部互连件90与源/漏极区50N和50P的上表面以及隔离区15的一部分的上表面接触。局部互连件90与侧壁间隔件45接触，并且覆盖绝缘层80的上表面、侧壁间隔件45的上表面(顶部分)和局部互连件90的上表面基本上彼此平齐，即在同一平面上。在本发明中，当各部件的高度之差小于最高部件高度的10％时，则认为这些部件是基本上彼此平齐的。在一个实施例中，局部互连件90相对于源/漏极区的表面处的高度在约60nm至约180nm的范围内。
图11A示出了六个Fin FET，即，TR1、TR2、TR3、TR4、TR5和TR6。局部互连件90连接TR1、TR2、TR3、TR4的源/漏极区。另外，在Fin FETTR3、TR5之间的共用源/漏极区上形成局部金属层95，该局部金属层95与局部互连件90同时制造。这个局部金属层95可以减小对源/漏极区的接触电阻。
图12示出了根据本发明的一个实施例的半导体器件的示例性截面图。
在形成局部互连件90之后，在图11A至图11D的结构上方形成第一层间介电(ILD)层ILD1。然后执行图案化操作以形成通孔口，并且用一种或多种导电材料填充通孔口以形成第一通孔插塞V1。第一金属引线M1也形成在第一通孔插塞V1的上方。通过双镶嵌方法可以形成第一金属引线M1和第一通孔插塞V1。第一通孔插塞V1中的一些连接至局部互连件90。此外，在第一金属布线M1的上方形成第二ILD层ILD2。然后执行图案化操作以形成通孔口，并且用一种或多种导电材料填充通孔口以形成第二通孔插塞V2。第二金属引线M2也形成在第二通孔插塞V2上方。可以通过双镶嵌方法形成第二金属布线M2和第二通孔插塞V2。第一和第二ILD层包括一个或多个绝缘材料层，诸如二氧化硅(SiO2)和SiON的氧化硅基材料。
图13A至图13C示出了根据本发明的各个方面的半导体器件的示意性布局结构。局部互连件的各种布置可能在标准单元内。在一个实施例中，在平面图中，局部互连件与栅电极线性平行地延伸。在其他实施例中，在平面图中，局部互连件具有曲柄形状。
在图11A、图13B和图13C中，栅极图案的各端部彼此相对设置同时中间留有间隔，并且局部互连件穿过该间隔。该间隔可以位于源/漏极区上方，或可以位于隔离区的上方。
本文描述的各个实施例或实例提供若干优于现有技术的优点。例如，在本发明中，由于以自对准方式形成局部互连件(和互连金属层)，所以可以避免由工艺变化(如，光刻操作中的对准误差)导致的短路。另外，加强了设计标准单元的设计灵活性。
应该理解，本文不必讨论所有优点，没有特定优势是所有实施例或实例都必需的，并且其他实施例或实例可提供不同优点。
根据本发明的一个方面，半导体器件包括：具有第一栅极、第一源极和第一漏极的第一晶体管；具有第二栅极、第二源极和第二漏极的第二晶体管；分隔所述第一晶体管和所述第二晶体管的隔离区；以及连接所述第一源极和所述第一漏极的至少一个到所述第二源极和所述第二漏极的至少一个的局部互连件。所述局部互连件与所述第一源极和所述第一漏极的至少一个的表面、所述第二源极和所述第二漏极的至少一个的表面、所述隔离区的一部分的表面接触。
在一些实施例中，所述第一栅极被供有第一侧壁间隔层，所述局部互连件与所述第一侧壁间隔层中的一个接触。
在一些实施例中，所述局部互连件的最上部分与所述第一侧壁间隔层的最上部分位于同一水平面上。
在一些实施例中，所述第一栅极被提供有覆盖绝缘层，以及所述局部互连件的所述最上部分与所述覆盖绝缘层的最上部分位于同一水平面上。
在一些实施例中，所述第一栅极由Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi和CoSi中的一种或多种制成。
在一些实施例中，所述第一晶体管和所述第二晶体管是鳍式场效应晶体管。
在一些实施例中，所述第一晶体管的导电类型与所述第二晶体管的导电类型不同。
在一些实施例中，在平面图中，所述局部互连件与所述第一栅电极和所述第二栅电极中的至少一个线性地平行延伸。
在一些实施例中，在平面图中，所述局部互连件具有曲柄形状。
在一些实施例中，该半导体器件还包括：第三晶体管，具有第三栅极、第三源极和第三漏极，其中，所述局部互连件还与所述第三源极和所述第三漏极中的至少一个的表面接触。根据本发明的另一个方面，半导体器件包括：在第一方向上延伸的源/漏极区；分隔所述源/漏极区的隔离区；在第一方向上延伸的第一栅极图案；在所述第一方向上延伸的第二栅极图案；在所述第一方向上延伸，并且在所述第一方向上与所述第二栅极图案对准的第三栅极图案；以及局部互连件。所述第二栅极图案的一端与所述第三栅极图案的一端之间具有间隔并且相对。所述局部互连件与所述源/漏极区中至少一个的表面和所述隔离区的表面中的至少一个接触。所述局部互连件在第二方向上延伸并且穿过所述间隔，所述第二方向与所述第一方向交叉。
在一些实施例中，所述间隔位于所述源/漏极区的所述至少一个的上方。
在一些实施例中，所述间隔位于所述隔离区的上方。
在一些实施例中，在平面图中，所述局部互连件具有曲柄形状。
在一些实施例中，所述源/漏极区包括第一源/漏极区和第二源/漏极区，所述第一栅极图案，设置在所述第一源/漏极区和第二源/漏极区的上方，所述第二栅极图案，设置在所述第一源/漏极区的上方，所述第三栅极图案，设置在所述第二源/漏极区的上方，所述局部互连件与所述第一源/漏极区的表面和所述第二源/漏极区的表面接触。
在一些实施例中，所述源/漏极区形成在鳍结构的上方。
根据本发明的又一方面，在制造半导体器件的方法中，在衬底中形成隔离结构。在衬底上方形成第一晶体管结构和第二晶体管结构。第一晶体管结构包括第一栅电极、设置在第一栅电极上方的第一覆盖绝缘层、设置在第一栅电极和第一覆盖绝缘层的侧面上的第一侧壁间隔件、第一源极和第一漏极。第二晶体管结构包括第二栅电极、设置在第二栅电极上方的第二覆盖绝缘层、设置在第二栅电极和第二覆盖绝缘层的侧面上的第二侧壁间隔件、第二源极和第二漏极。在所述第一和第二晶体管结构之间形成第一绝缘层。在所述第一绝缘层中形成开口，以露出所述第一源极和所述第一漏极的至少一个的表面，所述第二源极和所述第二漏极的至少一个的表面，以及所述隔离区的一部分的表面。用导电材料填充所述开口以形成局部互连件。
在一些实施例中，形成所述第一晶体管结构包括：形成有源区；在所述有源区和所述隔离区上方形成伪栅极图案；形成所述第一侧壁间隔件；在所述有源区上方形成所述第一源极和所述第二源极；去除所述伪栅极图案，从而形成栅极间隔；在所述栅极间隔中形成金属材料；以及在所述金属材料上方形成所述第一覆盖绝缘层。
在一些实施例中，形成所述伪栅极图案包括：在所述有源区和所述隔离区上方形成伪层；在所述伪层上方形成硬掩模图案；分割所述硬掩模层图案；以及通过采用分割的所述硬掩模层图案作为蚀刻掩模，图案化所述伪层。
在一些实施例中，用所述导电材料填充所述开口包括平坦化操作，以使所述局部互连件的最上部分与所述第一覆盖绝缘层的最上部分位于同一水平面上。
上面论述了若干实施例的部件，以便本领域技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。的情况下，可以进行多种变化、替换以及改变。

Claims (20)

1.一种半导体器件，包括：
第一晶体管，具有第一栅极、第一源极和第一漏极；
第二晶体管，具有第二栅极、第二源极和第二漏极；
隔离区，由绝缘材料形成，并且分隔所述第一晶体管和所述第二晶体管；以及
局部互连件，将所述第一源极和所述第一漏极中的至少一个连接至所述第二源极和所述第二漏极中的至少一个，并且所述局部互连件沿第一方向以及与所述第一方向交叉的第二方向延伸，其中：
所述局部互连件与所述第一源极和所述第一漏极中的所述至少一个的表面、所述第二源极和所述第二漏极中的所述至少一个的表面、所述隔离区的一部分的表面接触。
2.根据权利要求1所述的半导体器件，其中：
所述第一栅极被提供有第一侧壁间隔层，
所述局部互连件与所述第一侧壁间隔层中的一个接触。
3.根据权利要求2所述的半导体器件，其中，所述局部互连件的最上部分与所述第一侧壁间隔层的最上部分位于同一水平面上。
4.根据权利要求3所述的半导体器件，其中：
所述第一栅极被提供有覆盖绝缘层，以及
所述局部互连件的所述最上部分与所述覆盖绝缘层的最上部分位于同一水平面上。
5.根据权利要求4所述的半导体器件，其中，所述第一栅极由Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi和CoSi中的一种或多种制成。
6.根据权利要求1所述的半导体器件，其中，所述第一晶体管和所述第二晶体管是鳍式场效应晶体管。
7.根据权利要求1所述的半导体器件，其中，所述第一晶体管的导电类型与所述第二晶体管的导电类型不同。
8.根据权利要求1所述的半导体器件，其中，在平面图中，所述局部互连件与所述第一栅极和所述第二栅极中的至少一个线性地平行延伸。
9.根据权利要求1所述的半导体器件，其中，在平面图中，所述局部互连件具有曲柄形状。
10.根据权利要求1所述的半导体器件，还包括：
第三晶体管，具有第三栅极、第三源极和第三漏极，
其中，所述局部互连件还与所述第三源极和所述第三漏极中的至少一个的表面接触。
11.一种半导体器件，包括：
源/漏极区，在第一方向上延伸；
隔离区，分隔所述源/漏极区；
第一栅极图案，在第一方向上延伸；
第二栅极图案，在所述第一方向上延伸；
第三栅极图案，在所述第一方向上延伸，并且在所述第一方向上与所述第二栅极图案对准；以及
局部互连件，其中：
所述第二栅极图案的一端与所述第三栅极图案的一端彼此相对并且之间留有间隔，
所述局部互连件与所述源/漏极区中的至少一个的表面和所述隔离区的表面中的至少一个表面接触，以及
所述局部互连件在第二方向上延伸并且穿过所述间隔，所述第二方向与所述第一方向交叉。
12.根据权利要求11所述的半导体器件，其中：
所述间隔位于所述源/漏极区的所述至少一个的上方。
13.根据权利要求11所述的半导体器件，其中：
所述间隔位于所述隔离区的上方。
14.根据权利要求13所述的半导体器件，其中，在平面图中，所述局部互连件具有曲柄形状。
15.根据权利要求13所述的半导体器件，其中：
所述源/漏极区包括第一源/漏极区和第二源/漏极区，
所述第一栅极图案，设置在所述第一源/漏极区和第二源/漏极区的上方，
所述第二栅极图案，设置在所述第一源/漏极区的上方，
所述第三栅极图案，设置在所述第二源/漏极区的上方，
所述局部互连件与所述第一源/漏极区的表面和所述第二源/漏极区的表面接触。
16.根据权利要求11所述的半导体器件，其中，所述源/漏极区形成在鳍结构的上方。
17.一种制造半导体器件的方法，所述方法包括：
在衬底中形成隔离区；
在所述衬底上方形成第一晶体管结构和第二晶体管结构，所述第一晶体管结构包括第一栅极、设置在所述第一栅极上方的第一覆盖绝缘层、设置在所述第一栅极的侧面上和所述第一覆盖绝缘层的侧面上的第一侧壁间隔件、第一源极和第一漏极，所述第二晶体管结构包括第二栅极、设置在所述第二栅极上方的第二覆盖绝缘层、设置在所述第二栅极的侧面和所述第二覆盖绝缘层的侧面上的第二侧壁间隔件、第二源极和第二漏极；
在所述第一晶体管结构和所述第二晶体管结构之间形成第一绝缘层；
在所述第一绝缘层中形成开口，以露出所述第一源极和所述第一漏极中的至少一个的表面，所述第二源极和所述第二漏极中的至少一个的表面，以及所述隔离区的一部分的表面；
用导电材料填充所述开口以形成局部互连件，所述局部互连件沿第一方向以及与所述第一方向交叉的第二方向延伸。
18.根据权利要求17所述方法，其中，形成所述第一晶体管结构包括：
形成有源区；
在所述有源区和所述隔离区上方形成伪栅极图案；
形成所述第一侧壁间隔件；
在所述有源区上方形成所述第一源极和所述第二源极；
去除所述伪栅极图案，从而形成栅极间隔；
在所述栅极间隔中形成金属材料；以及
在所述金属材料上方形成所述第一覆盖绝缘层。
19.根据权利要求18所述方法，其中，形成所述伪栅极图案包括：
在所述有源区和所述隔离区上方形成伪层；
在所述伪层上方形成硬掩模图案；
分割所述硬掩模图案；以及
通过采用分割的所述硬掩模图案作为蚀刻掩模，图案化所述伪层。
20.根据权利要求19所述方法，其中，用所述导电材料填充所述开口包括平坦化操作，以使所述局部互连件的最上部分与所述第一覆盖绝缘层的最上部分位于同一水平面上。
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