CN107017249A - It is a kind of to improve the method for ESD protective device uniform conducting - Google Patents
It is a kind of to improve the method for ESD protective device uniform conducting Download PDFInfo
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- CN107017249A CN107017249A CN201710202712.5A CN201710202712A CN107017249A CN 107017249 A CN107017249 A CN 107017249A CN 201710202712 A CN201710202712 A CN 201710202712A CN 107017249 A CN107017249 A CN 107017249A
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- esd protective
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- 230000001681 protective effect Effects 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000003071 parasitic effect Effects 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
Improve the method for ESD protective device uniform conducting the invention discloses a kind of; the improved properties of ESD protection device suitable for integrated circuit; wherein described ESD protective device includes the multiple NMOS tubes being arranged in parallel; the drain electrode of the multiple NMOS tube is connected to I/O ports or power port by metal connecting line, and grid, source electrode and the substrate of multiple NMOS tubes are connected to ground potential jointly.It is characterized in that：In described ESD protective device, the grid of NMOS tube eliminates Silicide (metal silicide).When there is positive esd pulse in I/O ports or power port; parasitic gate resistance and gate-drain parasitic capacitances, are coupled to a high potential by grid voltage, reduce the trigger voltage of ESD protective device; so that the multiple metal-oxide-semiconductors being arranged in parallel simultaneously turn on electric discharge, ESD protective capabilities are improved.
Description
Technical field
Uniformly led the present invention relates to a kind of design method of ESD protective device, more particularly to a kind of ESD protective device that improves
Logical method, it is adaptable to IC design.
Background technology
With semiconductor technology be made it is increasingly advanced, in technique processing, transport, test, the ESD occurred in application process
Problem is increasingly taken seriously, in ESD protective device design, typically using resistance, diode, triode, metal-oxide-semiconductor and controllable
Silicone tube etc., metal-oxide-semiconductor is most widely used in these ESD protective devices.
ESD protective device based on metal-oxide-semiconductor is all to refer to MOS designs mostly more, by the multiple metal-oxide-semiconductor units of identical and townhouse
Row are constituted, circuit theory diagrams as shown in figure 1, domain schematic diagram so that four NMOS tubes are in parallel as an example as shown in Fig. 2 illustrate here,
But it is not limited to four NMOS tubes to be arranged in parallel, can is 6,8,10 ..., but can not is that odd number NMOS tube is in parallel
Arrangement.As shown in figure 1, the grid of NMOS tube, source electrode and Substrate ground, drain electrode connect I/O ports or power port.As shown in Fig. 2
Peripheral annular is substrate contact (1), and black bars are contact hole (2), four NMOS parallel connections altogether, and their grid is respectively
3a, 3b, 3c, 3d.The drain electrode of the drain electrode NMOS tube corresponding with 3b of the corresponding NMOS tubes of 3a shares (4a), 3c correspondences NMOS leakage
The drain electrode of pole NMOS tube corresponding with 3d shares (4b), and the source electrode of the corresponding NMOS tubes of 3b and the source electrode of the corresponding NMOS tubes of 3c are shared
(5b), this four NMOS drain electrode is connected to I/O ports or power port by metal (6), this four NMOS grid, source electrode
It is connected to ground by metal.
It is its sectional view as shown in Figure 3,5a and 4a form parasitic transistor T1 emitter and collector respectively, T1's
Base stage is connected to substrate contact by R1 (substrate parasitics resistance), and 5b and 4a form parasitic transistor T2 emitter stage and current collection respectively
Pole, T2 base stage is connected to substrate contact by R2 (substrate parasitics resistance), and 5b and 4b form parasitic transistor T3 transmitting respectively
Pole and colelctor electrode, T3 base stage are connected to substrate contact by R3 (substrate parasitics resistance), and 5c and 4b form parasitic transistor respectively
T4 emitter and collector, T4 base stage is connected to substrate contact by R4 (substrate parasitics resistance), the grid of this four NMOS tubes
Pole, drain electrode, source electrode and substrate contact are all covered by silicide (7).
When there is positive esd pulse in I/O ports or power port, drain electrode and substrate parasitics diode avalanche puncture, and produce
Electron hole, hole flows to substrate, forms substrate current, and T1~T4 emitter and collector all, flows to the electricity of substrate
All, so T1~T4 unlatching is mainly influenceed by resistance substrate, T2 and T3 connect stream closer to centre away from substrate
Touch, resistance substrate is bigger, and this causes T2 and T3 first to open, opened after T1 and T4, with the increase of ESD electric currents be likely to occur T2 and
T3 has been burnt out, the phenomenon that T1 and T4 are not turned on, and the uneven phenomenon of this unlatching causes ESD protective device ability to decline.
Even if very big metal-oxide-semiconductor, if the problem of not improving conducting homogeneity, its ESD protection capability there will not be institute
Improve.Improving the method for finger-like MOS uniform conductings has a lot, such as reduces the trigger voltage of ESD protective device, or improve ESD
Failure voltage of protection device etc..
The content of the invention
The primary and foremost purpose of the present invention, is to provide a kind of method of improvement ESD protective device uniform conducting, to increase it
ESD protective capabilities.
Invention one of be：The multiple NMOS tubes being arranged in parallel, the grid of the NMOS tube, source electrode and Substrate ground, drain electrode
I/O ports or power port are connect, the grid of described NMOS tube is covered by silicide barrier layers, without silicide so that
The increase of parasitic gate resistance, there is parasitic capacitance in grid and drain electrode.
When there is positive esd pulse in I/O ports or power port, dead resistance and parasitic capacitance so that grid voltage
It is coupled to high potential so that NMOS tube is turned on, adds drain electrode to the substrate current of p-well, reduce the triggering electricity of parasitic NPN
Pressure so that electric discharge can be simultaneously turned on more by referring to NMOS tube.
The two of invention are：The multiple PMOSs being arranged in parallel, the grid of the PMOS, source electrode and substrate connect I/O ports
Or power port, grounded drain, the grid of described PMOS is covered by silicide barrier layers, without silicide so that
The increase of parasitic gate resistance, there is parasitic capacitance in grid and drain electrode.
When there is positive esd pulse in I/O ports or power port, dead resistance and parasitic capacitance so that grid voltage
It is coupled to low potential so that PMOS is turned on, adds drain electrode to the substrate current of N traps, reduce parasitic PNP triggering electricity
Pressure so that electric discharge can be simultaneously turned on more by referring to PMOS.
Compared with prior art, the present invention has the following advantages：
The grid for the multiple metal-oxide-semiconductors being arranged in parallel is covered by silicide barrier layers, without silicide, is formed very big
Parasitic gate resistance, and using the grid and drain parasitic capacitance of metal-oxide-semiconductor, parasitic ESD auxiliary triggering circuits are constituted, for
NMOS tube constitutes high-pass filter, and low pass filter is constituted for PMOS.When there is positive esd pulse, dead resistance and
Parasitic capacitance so that grid voltage is coupled to a non zero potential, and then causes metal-oxide-semiconductor conducting, reduces parasitic transistor
Trigger voltage so that the conducting homogeneity of ESD protective device improves, and ESD protection capability is improved.
Brief description of the drawings
Below in conjunction with the accompanying drawings, the present invention will be described in detail
The existing ESD protective device schematic diagrams based on NMOS tube of Fig. 1；
The existing ESD protective device domain schematic diagrames based on NMOS tube of Fig. 2；
The existing ESD protective device domain cross-sectional views based on NMOS tube of Fig. 3；
ESD protective device voltage-to-current test charts of the Fig. 4 based on NMOS tube；
The ESD protective device schematic diagram based on NMOS tube of Fig. 5 this patents description；
The ESD protective device domain schematic diagram based on NMOS tube of Fig. 6 this patents description；
The ESD protective device domain sectional view based on NMOS tube of Fig. 7 this patents description；
The ESD protective device schematic diagram based on PMOS of Fig. 8 this patents description；
Embodiment
It is readily understood to enable above-mentioned purpose, feature and advantage of the invention to become apparent from, hereafter especially exemplified by preferred embodiment, and
Coordinate appended diagram, be described below in detail：
ESD protective device voltage-to-current test chart based on NMOS tube is as shown in figure 4, black curve is based on to be existing
The voltage-to-current test curve of the ESD protective device of NMOS tube, when there is positive esd pulse in I/O ports or power port,
Before Vt1, ESD protective device is not turned on, only small electric leakage, with the increase of ESD energy, NMOS drain electrode and lining
Avalanche breakdown occurs for bottom parasitism PN junction, produces electron hole, hole flows to substrate, parasitic brilliant due to there is substrate parasitics resistance
Body pipe is triggered, and trigger voltage is Vt1, and the voltage then occurred in negative resistance phenomenon, ESD protective device drops to Vh, with ESD
The continuation increase of energy, ESD protective device starts ESD charge of releasing, until (Vt2, It2), if Vt2 is equal to Vt1, or Vt2
Less than Vt1, with regard to conducting homogeneity problem occurs.
Red curve in the method that the present embodiment is provided so that Vt1 is reduced to Vt1 ', such as Fig. 1 so that be arranged in parallel
Multiple NMOS can be turned on.It is the ESD protective device schematic diagram based on NMOS tube of this patent description, wherein Cgd as shown in Figure 5
For grid and drain parasitic capacitance, Rg is parasitic gate resistance.It is the ESD based on NMOS tube of this patent description as shown in Figure 6
Protection device domain schematic diagram, is illustrated by taking four NMOS as an example, and this four NMOS grid is 3a, 3b, 3c, 3d respectively.
3a correspondences NMOS drain electrode NMOS corresponding with 3b drain electrode shares (4a), 3c correspondences NMOS drain electrode NMOS corresponding with 3d drain electrode
Share (4b), 3b correspondences NMOS source electrode NMOS corresponding with 3c source electrode shares (5b), and this four NMOS drain electrode passes through metal
(6) I/O ports or power port are connected to, it is important to which this four NMOS grid is covered by silicide barrier layers (8), is not had
silicide。
It is the ESD protective device domain sectional view based on NMOS tube of this patent description, 5a and 4a difference shapes as shown in Figure 7
Into parasitic transistor T1 emitter and collector, T1 base stage is connected to substrate contact by R1 (substrate parasitics resistance), 5b and
4a forms parasitic transistor T2 emitter and collector respectively, and T2 base stage is connected to substrate by R2 (substrate parasitics resistance) and connect
Touch, 5b and 4b form parasitic transistor T3 emitter and collector respectively, T3 base stage is connect by R3 (substrate parasitics resistance)
To substrate contact, 5c and 4b form parasitic transistor T4 emitter and collector respectively, and T4 base stage passes through R4 (substrate parasitics
Resistance) it is connected to substrate contact.Key is that the drain electrode and source electrode portion region not covered by silicide barrier layers (8) have
silicide(7)。
Because silicide square resistance very little, in the case that grid does not have silicide, the parasitism on grid
Resistance is very big, Rg as shown in Figure 5, and because grid and drain electrode have parasitic capacitance Cgd, the filter circuit constituted as Rg and Cgd
Time constant be more than 10ns after, auxiliary triggering parasitic NPN can be played a part of, time constant is bigger, the effect of auxiliary triggering
Fruit is more obvious, when positive esd pulse occur in I/O ports or power port, Cgd and Rg composition high-pass filters so that grid
Coupling obtains high potential so that NMOS is turned on, it is not necessary to which when draining, the avalanche breakdown voltage with substrate PN junction is just triggered, therefore drop
The low trigger voltage of ESD protective device, improves ESD protective device uniform conducting, improves ESD protection capability, and
Extra area is not taken.
The schematic diagram of ESD protective device based on PMOS is as shown in figure 8, because improve the ESD protective device based on PMOS
The method of conducting homogeneity is similar with the method for improving the ESD protective device conducting homogeneity based on NMOS, is all used without
Silicide parasitic gate resistance Rg and gate-drain parasitic capacitances Cgd so that MOS is turned on, auxiliary triggering parasitic transistor, reduction
Trigger voltage, is repeated no more.
Note, any term used in this document should not be considered as limiting the scope of the invention.The skill of this area
Art personnel will be understood that the present invention is not limited to the above embodiments, and does not depart from this hair being defined by the appended claims
Bright scope, can make many modifications and increase.
Claims (2)
1. a kind of improve the method for ESD protective device uniform conducting, it is characterised in that the ESD protective device is in p-well
The multiple NMOS tubes being arranged in parallel, the multiple NMOS drain electrode is connected to I/O ports or power port, grid, source electrode and substrate
Ground potential is connected to jointly, and in described ESD protective device, the grid of NMOS tube is covered by silicide barrier layers, is not had
, there is dead resistance in silicide；
When there is positive esd pulse in I/O ports or power port, parasitic gate resistance and gate-drain parasitic capacitances, by grid voltage
It is coupled to a high potential so that NMOS tube is turned on, adds drain electrode to the substrate current of p-well, reduce the triggering of parasitic NPN
Voltage so that the multiple NMOS tubes being arranged in parallel can simultaneously turn on electric discharge；
When there is negative esd pulse in I/O ports or power port, NMOS drain electrodes and p-well parasitic diode are opened, and are played protection and are made
With.
2. a kind of improve the method for ESD protective device uniform conducting, it is characterised in that the ESD protective device is in N traps
The multiple PMOSs being arranged in parallel, the multiple PMOS drain electrode is connected to ground potential, and grid, source electrode and substrate are connected to I/O jointly
Port or power port, in described ESD protective device, the grid of PMOS is covered by silicide barrier layers, is not had
, there is dead resistance in silicide；
When there is positive esd pulse in I/O ports or power port, parasitic gate resistance and gate-drain parasitic capacitances, by grid voltage
It is coupled to current potential one lower than I/O port or power port so that PMOS is turned on, adds drain electrode to the substrate of N traps
Electric current, reduces parasitic PNP trigger voltage so that the multiple PMOSs being arranged in parallel can simultaneously turn on electric discharge；
When there is negative esd pulse in I/O ports or power port, the drain electrode of PMOS and N traps parasitic diode are opened, and play guarantor
Shield is acted on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710202712.5A CN107017249A (en) | 2017-03-30 | 2017-03-30 | It is a kind of to improve the method for ESD protective device uniform conducting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710202712.5A CN107017249A (en) | 2017-03-30 | 2017-03-30 | It is a kind of to improve the method for ESD protective device uniform conducting |
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| CN201710202712.5A Pending CN107017249A (en) | 2017-03-30 | 2017-03-30 | It is a kind of to improve the method for ESD protective device uniform conducting |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109411467A (en) * | 2018-08-28 | 2019-03-01 | 北京中电华大电子设计有限责任公司 | A method of reducing ESD protective device trigger voltage |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121092A (en) * | 1999-02-02 | 2000-09-19 | Macronix International Co., Ltd. | Silicide blocking process to form non-silicided regions on MOS devices |
| US20080211028A1 (en) * | 2007-02-20 | 2008-09-04 | Fujitsu Limited | Electro-static discharge protection device, semiconductor device, and method for manufacturing electro-static discharge protection device |
| CN101452851A (en) * | 2007-12-06 | 2009-06-10 | 上海华虹Nec电子有限公司 | Manufacturing method for ESD gate grounding NMOS transistor |
| CN101640199A (en) * | 2009-08-25 | 2010-02-03 | 上海宏力半导体制造有限公司 | Electrostatic discharge prevention transistor and manufacture method thereof |
| CN102025135A (en) * | 2009-09-17 | 2011-04-20 | 上海宏力半导体制造有限公司 | ESD protective device |
| CN102543884A (en) * | 2010-12-17 | 2012-07-04 | 无锡华润上华半导体有限公司 | Method for manufacturing one time programmable (OTP) device |
| CN102655149A (en) * | 2012-05-07 | 2012-09-05 | 中国航天科技集团公司第九研究院第七七一研究所 | PD SOI (partially-depleted silicon on insulator) technology-based body grid coupling ESD (electro-static discharge) protection structure |
| CN103021954A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Polycrystalline silicon resistance structure and method for manufacturing corresponding semiconductor integrated device |
| CN103178058A (en) * | 2013-03-29 | 2013-06-26 | 中国航天科技集团公司第九研究院第七七一研究所 | Diode-assisting triggering ESD (Electro-Static Discharge) protection circuit based on PD (Potential Difference) SOI (Silicon On Insulator) |
| US20130264645A1 (en) * | 2006-08-24 | 2013-10-10 | Infineon Technologies Ag | Diode Biased ESD Protection Device and Method |
-
2017
- 2017-03-30 CN CN201710202712.5A patent/CN107017249A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121092A (en) * | 1999-02-02 | 2000-09-19 | Macronix International Co., Ltd. | Silicide blocking process to form non-silicided regions on MOS devices |
| US20130264645A1 (en) * | 2006-08-24 | 2013-10-10 | Infineon Technologies Ag | Diode Biased ESD Protection Device and Method |
| US20080211028A1 (en) * | 2007-02-20 | 2008-09-04 | Fujitsu Limited | Electro-static discharge protection device, semiconductor device, and method for manufacturing electro-static discharge protection device |
| CN101452851A (en) * | 2007-12-06 | 2009-06-10 | 上海华虹Nec电子有限公司 | Manufacturing method for ESD gate grounding NMOS transistor |
| CN101640199A (en) * | 2009-08-25 | 2010-02-03 | 上海宏力半导体制造有限公司 | Electrostatic discharge prevention transistor and manufacture method thereof |
| CN102025135A (en) * | 2009-09-17 | 2011-04-20 | 上海宏力半导体制造有限公司 | ESD protective device |
| CN102543884A (en) * | 2010-12-17 | 2012-07-04 | 无锡华润上华半导体有限公司 | Method for manufacturing one time programmable (OTP) device |
| CN102655149A (en) * | 2012-05-07 | 2012-09-05 | 中国航天科技集团公司第九研究院第七七一研究所 | PD SOI (partially-depleted silicon on insulator) technology-based body grid coupling ESD (electro-static discharge) protection structure |
| CN103021954A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Polycrystalline silicon resistance structure and method for manufacturing corresponding semiconductor integrated device |
| CN103178058A (en) * | 2013-03-29 | 2013-06-26 | 中国航天科技集团公司第九研究院第七七一研究所 | Diode-assisting triggering ESD (Electro-Static Discharge) protection circuit based on PD (Potential Difference) SOI (Silicon On Insulator) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109411467A (en) * | 2018-08-28 | 2019-03-01 | 北京中电华大电子设计有限责任公司 | A method of reducing ESD protective device trigger voltage |
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