CN107003904A - A kind of EMS memory management process, equipment and system - Google Patents
A kind of EMS memory management process, equipment and system Download PDFInfo
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- CN107003904A CN107003904A CN201580001237.4A CN201580001237A CN107003904A CN 107003904 A CN107003904 A CN 107003904A CN 201580001237 A CN201580001237 A CN 201580001237A CN 107003904 A CN107003904 A CN 107003904A
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Abstract
The embodiments of the invention provide a kind of EMS memory management process, equipment and system, the function of global administration's memory source is realized, allows the scope in registers memory region across memory node, the efficiency that internal memory is utilized is improved, and make memory management more flexibly and efficient.This method includes：Internal memory registration request is received, wherein carrying the size in the registers memory region to be applied；It is defined as the M memory node that the registers memory region provides physical memory, and the physical memory size that each memory node is provided；Into the M memory node, each memory node sends internal memory solicitation message；Receive the internal memory application response message of each memory node in the M memory node；Internal memory registration reply message is sent, the internal memory registration reply message carries the information in the registers memory region of distribution.
Description
The present embodiments relate to computer realm, more particularly to a kind of EMS memory management process, equipment and system.
With the fast development of computer networking technology, the performance of network has reached 100 gigabit rank per second at present, and the characteristic for how making full use of express network is the major issue that we face.Remote direct data accesses (Remote Direct Memory Access, abbreviation RDMA) it is to be produced to solve the delay of data processing in network transmission, RDMA allows a computing device directly to transmit information in the internal memory of another computing device, eliminates external memory storage and replicates and text exchange operation.This technology reduces time delay by reducing processor expense and reducing the copy of internal memory, improves network utilization.
RDMA solves the existing data in units of computing device and quickly interacted, increasingly it is taken seriously however as the demand for improving resource utilization, the memory source of computing device is separated from each other with computing device, form memory source pond, the data interaction of RDMA modes is also amplified to computing device with separating the data interaction memory source from the data interaction of computing device/computing device pattern, and the change thus brought brings new demand to RDMA.I.e. after the memory source of computing device is separated with computing device, when computing device is to internal memory resource registering region of memory, the memory management to memory source how is realized.
The content of the invention
In view of this, the embodiments of the invention provide a kind of remote direct data access memory management method, equipment and system, in the case where computing device is separated with memory source, the function of memory source global administration is realized.
In a first aspect, the embodiments of the invention provide a kind of EMS memory management process, Memory Controller Hub is provided out unified memory source interface, including：
Memory Controller Hub carries the size in registers memory region by the unified memory source interface internal memory registration request in the internal memory registration request；
The Memory Controller Hub is defined as the registers memory region from the multiple memory node and provides thing
M memory node of internal memory is managed, and each memory node is respectively necessary for the physical memory size provided in the M memory node, wherein, M is the natural number more than 0；
The Memory Controller Hub each memory node into the M memory node is sent respectively carries the physical memory size for needing to provide in internal memory solicitation message, each internal memory solicitation message；
The Memory Controller Hub receives the memory information that distribution is carried in the internal memory application response message that each memory node is sent respectively in the M memory node, each internal memory application response message；
The Memory Controller Hub generates the information in registers memory region according to the application response message of the M memory node, and internal memory registration reply message is sent by the unified memory source interface, the internal memory registration reply message carries the information in the registers memory region.
With reference in a first aspect, in the first possible implementation, the Memory Controller Hub safeguards the free memory size of each node in the multiple memory node；
The Memory Controller Hub is defined as the M memory node that the registers memory region provides physical memory from the multiple memory node, and the physical memory size that each memory node is respectively necessary for providing in the M memory node includes：The Memory Controller Hub is according to the free memory size and registers memory area size of each node in the multiple memory node of self maintained, determine that each memory node needs the physical memory size provided in the M memory node, and the M memory node.
With reference to the possible implementation of any one of first aspect or more, in second of possible implementation, the physical address information of internal memory of the memory information comprising distribution for the distribution that the internal memory application response message is carried；
Methods described also includes：The Memory Controller Hub is according to the registers memory area size, for the registers memory region distribute virtual address, and set up the virtual address in the registers memory region and the distribution of the M memory node internal memory physical address information between mapping relations.
With reference to the possible implementation of any one of first aspect or more, in the third possible implementation, the mapping relations between the physical address information of the internal memory of the distribution of virtual address and the M memory node of the internal memory registration reply message package containing the registers memory region.
With reference to the possible implementation of any one of first aspect or more, in the 4th kind of possible implementation, the internal memory registration reply message package contains the Pseudo Address information in the registers memory region.
With reference to the possible implementation of any one of first aspect or more, in the 5th kind of possible implementation, the internal memory application response message is also comprising queue to information, and the queue pair is associated with the internal memory distributed for the internal memory solicitation message；
It is institute that the internal memory registration reply message, which also includes each memory node in the M memory node,
The queue of internal memory association of registers memory region distribution is stated to information.
With reference to the possible implementation of any one of first aspect or more, in the 6th kind of possible implementation, the internal memory registration request also includes capability identification, and the capability identification is used to characterize the action type that the registers memory region allows；
The internal memory solicitation message also includes the capability identification.
With reference to the possible implementation of any one of first aspect or more, in the 7th kind of possible implementation, in addition to：The Memory Controller Hub generates key information, and the key information is sent to the M memory node, after the key confirmation response message of each memory node in receiving the M memory node, the key is sent to the computing device for applying for the registers memory region, the key information is used to characterize the authority for accessing the M memory node.
Second aspect, the embodiments of the invention provide a kind of memory management equipment, is provided out unified memory source interface, including：Processor, memory, bus and communication interface；
The memory is used to store computer executed instructions, the processor is connected with the memory by the bus, when the computing device is run, the computer executed instructions of memory storage described in the computing device, so that the method that the memory management equipment performs first aspect or any possible implementation of first aspect.
The third aspect, the embodiments of the invention provide a kind of memory management equipment, is provided out unified memory source interface, is provided out unified memory source interface, including：
Receiving unit, for by the unified memory source interface internal memory registration request, the size in registers memory region to be carried in the internal memory registration request；
Processing unit, M memory node of physical memory is provided for being defined as the registers memory region from the multiple memory node, and each memory node is respectively necessary for the physical memory size provided in the M memory node, wherein, M is the natural number more than 0；
Transmitting element, for into the M memory node each memory node send respectively carried in internal memory solicitation message, each internal memory solicitation message it is described need provide physical memory size；
The receiving unit is additionally operable to receive the memory information for carrying distribution in the internal memory application response message that each memory node is sent respectively in the M memory node, each internal memory application response message；
The transmitting element is additionally operable to generate the information in registers memory region according to the application response message of the M memory node, and internal memory registration reply message is sent by the unified memory source interface, the internal memory registration reply message carries the information in the registers memory region.
With reference to the third aspect, in the first possible implementation, the processing unit is additionally operable to safeguard
The free memory size of each node in the multiple memory node；
The processing unit is used to be defined as the M memory node that the registers memory region provides physical memory from the multiple memory node, and the physical memory size that each memory node is respectively necessary for providing in the M memory node includes：The processing unit is according to the free memory size and registers memory area size of each node in the multiple memory node of self maintained, determine that each memory node needs the physical memory size provided in the M memory node, and the M memory node.
With reference to the possible implementation of any one of third aspect or more, in second of possible implementation, the physical address information of internal memory of the memory information comprising distribution for the distribution that the internal memory application response message is carried；
The processing unit is additionally operable to：Be registers memory region distribution virtual address according to the registers memory area size, and set up the virtual address in the registers memory region and the distribution of the M memory node internal memory physical address information between mapping relations.
With reference to the possible implementation of any one of third aspect or more, in the third possible implementation, the mapping relations between the physical address information of the internal memory of the distribution of virtual address and the M memory node of the internal memory registration reply message package containing the registers memory region.
With reference to the possible implementation of any one of third aspect or more, in the 4th kind of possible implementation, the internal memory registration reply message package contains the Pseudo Address information in the registers memory region.
With reference to the possible implementation of any one of third aspect or more, in the 5th kind of possible implementation, the internal memory application response message is also comprising queue to information, and the queue pair is associated with the internal memory distributed for the internal memory solicitation message；
The internal memory registration reply message also includes the queue for the internal memory association that each memory node in the M memory node is registers memory region distribution to information.
With reference to the possible implementation of any one of third aspect or more, in the 6th kind of possible implementation, the internal memory registration request also includes capability identification, and the capability identification is used to characterize the action type that the registers memory region allows；
The internal memory solicitation message also includes the capability identification.
With reference to the possible implementation of any one of third aspect or more, in the 7th kind of possible implementation, the processing unit is additionally operable to：Generate key information, and the key information is sent to the M memory node, after the key confirmation response message of each memory node in receiving the M memory node, the key is sent to the computing device for applying for the registers memory region, the key information is used to characterize the authority for accessing the M memory node.
Fourth aspect, the embodiments of the invention provide a kind of internal storage management system, memory management equipment is provided out unified memory source interface, comprising：Calculate node, multiple memory nodes and and the third aspect or any described memory management equipment that may cause in implementation of the third aspect,
The calculate node is used to send internal memory registration request to the memory management equipment by the unified memory source interface, the size in registers memory region is carried in the internal memory registration request, and by internal memory registration reply message of the unified memory source interface from the memory management equipment, the internal memory registration reply message carries the information in the registers memory region.
The multiple memory node is used for the internal memory solicitation message for receiving the memory management equipment, is registers memory region storage allocation according to the internal memory solicitation message, and send internal memory application response message to the memory management equipment.
The technical scheme provided according to the present invention, after the computing resource of computing device is decoupled with memory source, memory source is supplied to computing resource to use in the form of internal memory resource pool, one memory source pond includes multiple memory nodes, the unified management to multiple memory nodes in internal memory resource pool can be realized, realize the function of global administration's RDMA memory sources, allow the scope in registers memory region across memory node, the efficiency that internal memory is utilized is improved, and makes memory management more flexibly and efficient.
Technical scheme in order to illustrate the embodiments of the present invention more clearly, the accompanying drawing used required in being described below to embodiment is briefly described, apparently, drawings in the following description are only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is exemplary networking environment block diagram of each computing device via RDMA shared datas；
Fig. 2 is the schematic diagram of the exemplary computer device of the present invention；
Fig. 3 is a kind of application scenarios schematic diagram of RDMA EMS memory management process；
Fig. 4 is a kind of signaling diagram of RDMA EMS memory management process；
Fig. 5 is the application scenarios schematic diagram of the EMS memory management process according to one embodiment of the invention；
Fig. 6 is the EMS memory management process signaling diagram according to one embodiment of the invention；
Fig. 7 is the exemplary flow chart of the EMS memory management process according to one embodiment of the invention；
Fig. 8 is the logical construction schematic diagram of the memory management equipment according to one embodiment of the invention；
Fig. 9 is the computing device hardware architecture diagram according to one embodiment of the invention.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made belongs to the scope of protection of the invention.
Fig. 1 shows RDMA networked environments 100, and wherein network 102 is connected to four computing devices 104.Computing device 104 is connected using their network 102 to be transmitted to perform mutual RDMA.Network 102 can be internet, Intranet, LAN (LANs), Wide Area Network (WLANs), storage area network (SANs) etc., or above network combination.
Fig. 1 is only intended to introduce RDMA participant and their correlation for following discussion purpose.Therefore, the RDMA environment 100 described is greatly simplified.Because RDMA some aspects are well known in the present art, therefore these aspects, certificate scheme and safety etc. are not discussed herein.Involved complexity is all known for the people worked in the art in setting and running successful RDMA environment 100.
Fig. 1 computing device 104 can be any architecture.Fig. 2 be vague generalization show support the embodiment of the present invention exemplary computer system block diagram.Fig. 2 computer system is only an example, is not intended to use scope or function to the embodiment of the present invention and proposes any limit.Also computing device 104 should not be construed to with any one in the component shown in Fig. 2 or its combine relevant any dependence or requirement.The embodiment of the present invention can work together with many other universal or special computing environment or configuration.Suitable for including but is not limited to the known computing system that the embodiment of the present invention is used together, environment and the example of configuration, personal computer, server, hand-held or laptop devices, multicomputer system, the system based on microprocessor, set top box, programmable-consumer electronics, network PC, microcomputer, mainframe computer and the DCE including any system above or equipment.In its most basic configuration, computing device 104 generally includes at least one processor 200 and memory 202.Memory 202 can be used by computing device 104 as memory source, can be volatibility (such as RAM), non-volatile (such as ROM or flash memory) or certain combination of both.This most basic configuration is illustrated by dotted line 204 in fig. 2.Computing device 104 can have additional feature and function.For example, it can include the storage (moveable and immovable) of peripheral hardware, it includes but is not limited to, Disk and tape and CD and light belt.It is such outer
If storage is illustrated by removable Storage 206 and irremovable storage 208 in fig. 2.Computer-readable storage medium includes volatibility and non-volatile, moveable and immovable, and that is realized in what method or technique in office is used for storing the medium of the information such as computer-readable instruction, data structure, program module or other data.Memory 202, removable Storage 206 and irremovable storage 208 are all the examples of computer-readable storage medium.Computer-readable storage medium includes, but it is not limited to, RAM, ROM, EEPROM, flash memory, other memory technologies, CD-ROM, digital universal disc, other optical storages, magnetic card band, tape, disk storage, other magnetic storage apparatus, and any other can be for storage information needed and the medium that can be accessed by computing device 104.Any such computer-readable storage medium can be a part for computing device 104.Computing device 104 can also be included in the equipment on network 102, the communication channel 210 of communication comprising itself and other equipment is allowed.Communication channel 210 is the example of communication media.Communication media generally includes computer-readable instruction, data structure, program module or other data in the modulated message signal or other transmission mechanisms of carrier wave etc., and including any information transmitting medium.Non-limiting as example, communication media includes the wireless medium of wire medium, sound, RF, infrared ray and other wireless mediums of optical medium, cable network and straight line connection etc. etc..Term " computer-readable medium " as used herein includes both storage medium and communication media.Computing device 104 can also have the input equipment 212 of touch-sensitive display screen, hardware keyboards, mouse, voice-input device etc..Output equipment 214 includes equipment in itself, and such as touch sensitive is explicitly shielded, loudspeaker, printer and the presentation module (often referred to as " adapter ") for driving these equipment.All these equipment are all it is known in the art that therefore need not be discussed in detail herein.Computing device 104 has power supply 216.
Optionally, the computing resource of computing device 104 is separated with memory source, and 104 points of computing device is calculate node and memory source.Memory source includes memory 202 and Memory Controller, and Memory Controller is used for the operation such as data access of control memory 202；Calculate node includes other features and function of computing device 104.Optionally, calculate node also includes the memory source of other in addition to the memory source of separation of computing device 104.It is attached between calculate node and separation memory source by network 102.
Optionally, the computing resource of computing device 104 is decoupled with memory source, i.e. computing resource is separated with memory source, computing resource exists in the form of computing resource pond, memory source exists in the form of internal memory resource pool, computing resource pond includes at least one calculate node, and memory source pond includes at least one memory node.Calculate node includes processor 200 and other calculating and the necessary component of communication,
Memory node is comprising other storages such as memory 202 and accessor control and communicates necessary component.
Fig. 3 is the logical construction schematic diagram that remote direct data accesses RDMA method application scenarios, as shown in Figure 3, the system includes the first computing device and the second computing device, wherein the first computing device and the second computing device are the computing device shown in Fig. 2, the processor and memory of computing device are only shown, other features and function are not shown in Fig. 3 in figure.
When the second memory of the second computing device needs to carry out RDMA operation to the first memory of the first computing device, its signaling diagram is as shown in figure 4, execution step is：
402：Second computing device sends RDMA operation by network 102 to the first computing device and asked.
Optionally, the RDMA operation type that the second computing device is asked to the first computing device, and the memory size that RDMA operation needs are carried in the RDMA operation request.
404：First computing device asks to carry out internal memory application in local memory according to RDMA operation.
Optionally, carry out also generating queue to (Queue Pair, QP) when internal memory application, and bound with registers memory region (Memory Region, MR).MR is the general designation in apllied registers memory region, and MR is presented in the way of virtual address, and it is physical address (page mode or block pattern) in the mapping of application layer.
QP includes transmit queue (Send Queue, SQ) and receiving queue (Receive Queue, RQ).SQ, which is used to send, to be operated, and preserves the instruction for making data be transmitted between the memory device of computing device and the memory device of another computing resource；RQ, which is used to receive, to be operated, and is preserved about the data received from another computing device are placed on into instruction where.Computing device submits work request, and this is the Work Queue Elements (Work Queue Element, WQE) that be placed in appropriate work queue.Channel adapter performs WQE, so that they are placed in work queue.
Optionally, operating system will be checked the operation that registers memory region allows during the visit in internal memory, the internal memory of application has remote key word and local keyword, for controlling the access rights of internal memory, local keyword is used for local RDMA network interface cards (RDMA Network Interface Card, RNIC) hardware interface adapters access local memory, and remote key word is used for long-range RNIC hardware interface adapters and accesses Installed System Memory.
406：The registers memory area message of application is sent to the second computing device by the first computing device.
Optionally, virtual address (Virtual Address, VA) and internal memory key (Remote Key, R_KEY) are included in RDMA registers memories area message.Wherein, virtual address VA represents that first memory is used for the virtual address for receiving the memory cell of RDMA operation, internal memory key R_KEY is used to characterize the authority for accessing first memory, and carries out virtual address to the conversion of first memory physical address for combining actual situation address translation table..
408：Second computing device carries out RDMA operation to the first computing device.
According to the RDMA methods shown in Fig. 4, it is possible to achieve based on the RDMA internal memory applications between the first computing device 104 and the second computing device 104.But the RDMA internal memory applications described in Fig. 4 are point-to-point progress, it is only applicable to the internal memory application when needing to carry out RDMA operation between two computing devices, apllied internal memory is only limitted to inside computing device, the internal memory applied can not be across multiple memory nodes, especially under the framework that the computing resource and memory source of computing device are decoupled, it is impossible to realize the unified management of internal memory.When the computing resource of computing device is separated with memory source, memory source exists in the form of internal memory resource pool, memory source pond includes multiple memory nodes, need to create different MR between point-to-multipoint, same process is caused to need to safeguard multiple MR, and physical memory can not be maximally utilized, and cause node memory to be unable to optimum use.
Fig. 5 is the application scenarios schematic diagram of the EMS memory management process according to one embodiment of the invention, as shown in Figure 5, the computing resource of computing device 104 is separated with memory source, it is divided into calculate node 502 and memory node 506, i.e. the computing resource of computing device and memory source are decoupled, no longer it is to be physically incorporated on a computing device, but calculate node and memory node are provided to computing device in the form of computing resource pond and memory source pond, calculate node 502 is attached with memory node 506 by forms such as network 102, PCIE buses or messaging bus.The memory source of computing device is supplied to calculate node 502 in the form of internal memory resource pool 510, and memory source pond 510 includes N number of memory node, and wherein N is the natural number more than 0.In the framework shown in Fig. 5, calculating and internal memory are no longer the relations of a close coupling, and computing resource and memory source are divided into different nodes, and calculate node 502 can apply for the resource in memory source pond 510, it is not necessary to be confined to again inside some memory node.
Optionally, calculate node 502 is the remainder that computing device 104 removes memory source, the memory source of calculate node 502 is decoupled with calculate node 502, i.e. the memory source of calculate node 502 is separated with calculate node 502, and memory source is provided to calculate node 502 in the form of internal memory resource pool 510.
Optionally, calculate node 502 is computing device 104, its partial memory resource and calculate node
502 decouplings, the i.e. partial memory resource of calculate node 502 is separated with calculate node 502, and calculate node 502 is supplied in the form of internal memory resource pool 510.
Optionally, calculate node 502 is responsible for calculating the node of processing operation for computing device 104, comprising processor 200 and other calculating with communicating necessary component.
Optionally, calculate node 502 is a computing resource pond, and the computing resource pond is comprising multiple processors 200 and other calculating with communicating necessary component.
Wherein, Memory Controller Hub 504 is the management equipment that unified memory management is carried out to the memory node 506 in internal memory resource pool 510.
Optionally, Memory Controller Hub 504 is responsible for the unified management and distribution of N number of memory node 506 inside memory source pond 510.System memory address is divided into virtual address and physical address, client layer it is seen that virtual address, and needs physical address when being handled on memory node 506, and the virtual address of memory node 506 is completed on Memory Controller Hub 504 to the conversion of physical address.
Optionally, the internal memory service condition in whole memory source pond 510 is saved on Memory Controller Hub 504, i.e. Memory Controller Hub 504 knows which internal memory is used on N number of memory node 506, which internal memory is idle, and such Memory Controller Hub 504 can apply for internal memory length reasonable distribution internal memory in memory node according to user.
Optionally, the virtual address that Memory Controller Hub 504 carries out N number of memory node inside unified addressing, memory source pond 510 to N number of memory node inside internal memory resource pool 510 is managed collectively by Memory Controller Hub 504.
Optionally, Memory Controller 508 is deployed on memory node 506, is responsible for the instruction of the access privilege control of memory node 506 and response memory controller 504.
Optionally, internal storage access control of authority table is set on Memory Controller 508, when receiving internal storage access instruction, to arrive first in control of authority table and search, meet and practical operation physics internal memory is just removed after authority.
Memory Controller Hub 504 is provided out unified memory source interface.
Optionally, when calculate node 502 will carry out RDMA internal memory applications in internal memory resource pool 510, its signaling diagram is as shown in fig. 6, its step is：
602：Memory Controller Hub 504 receives the size that registers memory region is carried in the internal memory registration request from calculate node 502, the internal memory registration request by unified memory source interface.
Optionally, the internal memory application request also includes process identification (PID).The registers memory area size that Memory Controller Hub 504 is asked according to process identification (PID) and internal memory registration request distributes virtual address for registers memory region.
Optionally, the internal memory registration request also includes capability identification, and the capability identification is used to characterize the action type that the registers memory region allows.
Optionally, the action type includes following at least one：Local reading, locally-written, long-range reading, remote write, atomic operation or binding.
604：Memory Controller Hub 504 is defined as the M memory node 506 that the registers memory region provides physical memory from the multiple memory node 506, and each memory node 506 is respectively necessary for the physical memory size provided in the M memory node 506, wherein, M is the natural number more than 0.
Optionally, the Memory Controller Hub 504 safeguards the free memory size of each node in the multiple memory node 506；The Memory Controller Hub 504 is defined as the M memory node 506 that the registers memory region provides physical memory from the multiple memory node 506, and the physical memory size that each memory node 506 is respectively necessary for providing in the M memory node 506 includes：The Memory Controller Hub 504 is according to the free memory size and registers memory area size of each node in the multiple memory node 506 of self maintained, determine that each memory node 506 needs the physical memory size provided in the M memory node 506, and the M memory node 506.
Optionally, the physical memory service condition of N number of memory node 506 in memory headroom size and memory source pond 510 that Memory Controller Hub 504 is asked according to internal memory registration request, it is defined as the M memory node 506 that the registers memory region provides physical memory, and the physical memory size that each memory node 506 is provided in the M memory node 506.
606：The each memory node 506 into the M memory node 506 of Memory Controller Hub 504 is sent respectively carries the physical memory size for needing to provide in internal memory solicitation message, each internal memory solicitation message.
Optionally, the internal memory solicitation message also includes capability identification, and the capability identification is used to characterize the action type that the registers memory region allows.The action type includes following at least one：Local reading, locally-written, long-range reading, remote write, atomic operation or binding.
Optionally, internal memory solicitation message also carries process identification (PID), and Memory Controller 508 applies for that memory headroom size distributes physics memory headroom according to the internal memory solicitation message received, and process identification (PID)
It is mapped with the physical memory addresses distributed, recorded memory management authority list.
Optionally, Memory Controller 508 also creates QP on memory node 506, and is bound with the physical memory space of distribution.
608：Memory Controller Hub 504 receives and the memory information that corresponding memory node 506 is distributed is carried in the internal memory application response message that each memory node 506 is sent respectively in the M memory node 506, each internal memory application response message.
Optionally, the internal memory application response message is the physical address information for the internal memory that the internal memory solicitation message is distributed comprising 506.
Optionally, Memory Controller Hub 504 is according to the registers memory area size, for the registers memory region distribute virtual address, and set up the virtual address in the registers memory region and the distribution of the M memory node 506 internal memory physical address information between mapping relations.
Optionally, the internal memory application response message is also comprising queue to information, and the queue is that the internal memory that the internal memory solicitation message is distributed is associated with affiliated memory node 506 to QP.
Optionally, the queue that the internal memory that the Memory Controller Hub 504 sets up the registers memory region with the M memory node 506 is registers memory region distribution is associated is to the mapping relations between QP.
Optionally, Memory Controller Hub 504 also generates queue team QP, and queue team QP is associated with registers memory region.
610：Memory Controller Hub 504 generates the information in registers memory region according to the application response message of the M memory node 506, and internal memory registration reply message is sent to calculate node 502 by the unified memory source interface, the internal memory registration reply message carries the information in the registers memory region.
Optionally, the mapping relations between the physical address information of the internal memory of the distribution of virtual address and the M memory node 506 of the internal memory registration reply message package containing the registers memory region.
Optionally, the internal memory registration reply message package contains the Pseudo Address information in the registers memory region.
Optionally, the internal memory registration reply message also includes the queue for the internal memory association that each memory node 506 in the M memory node 506 is registers memory region distribution to QP information.
Optionally, the internal memory registration reply message is also comprising the queue team QP information associated with the registers memory region.
Optionally, the Memory Controller Hub 504 also generates key information, and the key information is sent to the M memory node 506, after the key confirmation response message of each memory node 506 in receiving the M memory node 506, the key is sent to the computing device for applying for the registers memory region, the key information is used to characterize the authority for accessing the M memory node 506.
The technical scheme according to disclosed in the present embodiment, after the computing resource of computing device is decoupled with memory source, memory source is supplied to computing resource to use in the form of internal memory resource pool, one memory source pond includes multiple memory nodes, the unified management to multiple memory nodes in internal memory resource pool can be realized, the function of global administration's memory source is realized, allows the scope in registers memory region across memory node, the efficiency that internal memory is utilized is improved, and makes memory management more flexibly and efficient.
Fig. 7 is the exemplary flow chart of the EMS memory management process 700 according to one embodiment of the invention.When the computing resource of computing device is separated with memory source, the memory source of computing device is supplied to computing resource in the form of internal memory resource pool, and memory source pond includes N number of memory node, and wherein N is the natural number more than 0.Method 700 realizes the function that computing resource carries out RDMA internal memory registrations in internal memory resource pool, internal memory registration is no longer limited to inside some memory node.The executive agent of method 700 can be the RDMA Memory Controller Hub in memory source pond.Memory Controller Hub is provided out unified memory source interface, as shown in fig. 7, method 700 includes：
S702：Memory Controller Hub carries the size in registers memory region by the unified memory source interface internal memory registration request in the internal memory registration request.
S704：The Memory Controller Hub is defined as the M memory node that the registers memory region provides physical memory from the multiple memory node, and each memory node is respectively necessary for the physical memory size provided in the M memory node, wherein, M is the natural number more than 0.
S706：The Memory Controller Hub each memory node into the M memory node is sent respectively carries the physical memory size for needing to provide in internal memory solicitation message, each internal memory solicitation message.
S708：The Memory Controller Hub receives the memory information that distribution is carried in the internal memory application response message that each memory node is sent respectively in the M memory node, each internal memory application response message.
S710：The Memory Controller Hub generates the information in registers memory region according to the application response message of the M memory node, and is disappeared by the unified memory source interface transmission internal memory registration reply
Breath, the internal memory registration reply message carries the information in the registers memory region..
Optionally, the Memory Controller Hub safeguards the free memory size of each node in the multiple memory node；The Memory Controller Hub is defined as the M memory node that the registers memory region provides physical memory from the multiple memory node, and the physical memory size that each memory node is respectively necessary for providing in the M memory node includes：The Memory Controller Hub is according to the free memory size and registers memory area size of each node in the multiple memory node of self maintained, determine that each memory node needs the physical memory size provided in the M memory node, and the M memory node.
Optionally, the physical address information of internal memory of the memory information for the distribution that the internal memory application response message is carried comprising distribution；Methods described 700 also includes：The Memory Controller Hub is according to the registers memory area size, for the registers memory region distribute virtual address, and set up the virtual address in the registers memory region and the distribution of the M memory node internal memory physical address information between mapping relations.
Optionally, the mapping relations between the physical address information of the internal memory of the distribution of virtual address and the M memory node of the internal memory registration reply message package containing the registers memory region.
Optionally, the internal memory registration reply message package contains the Pseudo Address information in the registers memory region.
Optionally, the internal memory application response message is also comprising queue to information, and the queue pair is associated with the internal memory distributed for the internal memory solicitation message；The internal memory registration reply message also includes the queue for the internal memory association that each memory node in the M memory node is registers memory region distribution to information.
Optionally, the internal memory registration request also includes capability identification, and the capability identification is used to characterize the action type that the registers memory region allows；The internal memory solicitation message also includes the capability identification.
Optionally, the action type includes following at least one：Local reading, locally-written, long-range reading, remote write, atomic operation or binding.
Optionally, method 700 also includes：The Memory Controller Hub generates key information, and the key information is sent to the M memory node, after the key confirmation response message of each memory node in receiving the M memory node, the key is sent to the computing device for applying for the registers memory region, the key information is used to characterize the authority for accessing the M memory node..
Optionally, the Memory Controller Hub is additionally operable to generation queue team QP, and the incidence relation set up between queue team QP and the registers memory region；The internal memory registration reply message is also comprising queue team information.
Optionally, the internal memory application response message also comprising remote memory key (Remote Key,
R_KEY), the remote memory key R_KEY is used to characterizing the authority for accessing the internal memory application response message, and for reference to virtual address determine jointly the memory node be used for receive the physical address of memory cell that operates.It is the corresponding remote memory key R_KEY in the registers memory region that the internal memory registration reply message, which also includes each memory node in the M memory node,.
Optionally, the internal memory application request also includes process identification (PID), and the registers memory area size that the Memory Controller Hub in memory source pond is asked according to process identification (PID) and internal memory registration request distributes virtual address for registers memory region.
Optionally, N number of memory node physical memory service condition in memory headroom size and memory source pond that the Memory Controller Hub in memory source pond is asked according to internal memory registration request, it is defined as the M memory node that the registers memory region provides physical memory, and the physical memory size that each memory node is provided in the M memory node.
The technical scheme according to disclosed in the present embodiment, after the computing resource of computing device is decoupled with memory source, memory source is supplied to computing resource to use in the form of internal memory resource pool, one memory source pond includes multiple memory nodes, the unified management to multiple memory nodes in internal memory resource pool can be realized, the function of global administration's memory source is realized, allows the scope in registers memory region across memory node, the efficiency that internal memory is utilized is improved, and makes memory management more flexibly and efficient.
Fig. 8 is the logical construction schematic diagram of the memory management equipment 800 according to one embodiment of the invention.When the computing resource of computing device is separated with memory source, the memory source of computing device is supplied to computing resource in the form of internal memory resource pool, and memory source pond includes N number of memory node, and wherein N is the natural number more than 0.Equipment 800 realizes the function that computing resource carries out RDMA internal memory registrations in internal memory resource pool, the registration of RDMA internal memories is no longer limited to inside some memory node.As shown in figure 8, method 800 includes：
Receiving unit 802, for by the unified memory source interface internal memory registration request, the size in registers memory region to be carried in the internal memory registration request；
Processing unit 804, M memory node of physical memory is provided for being defined as the registers memory region from the multiple memory node, and each memory node is respectively necessary for the physical memory size provided in the M memory node, wherein, M is the natural number more than 0；
Transmitting element 806, for into the M memory node each memory node send respectively carried in internal memory solicitation message, each internal memory solicitation message it is described need provide physical memory size；
The receiving unit 802, which is additionally operable to receive, comes from each memory node in the M memory node
The memory information of distribution is carried in the internal memory application response message sent respectively, each internal memory application response message；
The transmitting element 806 is additionally operable to generate the information in registers memory region according to the application response message of the M memory node, and internal memory registration reply message is sent by the unified memory source interface, the internal memory registration reply message carries the information in the registers memory region.
Optionally, the processing unit 804 safeguards the free memory size of each node in the multiple memory node；The processing unit 804 is used to be defined as the M memory node that the registers memory region provides physical memory from the multiple memory node, and the physical memory size that each memory node is respectively necessary for providing in the M memory node includes：The processing unit is according to the free memory size and registers memory area size of each node in the multiple memory node of self maintained, determine that each memory node needs the physical memory size provided in the M memory node, and the M memory node.
Optionally, the physical address information of internal memory of the memory information for the distribution that the internal memory application response message is carried comprising distribution；The processing unit 804 is additionally operable to：Be registers memory region distribution virtual address according to the registers memory area size, and set up the virtual address in the registers memory region and the distribution of the M memory node internal memory physical address information between mapping relations.
Optionally, the mapping relations between the physical address information of the internal memory of the distribution of virtual address and the M memory node of the internal memory registration reply message package containing the registers memory region.
Optionally, the internal memory registration reply message package contains the Pseudo Address information in the registers memory region.
Optionally, the internal memory application response message is also comprising queue to information, and the queue pair is associated with the internal memory distributed for the internal memory solicitation message；The internal memory registration reply message also includes the queue for the internal memory association that each memory node in the M memory node is registers memory region distribution to information.
Optionally, the internal memory registration request also includes capability identification, and the capability identification is used to characterize the action type that the registers memory region allows；The internal memory solicitation message also includes the capability identification.
Optionally, the action type includes following at least one：Local reading, locally-written, long-range reading, remote write, atomic operation or binding.
Optionally, the processing unit 804 is additionally operable to：Key information is generated, and the key information is sent to the M memory node, each memory node in the M memory node is received
Key confirmation response message after, the key is sent to the computing device for applying for the registers memory region, the key information is used to characterize the authority for accessing the M memory node.
Optionally, the internal memory application response message also includes remote memory key (Remote Key, R_KEY), the remote memory key R_KEY is used to characterize the authority for accessing the internal memory application response message, and for determining that the memory node is used for the physical address for receiving the memory cell of RDMA operation jointly with reference to virtual address.It is the corresponding remote memory key R_KEY in the registers memory region that the internal memory registration reply message, which also includes each memory node in the M memory node,.
Optionally, the processing unit 804 is additionally operable to generation queue team QP, and the incidence relation set up between queue team QP and the registers memory region；The internal memory registration reply message is also comprising queue team information.
Optionally, the internal memory application request also includes process identification (PID), and the registers memory area size that processing unit 804 is asked according to process identification (PID) and internal memory registration request distributes virtual address for registers memory region.
Optionally, N number of memory node physical memory service condition in memory headroom size and memory source pond that processing unit 804 is asked according to internal memory registration request, it is defined as the M memory node that the registers memory region provides physical memory, and the physical memory size that each memory node is provided in the M memory node.
The technical scheme according to disclosed in the present embodiment, after the computing resource of computing device is decoupled with memory source, memory source is supplied to computing resource to use in the form of internal memory resource pool, one memory source pond includes multiple memory nodes, the unified management to multiple memory nodes in internal memory resource pool can be realized, the function of global administration's memory source is realized, allows the scope in registers memory region across memory node, the efficiency that internal memory is utilized is improved, and makes memory management more flexibly and efficient.
Fig. 9 is the hardware architecture diagram of the computing device equipment 900 according to one embodiment of the invention.As shown in figure 9, computing device 900 includes processor 902, internal memory 904, input/output interface 906, communication interface 908 and bus 910.Wherein, processor 902, internal memory 904, input/output interface 906 and communication interface 908 pass through the communication connection between the realization of bus 910.
Processor 902 can use general central processing unit (Central Processing Unit, CPU), microprocessor, application specific integrated circuit (Application SQecific Integrated Circuit, ASIC), or one or more integrated circuits, for performing relative program, to realize technical scheme that the embodiment of the present invention is provided.
Internal memory 904 can be read-only memory device (Read Only Memory, ROM), static memory equipment, Dram equipment or random access memory device (Random Access Memory, RAM).Internal memory 904 can be with internal memory operation system and other applications.When by software or firmware to realize technical scheme provided in an embodiment of the present invention, for realizing that the program code of technical scheme provided in an embodiment of the present invention is stored in internal memory 904, and performed by processor 902.
Input/output interface 906 is used for the data and information for receiving input, exports the data such as operating result.
Communication interface 908 uses the R-T unit of the such as, but not limited to class of transceiver one, to realize the communication between computing device 900 and other equipment or communication network.
Bus 910 may include a path, and information is transmitted between all parts of computing device 900 (such as processor 902, internal memory 904, input/output interface 906 and communication interface 908).
It should be noted that, although the meter computing device 900 shown in Fig. 9 illustrate only processor 902, internal memory 904, input/output interface 906, communication interface 908 and bus 910, but during implementing, it should be apparent to a person skilled in the art that computing device 900 is also comprising other devices necessary to realizing normal operation.Meanwhile, according to specific needs, it should be apparent to a person skilled in the art that computing device 900 can also include the hardware device for realizing other additional functions.In addition, it should be apparent to a person skilled in the art that computing device 900 also can be only comprising device necessary to the embodiment of the present invention be realized, without including whole devices shown in Fig. 9.
Hardware configuration and foregoing description shown in Fig. 9 are applied to various memory management equipments and system that the embodiment of the present invention is provided, it is adaptable to perform the various EMS memory management process that the embodiment of the present invention is provided.
In several embodiments provided herein, it should be understood that disclosed system, apparatus and method can be realized by another way.For example, device embodiment described above is only schematical, for example, the division of the module, it is only a kind of division of logic function, there can be other dividing mode when realizing, such as multiple module or components can combine or be desirably integrated into another system, or some features can be ignored, or do not perform.Another, it, by some interfaces, the INDIRECT COUPLING or communication connection of device or module, can be electrical, machinery or other forms that shown or discussed coupling or direct-coupling or communication connection each other, which can be,.
The module illustrated as separating component can be or may not be physically separate, and the part shown as module can be or may not be physical module, you can with positioned at a place, or can also be distributed on multiple mixed-media network modules mixed-medias.It can select therein according to the actual needs
Some or all of module realizes the purpose of this embodiment scheme.
In addition, each functional module in each of the invention embodiment can be integrated in a processing module or modules are individually physically present, can also two or more modules be integrated in a module.Above-mentioned integrated module can both be realized in the form of hardware, it would however also be possible to employ hardware adds the form of software function module to realize.
The above-mentioned integrated module realized in the form of software function module, interior can be present in an embodied on computer readable memory medium.Exist in above-mentioned software function module in a memory medium, including some instructions are to cause a computer equipment (can be personal computer, server, or network equipment etc.) to perform the part steps of each embodiment methods described of the invention.And foregoing memory medium includes：Mobile hard disk, read-only memory device (English：Read-Only Memory, abbreviation ROM), random access memory device (English：Random Access Memory, abbreviation RAM), magnetic disc or CD etc. are various can be with the medium of internally stored program code.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although the present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It can still modify to the technical scheme described in foregoing embodiments, or carry out equivalent substitution to which part technical characteristic；And these modifications or replacement, the essence of appropriate technical solution is departed from the protection domain of various embodiments of the present invention technical scheme.
Claims (18)
- A kind of EMS memory management process, it is characterised in that Memory Controller Hub is provided out unified memory source interface, including：Memory Controller Hub carries the size in registers memory region by the unified memory source interface internal memory registration request in the internal memory registration request；The Memory Controller Hub is defined as the M memory node that the registers memory region provides physical memory from the multiple memory node, and each memory node is respectively necessary for the physical memory size provided in the M memory node, wherein, M is the natural number more than 0；The Memory Controller Hub each memory node into the M memory node is sent respectively carries the physical memory size for needing to provide in internal memory solicitation message, each internal memory solicitation message；The Memory Controller Hub receives the memory information that distribution is carried in the internal memory application response message that each memory node is sent respectively in the M memory node, each internal memory application response message；The Memory Controller Hub generates the information in registers memory region according to the application response message of the M memory node, and internal memory registration reply message is sent by the unified memory source interface, the internal memory registration reply message carries the information in the registers memory region.
- According to the method described in claim 1, it is characterised in that the Memory Controller Hub safeguards the free memory size of each node in the multiple memory node；The Memory Controller Hub is defined as the M memory node that the registers memory region provides physical memory from the multiple memory node, and the physical memory size that each memory node is respectively necessary for providing in the M memory node includes：The Memory Controller Hub is according to the free memory size and registers memory area size of each node in the multiple memory node of self maintained, determine that each memory node needs the physical memory size provided in the M memory node, and the M memory node.
- Method according to claim 1 or 2, it is characterised in that the physical address information of internal memory of the memory information for the distribution that the internal memory application response message is carried comprising distribution；Methods described also includes：The Memory Controller Hub is according to the registers memory area size, for the registers memory region distribute virtual address, and set up the virtual address in the registers memory region and the distribution of the M memory node internal memory physical address information between mapping relations.
- Method according to claim 3, it is characterised in that the mapping relations between the physical address information of the internal memory of the distribution of virtual address and the M memory node of the internal memory registration reply message package containing the registers memory region.
- Method according to claim 3, it is characterised in that the internal memory registration reply message package contains the Pseudo Address information in the registers memory region.
- Method according to claim 4 or 5, it is characterised in that the internal memory application response message is also comprising queue to information, and the queue pair is associated with the internal memory distributed for the internal memory solicitation message；The internal memory registration reply message also includes the queue for the internal memory association that each memory node in the M memory node is registers memory region distribution to information.
- Method according to claim 6, it is characterised in that the internal memory registration request also includes capability identification, the capability identification is used to characterize the action type that the registers memory region allows；The internal memory solicitation message also includes the capability identification.
- Method according to claim any one of 1-7, it is characterised in that also include：The Memory Controller Hub generates key information, and the key information is sent to the M memory node, after the key confirmation response message of each memory node in receiving the M memory node, the key is sent to the computing device for applying for the registers memory region, the key information is used to characterize the authority for accessing the M memory node.
- A kind of memory management equipment, it is characterised in that be provided out unified memory source interface, including：Processor, memory, bus and communication interface；The memory is used to store computer executed instructions, the processor is connected with the memory by the bus, when the computing device is run, the computer executed instructions of memory storage described in the computing device, so that the memory management equipment perform claim requires the method described in any one of 1-8.
- A kind of memory management equipment, it is characterised in that be provided out unified memory source interface, is provided out unified memory source interface, including：Receiving unit, for by the unified memory source interface internal memory registration request, the size in registers memory region to be carried in the internal memory registration request；Processing unit, M memory node of physical memory is provided for being defined as the registers memory region from the multiple memory node, and each memory node is respectively necessary for the physical memory size provided in the M memory node, wherein, M is the natural number more than 0；Transmitting element, for into the M memory node each memory node send respectively carried in internal memory solicitation message, each internal memory solicitation message it is described need provide physical memory size；The receiving unit, which is additionally operable to receive, comes from each memory node difference in the M memory node The memory information of distribution is carried in the internal memory application response message of transmission, each internal memory application response message；The transmitting element is additionally operable to generate the information in registers memory region according to the application response message of the M memory node, and internal memory registration reply message is sent by the unified memory source interface, the internal memory registration reply message carries the information in the registers memory region.
- Equipment according to claim 10, it is characterised in that the processing unit is additionally operable to safeguard the free memory size of each node in the multiple memory node；The processing unit is used to be defined as the M memory node that the registers memory region provides physical memory from the multiple memory node, and the physical memory size that each memory node is respectively necessary for providing in the M memory node includes：The processing unit is according to the free memory size and registers memory area size of each node in the multiple memory node of self maintained, determine that each memory node needs the physical memory size provided in the M memory node, and the M memory node.
- Equipment according to claim 10 or 11, it is characterised in that the physical address information of internal memory of the memory information for the distribution that the internal memory application response message is carried comprising distribution；The processing unit is additionally operable to：Be registers memory region distribution virtual address according to the registers memory area size, and set up the virtual address in the registers memory region and the distribution of the M memory node internal memory physical address information between mapping relations.
- Equipment according to claim 12, it is characterised in that the mapping relations between the physical address information of the internal memory of the distribution of virtual address and the M memory node of the internal memory registration reply message package containing the registers memory region.
- Equipment according to claim 12, it is characterised in that the internal memory registration reply message package contains the Pseudo Address information in the registers memory region.
- Equipment according to claim 13 or 14, it is characterised in that the internal memory application response message is also comprising queue to information, and the queue pair is associated with the internal memory distributed for the internal memory solicitation message；The internal memory registration reply message also includes the queue for the internal memory association that each memory node in the M memory node is registers memory region distribution to information.
- Equipment according to claim 15, it is characterised in that the internal memory registration request also includes capability identification, the capability identification is used to characterize the action type that the registers memory region allows；The internal memory solicitation message also includes the capability identification.
- Equipment according to claim any one of 10-16, it is characterised in that the processing unit is additionally operable to：Key information is generated, and the key information is sent to the M memory node, After the key confirmation response message of each memory node in receiving the M memory node, the key is sent to the computing device for applying for the registers memory region, the key information is used to characterize the authority for accessing the M memory node.
- A kind of internal storage management system, it is characterised in that memory management equipment is provided out unified memory source interface, comprising：Memory management equipment described in calculate node, multiple memory nodes and claim any one of 10-17,The calculate node is used to send internal memory registration request to the memory management equipment by the unified memory source interface, the size in registers memory region is carried in the internal memory registration request, and by internal memory registration reply message of the unified memory source interface from the memory management equipment, the internal memory registration reply message carries the information in the registers memory region.The multiple memory node is used for the internal memory solicitation message for receiving the memory management equipment, is registers memory region storage allocation according to the internal memory solicitation message, and send internal memory application response message to the memory management equipment.
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