CN106992210A - Apparatus and method for manufacturing horizontal HEMT - Google Patents
Apparatus and method for manufacturing horizontal HEMT Download PDFInfo
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- CN106992210A CN106992210A CN201710043636.8A CN201710043636A CN106992210A CN 106992210 A CN106992210 A CN 106992210A CN 201710043636 A CN201710043636 A CN 201710043636A CN 106992210 A CN106992210 A CN 106992210A
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- 238000000034 method Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 9
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- 230000004888 barrier function Effects 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 12
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- 238000005530 etching Methods 0.000 claims description 2
- 239000004744 fabric Substances 0.000 claims 1
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- 229910002601 GaN Inorganic materials 0.000 description 11
- 230000008901 benefit Effects 0.000 description 7
- 238000000605 extraction Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
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- 229910052710 silicon Inorganic materials 0.000 description 5
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- 238000009826 distribution Methods 0.000 description 4
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- 229910017083 AlN Inorganic materials 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
Abstract
Present invention proposition is a kind of to include transverse direction HEMT device (100, 200, 300, 400), wherein, the horizontal HEMT includes at least one cushion (101, 201, 301, 401), another semiconductor layer (102 is arranged on the cushion, 202, 302, 402), wherein, in another semiconductor layer (102, 202, 302, 402) first electrode (103 is arranged on, 203, 303, 403), grid (104, 204, 304, 404) with second electrode (105, 205, 305, 405), it is characterized in that, in the cushion (101, 201, 301, 401) the first field plate of arranged beneath (109, 209, 309, 409), wherein, first field plate (109, 209, 309, 409) cushion (101 is contiguous at least in part, 201, 301, 401) on.
Description
Technical field
The present invention relates to a kind of device and a kind of method for manufacturing horizontal HEMT.
Background technology
HEMT (horizontal HEMT, High-electron-mobility Transistoren) passes through
Such as aluminum-gallium-nitrogen/gallium nitride (AiGaN/GaN) or indium gallium nitrogen (InGaN) or aluminium nitride/gallium nitride (AlN/GaN) heterojunction structure exist
Substrate such as sapphire, carborundum (SiC) or deposition on silicon (Si) and deposit.Here, depositions of the GaN on Si due to Si with
Big lattice between GaN mismatches and causes high load in the GaN layer of growth.In addition, silicon is in the allusion quotation for GaN growth
It is mechanical instability in the case of type temperature, generally in the range of 1000 to 1200 DEG C.In order to reduce the load, in order to manufacture
This HEMT transistors and the deposition that the doped silicon with face-centred cubic lattice structure is used in GaN, lattice structure tool
There is { 111 } face.Herein disadvantageously, high substrate leakage currents are produced.In addition, disadvantageously, this HEMT transistors puncture
The thermal coupling of voltage limiting member, thus limits heat extraction.In order to improve transistor heat extraction, the 374A1 of document DE 10 2,013 211
Describe use and the back face metalization of insulating barrier.But heat extraction also suffers from the limitation of thickness of insulating layer.
, it is known that improving breakdown voltage by substrate of the local removal below active transistor regions and limiting substrate
Leakage current.Herein disadvantageously, the thermal coupling on semiconductor back surface to such as circuit board or sheet material is worse, because part is removed
Substrate be arranged between the coupling body of heat conduction and semiconductor, thus make the heat extraction of component worse.
The content of the invention
The task of the present invention is to improve breakdown characteristics and the heat extraction of transistor.
Described device includes transverse direction HEMT, wherein, horizontal HEMT includes at least one cushion, is arranged on the cushion
Another semiconductor layer.First electrode, grid and second electrode are arranged on the semiconductor layer.According to the present invention, under cushion
Side's the first field plate of arrangement, wherein, the first field plate is at least partly abutted directly against on cushion.
Herein advantageously, improve the cut-off characteristics and on state characteristic of transistor, thus improve puncturing for the transistor
Voltage.
In expansion scheme, the first field plate has at least one step, wherein, the step is substantially perpendicular to cushion
Arrangement.
Herein advantageously, the first field plate and second electrode, so-called drain insulation so that high cut-off electricity can be realized
Pressure.
In another configuration, the step is arranged in below grid.
In expansion scheme, the step is arranged in below the bottom point of grid, wherein, the bottom point is arranged in the one of grid
On side, this is sideways to second electrode.
It is that the ratio between the length of the contact length and insulation division of the first field plate and cushion can be adjusted in this advantage
It is whole so as to realize the optimization between high heat extraction and high blocking capability.
In expansion scheme, first electrode represents source electrode, and second electrode represents drain electrode.
In another configuration, the first insulating barrier in cushion arranged beneath, wherein, the first insulating barrier is at least partly directly adjacent
It is connected on cushion.
Herein advantageously, HEMT heat extraction is improved.
In expansion scheme, the first insulating barrier has lateral length, and the lateral length is at least from grid, especially from grid bottom
Point extends to second electrode.
It is that dynamic conducting resistance (On-Widerstand) is small in this advantage, because the first field plate is spatially positioned at
Near two electrodes, this electric field of influence therebetween.Term conducting resistance be interpreted as herein source electrode and drain electrode between resistance, it
Produced in the case of HETM dynamic-ons and disconnection.
In another configuration, the first insulating barrier is designed for making the first field plate structure.First field plate portion herein
It is arranged in below the first insulating barrier and partly abuts directly against onto the first insulating barrier.
It is to be transferred in the field peak value of component inside formation in insulating barrier so that can reduce in insulating barrier in this advantage
Internal field peak value and thus without the effective power or less reliable for making component.Thus prevent from damaging in the limiting case
Component.
In another configuration, structuring, doping Semiconductor substrate is at least partially disposed at below cushion.
This, structuring, doping Semiconductor substrate is abutted directly against on cushion.
Herein advantageously, the leakage stream inside HEMT is reduced.
In expansion scheme, the first via is arranged between first electrode and the first field plate.Term via is interpreted as vertical
Electrical connection.The first via electrically connects first electrode with the first field plate herein.
It is that first electrode and the first field plate have identical current potential in this advantage.It is possible thereby to make in switching process by
Discharge more quickly in the hole produce in the electric loading in the case of high blanking voltage, charged.Therefore, it is possible to efficiently
HEMT is turned on, because switching process is rapidly carried out.In addition, targetedly changing the Electric Field Distribution especially on field plate, make
The dynamic effective power of component must be improved.
In another configuration, grid includes the second field plate, wherein, the second field plate is directly arranged on grid and laterally
At least extend towards the direction of first electrode.
At this it is advantageously possible to adjust field distribution in active transistor area.Pass through the structure of the first insulating barrier
Change the distance that can alternatively adjust field plate and drain side and the distance with cushion so that targetedly control in component
Electric Field Distribution.It is moved in this maximum field intensity on the field plate seamed edge inside insulating barrier.
In expansion scheme, it is exhausted that backplate is arranged in first with separating a vertical range with cushion below cushion
Inside edge layer.The second via electrically connects backplate with the second field plate herein so that form back side hole.
Be in this advantage can adjust grid voltage in other words grid-source voltage (in the case of the voltage, crystal
Pipe from cut-off state transform to conducting state or otherwise), i.e. so-called use voltage.Thus self-conductance can not only for example be run
Logical, so-called normal open component, and from cut-off, so-called normal off component can be run.
The method according to the invention is used to manufacture horizontal HEMT, and the horizontal HEMT has at least one cushion, slow at this
Rush on layer and arrange another semiconductor layer, wherein, first electrode, grid and second electrode are arranged on another semiconductor layer, and
Cushion be arranged in the Semiconductor substrate of doping front on, wherein, the Semiconductor substrate of doping has the back side, the back side with just
Face is opposed, and methods described includes the back side of the Semiconductor substrate by handling or etching doping at least partly to remove doping
Semiconductor substrate.In addition, methods described applies the first insulating barrier with being included in cushion rectangular structure so that the first insulating barrier
With lateral length, the lateral length extends at least between the bottom point and second electrode of grid.Methods described is additionally included in slow
Rush and the first metal layer is produced below layer and the first insulating barrier so that form the first field plate.
It is that transistor has high-breakdown-voltage in this advantage.
Further advantage is described by the following examples and provided in dependent claims.
Brief description of the drawings
Referring to preferred embodiment of the invention with accompanying drawing elaboration.Accompanying drawing is shown：
Fig. 1 according to the present invention first device,
Fig. 2 according to the present invention second device,
Fig. 3 according to the present invention 3rd device,
Fig. 4 according to the present invention the 4th device, and
Fig. 5 is used for the method for manufacturing the apparatus according to the invention.
Embodiment
Fig. 1 shows the device 100 with transverse direction HEMT according to the present invention.Transverse direction HEMT has cushion 101 herein, should
Cushion has the first semi-conducting material.Another semiconductor layer 102 is arranged on cushion 101, the semiconductor layer has second
Semi-conducting material, wherein, the second semi-conducting material has the electrode movement different from the first semi-conducting material.In other words, shape
Into heterojunction structure, because the first semi-conducting material and the second semi-conducting material are different.On another semiconductor layer 102
Arrange first electrode 103, grid 104 and second electrode 105.Selectively, gate dielectric is arranged on another semiconductor layer 102
Layer 107.The protective layer of insulation is arranged in first electrode 103, grid 104 and second electrode 105, the protective layer guard electrode
103rd, 104 and 105 from mechanical influence.In the first field plate of arranged beneath 109 of cushion 101.The field plate passes through the first insulating barrier
108 shapings.
Fig. 2 shows the second device 200 with transverse direction HEMT according to the present invention.Herein with after Fig. 1 reference
The back location of the reference of face position consistency represents identical feature.In the arranged beneath field plate 209 of cushion 201, doping
Silicon substrate 210 structured region and the first insulating barrier 208.The shape of the first field plate 209 is served as a contrast by the silicon of structuring herein
The insulating barrier 208 of bottom 210 and first shapes.
Fig. 3 shows the 3rd device 300 with transverse direction HEMT according to the present invention.Herein with Fig. 1 and Fig. 2 reference
The back location of the consistent reference of back location represent identical feature.In the first field plate of arranged beneath of cushion 301
309.Via 311 connects first electrode 303 with the first field plate 309.
In embodiment, horizontal HEMT the first field plate 109,209 and 309 has step, and the step is perpendicular to cushion
101st, 201 and 301 arrangement.The step 118,218 and 318 is substantially vertical, it means that consider foozle.
Selectively, in grid 104,204 and 304 arranged beneath steps 118,218 and 318.In this grid 104,204 and
304 bottom point 116,216 and 316 is arranged on grid 104,204 and 304 sides, and this is sideways to second electrode 105,205 and
305.In another selectable embodiment, step 118,218 and 318 is arranged in the bottom point of grid 104,204 and 304, should
Bottom point is towards first electrode 103,203 and 303.
In embodiment, first electrode 103,203 and 303 is source electrode, and second electrode 105,205 and 305 is drain electrode.
In another embodiment, the first insulating barrier has lateral length, and the length is at least from grid 104,204 and 304
Bottom point 116,216 and 316 extends to second electrode 105,205 and 305.It means that the first insulating barrier 108,208 and
308 can also cover second electrode 105,205 and 305.
Because the Semiconductor substrate 210 of doping is at least partially disposed at the lower section of cushion 101,201 and 301, doping
Semiconductor substrate 210 is initially formed the first insulating barrier 108,208 and 308, wherein, the first field plate 109,209 and 309 one side by
Structuring, doping Semiconductor substrate 210 shapes, and is on the other hand shaped by the first insulating barrier 108,208 and 308.
Fig. 4 shows the 4th device 400 with transverse direction HEMT according to the present invention.Horizontal HEMT has cushion 410,
Another semiconductor layer 402 is arranged on the cushion.First electrode 403, grid 404 and leakage are arranged on another semiconductor layer 402
Pole 405.Selectively, gate dielectric 407 is arranged on the second layer 402.Grid 404 has the second field plate 412, this second
Plate laterally extends from grid 404 towards the direction of source electrode 403.Transverse direction HEMT 400 has the source electrode field plate of split, the source herein
Pole field plate is connected by via 420 with source electrode 403.The source electrode field plate of split includes region 421 and 422.In addition, laterally
HEMT400 has backplate 423, and the backplate is electrically connected by means of the second via 424 with the second field plate 412.Split
Source electrode field plate and backplate 423 are all shaped by the first insulating barrier 408.
In embodiment, cushion 101,201,301 and 401 includes GaN.Another semiconductor layer 102,202,302 and 402
Including AlGaN or InGaN or AlN.
First insulating barrier 108,208,308 and 408 includes such as silica or SiN.
First field plate 109,209 and 309 is metal, wherein, the metal has high heat conduction ability, and the capacity of heat transmission can
The first field plate is selectively set to be used as supplementary electrode.Metal is, for example, copper, aluminium, titanium, nickel, silver or gold.First field plate 109,
209 and 309 can also be by multiple layer metal stacking construction.Semiconductor substrate 210 is, for example, the Si or SiC adulterated.
Fig. 5 shows the method for manufacturing the device with transverse direction HEMT.Said method is at the HEMT back side, exist
Implement on the side of electrode.Therefore it is related to back side process.Methods described is started by step 1030, is led in this step
Cross the semiconductor lining for the Semiconductor substrate back side of doping being handled or being etched the doping for removing transverse direction HEMT at least in part
Bottom.In step 1060 below, the first insulating barrier is applied on the back side of the Semiconductor substrate of doping and structure is carried out
Change so that the first insulating barrier has lateral length, and the long horizontal directive tendency extends at least between the bottom point and second electrode of grid.
Grid is not fully achieved in insulating barrier in another embodiment.
In step 1070 below, the first metal layer is applied on cushion and the first insulating barrier and structure is carried out
Change so that form the first field plate.
In another embodiment, horizontal HEMT is applied to foreign substrate, such as glass in selectable step 1020
On.The step is carried out before step 1030.Applied HEMT fronts, the i.e. side with electrode protected herein by protective layer
It is added in foreign substrate.This causes horizontal HEMT processing to become simple.Selectively, when terminating manufacture method in step 1150
Middle removal foreign substrate.
In another embodiment, another step is implemented between step 1030 and 1060.Directly it is connected in this step 1040
On to step 1030, wherein, removed in step 1040 by means of dry ecthing in first electrode area by cushion and another
The heterojunction structure of semiconductor layer composition.Plated through hole is also realized from there through second metal layer is applied in process 1070.
In another embodiment, another step 1050 is carried out after selectable step 1040, is removed in this step
The region of first electrode is until positive protective layer.Another step 1080 is carried out after implementation steps 1060 and 1070, at this
The first metal layer carries out structuring in step, thus exposes the region below the section between grid and drain electrode.Following
In step 1090, the first metal layer in the region below first electrode is removed so that produce the region for the second via.
In step 1100 below, the second insulating barrier is applied in the region below the section between grid and drain electrode.Below
Step 1110 in, remove the second insulating barrier in the region below source contact.In step 1120 below, apply the
In two metal levels, and step 1130 below, apply the 3rd insulating barrier.In step 1140 below, apply the 3rd gold medal
Belong to layer.By constructing the source electrode field plate (source electrode field plate is made up of first, second, and third metal level) of split, it can be directed to
Control the Electric Field Distribution in component to property.Maximum field strength can by this way be moved on field plate seamed edge and be thus moved to
Inside first insulating barrier.It reduce in GaN cushions until the peak electric field of upside protective layer.Thus transistor is improved
Breakdown voltage simultaneously reduces hole transfer hole generation in other words.Therefore dynamic property is improved.The reliability of component is improved simultaneously.With
The transistor that this mode is manufactured can be used in many power electronic converters, such as the hybrid power in automotive field
Car or electric car, and for realizing such as inversion system in photovoltaic art.
Claims (13)
1. include transverse direction HEMT device (100,200,300,400), wherein, the horizontal HEMT includes at least one cushion
(101,201,301,401), arrange another semiconductor layer (102,202,302,402) on the cushion, wherein, described another
In semi-conductor layer (102,202,302,402) arrange first electrode (103,203,303,403), grid (104,204,304,
404) with second electrode (105,205,305,405), it is characterised in that below the cushion (101,201,301,401)
The first field plate (109,209,309,409) is arranged, wherein, first field plate (109,209,309,409) is adjacent at least in part
It is connected on the cushion (101,201,301,401).
2. device (100,200,300,400) according to claim 1, it is characterised in that first field plate (109,
209th, 309,409) there is at least one step (118,218,318,418), wherein, the step (118,218,318,418)
Especially arranged substantially perpendicular to the cushion (101,201,301,401).
3. device (100,200,300,400) according to claim 2, it is characterised in that the step (118,218,
318th, 418) it is arranged in below the grid (104,204,304,404).
4. the device (100,200,300,400) according to Claims 2 or 3, it is characterised in that the step (118,
218th, 318 below the bottom point (116,216,316,416) for, 418) being arranged in the grid (104,204,304,404), wherein,
The bottom point (116,216,316,416) is arranged on the side of the grid (104,204,304,404), and this is sideways to described
Second electrode (105,205,305,405).
5. the device (100,200,300,400) according to any one of the claims, it is characterised in that described first
Electrode (103,203,303,403) is source electrode, and the second electrode (105,205,305,405) is drain electrode.
6. the device (100,200,300,400) according to any one of the claims, it is characterised in that described first
Insulating barrier (108,208,308,408) is arranged in below the cushion (101,201,301,401), and straight at least in part
It is adjoining to be connected on the cushion (101,201,301,401).
7. device (100,200,300,400) according to claim 6, it is characterised in that first insulating barrier (108,
208th, 308,408) there is lateral length, the lateral length is at least from the grid (104,204,304,404), especially described
Bottom point (116,216,316,416) extends to the second electrode (105,205,305,405).
8. the device (100,200,300,400) according to claim 6 or 7, it is characterised in that first insulating barrier
(108,208,308,408) are designed to make first field plate (109,209,309) structuring, wherein, first field plate
(109,209,309) are partially positioned in below first insulating barrier (108,208,308,408) and partly directly adjacent
It is connected on first insulating barrier (108,208,308,408).
9. the device (100,200,300,400) according to any one of the claims, it is characterised in that structuring
, the Semiconductor substrate (210) of doping be at least partially disposed at below the cushion (101,201,301,401), wherein,
The Semiconductor substrate (210) is abutted directly against on the cushion (101,201,301,401).
10. the device (100,200,300,400) according to any one of the claims, it is characterised in that the first mistake
Hole (311) is arranged between the first electrode (103,203,303,403) and first field plate (109,209,309), its
In, first via (311) by the first electrode (103,203,303,403) and first field plate (109,209,
309) electrically connect.
11. the device (100,200,300,400) according to any one of the claims, it is characterised in that the grid
Pole (104,204,304,404) includes the second field plate (412), wherein, second field plate (412) is directly arranged at the grid
Laterally at least extend on (104,204,304,404) and towards the direction of the first electrode (103,203,303,403).
12. device (100,200,300,400) according to claim 11, it is characterised in that backplate (415) is in institute
State cushion (101,201,301,401) lower section and the cushion (101,201,301,401) with separating vertical range cloth
Put internal in first insulating barrier (108,208,308,408), wherein, the second via (413) is by the backplate (415)
Electrically connected with second field plate (412) so that form back side hole.
13. the method for manufacturing horizontal HEMT (100,200,300,400), wherein, the horizontal HEMT includes at least one
Cushion (101,201,301,401), arranges another semiconductor layer (102,202,302,402) on the cushion, wherein,
On another semiconductor layer (102,202,302,402) arrange first electrode (103,203,303,403), grid (104,
, 404) and second electrode (105,205,305,405), and the cushion (101,201,301,401) is arranged in 204,304
On the front of the Semiconductor substrate (210) of doping, and the Semiconductor substrate (210) of the doping has the back side, and the back side leads to
Cross following steps opposed with front：
By the back side for the Semiconductor substrate (210) for etching the doping, (1030) described doping is removed at least in part
Semiconductor substrate (210),
First insulating barrier (108,208,308,408) is structurally applied (1060) the cushion (101,
201st, 301,401) lower section so that first insulating barrier (108,208,308,408) from the grid (104,204,304,
404) bottom point (116,216,316,416) laterally extends towards the direction of the second electrode (105,205,305,405), its
In, first insulating barrier especially at least extends to the second electrode from the bottom point of the grid, and
The first metal layer is applied into (1070) and structuring is to the cushion (101,201,301,401) and described first exhausted
In edge layer (108,208,308,408) so that form the first field plate (109,209,309).
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| DE102016200825.0 | 2016-01-21 | ||
| DE102016200825.0A DE102016200825A1 (en) | 2016-01-21 | 2016-01-21 | Apparatus and method for producing a lateral HEMT |
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| DE102016200825A1 (en) | 2017-07-27 |
| TWI718233B (en) | 2021-02-11 |
| TW201737352A (en) | 2017-10-16 |
| CN106992210B (en) | 2022-08-16 |
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