CN106991979B

CN106991979B - Electronic paper and display device

Info

Publication number: CN106991979B
Application number: CN201710379720.7A
Authority: CN
Inventors: 林柏全; 席克瑞; 许祖钊
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2017-05-25
Filing date: 2017-05-25
Publication date: 2019-06-07
Anticipated expiration: 2037-05-25
Also published as: CN106991979A

Abstract

The invention discloses electronic paper and a display device, and relates to the technical field of electronic paper display, wherein the electronic paper comprises a gate drive circuit, the gate drive circuit comprises a multi-stage gate scanning unit, the gate scanning unit is used for providing gate drive signals for a gate line, and the gate scanning unit comprises a plurality of transistors; at least one of the plurality of transistors is a multi-channel transistor. According to the technical scheme provided by the invention, the pixel unit is driven by the grid drive circuit arranged in the electronic paper so as to achieve the purpose of display; in addition, the grid driving circuit comprises a multi-stage grid scanning unit, wherein at least one of the transistors included in the grid scanning unit is a multi-channel transistor, and the design of the multi-channel transistor can avoid the situation that the characteristic drift is caused by overhigh grid voltage in the grid driving circuit, so that the high display effect of the display device is ensured.

Description

Electronic paper and display device

Technical Field

The invention relates to the technical field of electronic paper display, in particular to electronic paper and a display device.

Background

Electronic ink displays that are thin, flexible, and erasable like paper are generally known in the art as electronic paper (E-paper). The electronic paper has the advantages of paper, can refresh display contents like a common liquid crystal display, and saves much power compared with the liquid crystal display, so the electronic paper is more and more popular in the market. A conventional electronic paper display device includes a plurality of gate lines, a plurality of data lines, a plurality of pixel units surrounded by the plurality of gate lines and the plurality of data lines, a gate driving circuit for supplying a gate driving signal to the gate lines, a data driving circuit for supplying a data driving signal to the data lines, and the like. Among them, the display effect of the conventional electronic paper display device needs to be improved.

Disclosure of Invention

In view of the above, the present invention provides an electronic paper and a display device, in which a gate driving circuit disposed in the electronic paper drives a pixel unit to achieve the purpose of displaying; in addition, the grid driving circuit comprises a multi-stage grid scanning unit, wherein at least one of the transistors included in the grid scanning unit is a multi-channel transistor, and the design of the multi-channel transistor can avoid the situation that the characteristic drift is caused by overhigh grid voltage in the grid driving circuit, so that the high display effect of the display device is ensured.

In order to achieve the purpose, the technical scheme provided by the invention is as follows:

an electronic paper, the electronic paper comprising a gate driving circuit, the gate driving circuit comprising a multi-stage gate scanning unit for providing gate driving signals to gate lines, the gate scanning unit comprising a plurality of transistors;

at least one of the plurality of transistors is a multi-channel transistor.

Correspondingly, the invention further provides a display device which comprises the electronic paper.

Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:

the invention provides electronic paper and a display device, wherein the electronic paper comprises a gate drive circuit, the gate drive circuit comprises a multi-stage gate scanning unit, the gate scanning unit is used for providing gate drive signals for gate lines, and the gate scanning unit comprises a plurality of transistors; at least one of the plurality of transistors is a multi-channel transistor. According to the technical scheme provided by the invention, the pixel unit is driven by the grid drive circuit arranged in the electronic paper so as to achieve the purpose of display; in addition, the grid driving circuit comprises a multi-stage grid scanning unit, wherein at least one of the transistors included in the grid scanning unit is a multi-channel transistor, and the design of the multi-channel transistor can avoid the situation that the characteristic drift is caused by overhigh grid voltage in the grid driving circuit, so that the high display effect of the display device is ensured.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a gate scan unit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another gate scan unit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a double-channel transistor according to an embodiment of the present disclosure;

FIG. 4a is a schematic view of a cross-sectional view along AA' of FIG. 3;

FIG. 4b is a schematic view of another cross-sectional structure along the direction AA' in FIG. 3;

fig. 5 is a schematic structural diagram of another double-channel transistor provided in the embodiment of the present application;

fig. 6a is a schematic structural diagram of an electronic paper according to an embodiment of the present application;

fig. 6b is a schematic structural diagram of another electronic paper provided in an embodiment of the present application;

fig. 7 is a schematic structural diagram of another electronic paper provided in an embodiment of the present application;

fig. 8 is a schematic structural diagram of another gate scan unit according to an embodiment of the present disclosure;

FIG. 9 is a timing diagram provided in accordance with an embodiment of the present application;

fig. 10 is a schematic structural diagram of another gate scan unit according to an embodiment of the present disclosure;

fig. 11a is a schematic top view of a part of an electronic paper according to an embodiment of the present disclosure;

fig. 11b is a schematic structural diagram of another electronic paper according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As described in the background art, the conventional electronic paper display device includes a plurality of gate lines, a plurality of data lines, a plurality of pixel units surrounded by the plurality of gate lines and the plurality of data lines, a gate driving circuit supplying a gate driving signal to the gate lines, a data driving circuit supplying a data driving signal to the data lines, and the like. Among them, the display effect of the conventional electronic paper display device needs to be improved. Particularly, nowadays, users have more and more demands for high-resolution electronic paper display devices, and therefore, research and development of a new driving mode of electronic paper display devices is one of the main research trends of technicians today; in addition, according to the present application, it is found through research that, because the scanning frequency is low and the scanning time is too long when the electronic paper display device displays a picture, compared with the liquid crystal display device, a new driving mode needs to be developed, and at the same time, the drift characteristic of the transistor used in the driving structure needs to be considered, so that the situation that the display effect is reduced due to the characteristic drift of the transistor in the display process is avoided.

Based on this, the embodiment of the application provides an electronic paper and a display device, wherein the electronic paper comprises a gate driving circuit, the gate driving circuit comprises a multi-stage gate scanning unit, the gate scanning unit is used for providing a gate driving signal for a gate line, and the gate scanning unit comprises a plurality of transistors; at least one of the plurality of transistors is a multi-channel transistor. According to the above, the purpose of displaying is achieved by driving the pixels through the gate driving circuit arranged in the electronic paper, and meanwhile, the high resolution of the electronic paper can be ensured due to the fact that the gate driving circuit is adopted to achieve the driving mode of scanning display; in addition, the grid driving circuit comprises a multi-stage grid scanning unit, wherein at least one of the transistors included in the grid scanning unit is a multi-channel transistor, and the design of the multi-channel transistor can avoid the situation that the characteristic drift is caused by overhigh grid voltage in the grid driving circuit, so that the high display effect of the display device is ensured.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a gate scan unit according to an embodiment of the present disclosure, where the gate scan unit includes:

the input module 100, the pull-up node P, the pull-up control module 200, the pull-down node Q, the pull-down control module 300, the first coupling module 410, the second coupling module 420, the output transistor Mout and the output terminal Gout;

the input module 100 controls an on state between a first voltage terminal DIR1 and the pull-up node P in response to a signal of a first control terminal Set and controls an on state between a second voltage terminal DIR2 and the pull-up node P in response to a signal of a second control terminal Reset, wherein levels of signals output from the first voltage terminal DIR1 and the second voltage terminal DIR2 are opposite; the input module 100 is configured to transmit a level signal output by the first voltage terminal DIR1 or the second voltage terminal DIR2 to the pull-up node P according to an active level signal control of the first control terminal Set or the second control terminal Reset (wherein the active level signal may be a high level signal or a low level signal, which is determined according to a type of a transistor connected to the control terminal in the input module), so as to control a level state of the pull-up node P.

The pull-up control module 200 controls an on state between the pull-down node Q and a reference voltage terminal Vref in response to a signal of the pull-up node P, and the pull-down control module 300 controls an on state between the pull-up node P and the output terminal Gout and the reference voltage terminal Vref, respectively, in response to a signal of the pull-down node Q; the pull-up control module 200 is configured to transmit a level signal output by a reference voltage terminal Vref to the pull-down node Q according to the active level signal control of the pull-up node P, so as to control a level state of the pull-down node Q; and the pull-down control module 300 is configured to transmit the level signal output by the reference voltage terminal Vref to the pull-up node P and the output terminal Gout, respectively, according to the active level signal control of the pull-down node Q, so as to control the level states of the pull-up node P and the output terminal Gout.

The first coupling module 410 is configured to couple a signal of the output terminal Gout to the pull-up node P, the second coupling module 420 is configured to couple a clock signal of the first clock signal terminal CK1 to the pull-down node Q, and when the pull-up control module 200 controls a connection between the pull-down node Q and the reference voltage terminal Vref, the signal of the pull-down node Q is a signal output by the reference voltage terminal Vref; the first coupling module 410 is configured to couple a level signal of the output terminal Gout to a pull-up node P, so as to control and maintain the level signal of the pull-up node P; and the second coupling module 420 is configured to couple the level signal output by the reference voltage terminal Vref to the pull-down node Q, so as to control and maintain the level signal of the pull-down node Q.

A gate of the output transistor Mout is electrically connected to the pull-up node P, a first terminal of the output transistor Mout is electrically connected to the first clock signal terminal CK1, and a second terminal of the output transistor Mout is electrically connected to the output terminal Gout. The output transistor Mout is used for transmitting the level signal output from the first clock signal terminal CK1 to the output terminal Gout according to the active level signal control of the pull-up node P.

Further, in an embodiment of the present application, the gate scan unit further includes a reset module, configured to reset signals of the pull-up node and the output terminal before scanning, so as to ensure a high scanning effect. Referring to fig. 2, fig. 2 is a schematic structural diagram of another gate scan unit provided in the embodiment of the present application, where the gate scan unit further includes:

a reset module 500, the reset module 500 being responsive to a signal of a reset control terminal R0 for controlling on-states between a reset signal terminal V0 and the pull-up node P and an output terminal Gout, respectively. The reset module 500 is configured to transmit a level signal output by the reset signal terminal V0 to the pull-up node P and the output terminal Gout according to active level signal control of the reset control terminal R0 before scanning, so as to reset the pull-up node P and the output terminal Gout, thereby ensuring that a subsequent scanning process is performed smoothly.

Optionally, in the gate scan unit provided in this embodiment of the present application, a transistor included in at least one of the output transistor, the input module, the pull-up control module, the pull-down control module, and the reset module is a multi-channel transistor. The design of the multi-channel transistor can avoid the situation that the characteristic drift is caused by overhigh grid voltage in the grid driving circuit, and ensures that the display effect of the display device is high.

Optionally, in the gate scanning unit provided in the embodiment of the present application, the multi-channel transistor may be a double-channel transistor, where the double-channel transistor is configured to ensure that a situation that a characteristic drift is caused by an excessively high gate voltage in the gate driving circuit is avoided, and a large layout area is not occupied. Specifically, referring to fig. 3 and fig. 4a, a detailed description is given of a double-channel transistor provided in the present embodiment, fig. 3 is a schematic structural diagram of a double-channel transistor provided in the present embodiment, and fig. 4a is a schematic structural diagram of a cross section along the AA' direction in fig. 3. Wherein the double channel transistor comprises:

a gate G;

a semiconductor layer 20 provided to be insulated from the gate electrode G;

and a source electrode S and a drain electrode D in contact with the semiconductor layer 20 and disposed insulated from the gate electrode;

wherein the source S includes at least one source stripe 30, the drain D includes a plurality of drain stripes extending in the same direction as the source stripe 30, the drain stripes include first sub-drain stripes 41 and second sub-drain stripes 42, the source stripes 30 and the drain stripes are alternately arranged, and the second sub-drain stripes 42 are adjacent to the source stripe 30; the source S and drain D regions include a plurality of electrode stripes arranged in sequence, and a second sub-drain stripe 42 is disposed between two adjacent source stripes 30 and first sub-drain stripes 41. The first ends of all the source bars 30 are connected, the second ends of all the first sub-drain bars 41 are connected, the first ends or the second ends of two adjacent second sub-drain bars 42 are connected, and the end connection regions of two adjacent second sub-drain bars 42 are not overlapped with the source bars 30 and the first sub-drain bars 41, wherein the first ends of the second sub-drain bars 42 are opposite to the second ends of the second sub-drain bars 42, and the first ends of the source bars 30 are opposite to the second ends of the first sub-drain bars 41.

Referring to fig. 4a, the double-channel transistor provided in the embodiment of the present application may be a bottom-gate double-channel transistor, that is, the double-channel transistor may include:

a gate electrode G on the substrate;

a gate insulating layer 10 covering the gate electrode G;

a semiconductor layer 20 on the side of the gate insulating layer 10 facing away from the gate electrode G;

and a source electrode S and a drain electrode D on a side of the semiconductor layer 20 facing away from the gate electrode G.

In addition, the double-channel transistor provided in the embodiment of the present application may also be a top-gate double-channel transistor, as shown in fig. 4b, and fig. 4b is another schematic cross-sectional structure view along the AA' direction in fig. 3, where the top-gate double-channel transistor may include:

a semiconductor layer 20 over the substrate;

a first insulating layer 11 on the side of the semiconductor layer 20 facing away from the substrate;

a gate electrode G on a side of the first insulating layer 11 facing away from the semiconductor layer 20;

the second insulating layer 12 is positioned on one side of the grid G, which is far away from the first insulating layer 11;

and a source electrode S and a drain electrode D on a side of the second insulating layer 12 facing away from the gate electrode G, wherein the source electrode S and the drain electrode D are in contact with the semiconductor layer 20 through respective corresponding via holes 13.

It should be noted that, in the embodiment of the present application, no specific limitation is imposed on the top gate structure and the bottom gate structure of the double-channel transistor, and the top gate structure and the bottom gate structure need to be specifically selected according to practical applications. As shown in fig. 3, 4a and 4b, the source S of the double channel transistor comprises a plurality of source stripes 30. In addition, referring to fig. 5, fig. 5 is a schematic structural diagram of another double-channel transistor provided in the embodiment of the present application, where the source S may include one source stripe 30, the drain D may include two first sub-drain stripes 41 and two second sub-drain stripes 42, any one of the second sub-drain stripes 42 is located between the first sub-drain stripe 41 and the source stripe 30, and the source stripe 30 is located between the two second sub-drain stripes 42.

It should be noted that, in the present application, the number of the source bars and the number of the drain bars in the double-channel transistor are not specifically limited, and the number needs to be specifically designed according to practical applications, so as to balance the layout area design and the display effect of the display device.

In an embodiment of the present application, the gate driving circuit of the electronic paper may be partially located in the inner frame region thereof, so as to reduce the frame region of the electronic paper, and meet the design trend of narrow frames. Referring to fig. 6a, fig. 6a is a schematic structural diagram of an electronic paper according to an embodiment of the present application, where the electronic paper includes:

a display area 1000 and a non-display area surrounding the display area 1000, the non-display area including an inner frame area 2001, an outer frame area 2002, the inner frame area 2001 surrounding the display area 1000, the outer frame area 2002 surrounding the inner frame area 2001,

the gate driving circuit 3000 is located in the non-display region, and at least a portion of the gate driving circuit 3000 is located in the inner frame region 2001.

Specifically, the inner frame region is a region for fixedly displaying black or white, that is, the electronic paper includes an electrophoretic film (not shown in the figure), wherein the electrophoretic film covers the display region 1000, and a portion of the electrophoretic film outside the display region 1000 covers the inner frame region 2001; and, a driving electrode (not shown) surrounding the display region 1000 is disposed in the inner frame region 2001 of the electronic paper, and the portion of the electrophoretic film corresponding to the inner frame region can be driven to display white or black due to the driving action of the driving electrode. In the present application, the gate driving circuit 3000 is partially formed in the inner frame region, so that the width of the outer frame region can be effectively reduced to reduce the width of the non-display region, thereby meeting the trend of narrow frame design.

Optionally, referring to fig. 6b, fig. 6b is a schematic structural diagram of another electronic paper provided in this embodiment, where the gate driving circuit 3000 provided in this embodiment may be located in the inner frame region 2001, and the gate driving circuit 3000 is entirely disposed in the inner frame region 2001, so as to reduce the width of the outer frame region as much as possible, and then reduce the width of the non-display region of the display panel as much as possible, thereby implementing a narrow frame design.

Alternatively, referring to fig. 6a, the gate driving circuit provided in the embodiment of the present application may be located at a first end of the gate line extending direction X.

Optionally, the gate driving circuit provided in this embodiment of the present application may include two parts, as described with reference to fig. 7, fig. 7 is a schematic structural diagram of another electronic paper provided in this embodiment of the present application, where the gate driving circuit includes a first sub-gate driving circuit 3001 and a second sub-gate driving circuit 3002, and the first sub-gate driving circuit 3001 and the second sub-gate driving circuit 3002 are respectively located at two ends of the gate line extending direction X.

Specifically, as shown in fig. 7, both the first sub-gate driver circuit 3001 and the second sub-gate driver circuit 3002 may be partially located in the inner frame region 2001; it should be noted that, the first sub-gate driving circuit and the second sub-gate driving circuit may be both located in the inner frame region, and the present application is not particularly limited and needs to be designed according to practical applications. In the embodiment of the application, the gate driving circuit is divided into two parts which are respectively arranged in the non-display areas corresponding to the two ends of the gate line in the extending direction, so that the purpose of maximally utilizing the layout of the non-display areas can be achieved, and the layout design of the electronic paper circuit is optimized.

A specific gate scan cell provided in the embodiments of the present application is described below with reference to the drawings, and the following embodiments take the example where the transistor is an N-type transistor, the reference voltage terminal outputs a low level signal, the first voltage terminal outputs a high level signal, and the second voltage terminal outputs a low level signal. It should be noted that, in other embodiments of the present application, the type of the transistor may also be a P-type transistor, and the reference voltage terminal, the first voltage terminal, and the second voltage terminal may further output a signal with a level opposite to that of the above-mentioned signal (that is, the reference voltage terminal may output a high-level signal, the first voltage terminal may output a low-level signal, and the second voltage terminal may output a high-level signal).

Optionally, referring to fig. 8, fig. 8 is a schematic structural diagram of another gate scanning unit provided in the embodiment of the present application, where the input module provided in the embodiment of the present application includes:

a first transistor M1 and a second transistor M2;

a gate of the first transistor M1 is electrically connected to the first control terminal Set, a first terminal of the first transistor M1 is electrically connected to the first voltage terminal DIR1, and a second terminal of the first transistor M1 is electrically connected to the pull-up node P;

the gate of the second transistor M2 is electrically connected to the second control terminal Reset, the first terminal of the second transistor M2 is electrically connected to the second voltage terminal DIR2, and the second terminal of the second transistor M2 is electrically connected to the pull-up node P.

Specifically, in the embodiment of the present application, the input module is configured to transmit the level signal output by the first voltage terminal DIR1 or the second voltage terminal DIR2 to the pull-up node P according to the active level signal control of the first control terminal Set or the second control terminal Reset, so as to control the level state of the pull-up node P.

Optionally, as shown in fig. 8, the pull-up control module provided in the embodiment of the present application includes:

a third transistor M3;

a gate of the third transistor M3 is electrically connected to the pull-up node P, a first terminal of the third transistor M3 is electrically connected to the reference voltage terminal Vref, and a second terminal of the third transistor M3 is electrically connected to the pull-down node Q.

Specifically, in the embodiment of the present application, the pull-up control module is configured to transmit a level signal output by a reference voltage terminal Vref to the pull-down node Q according to the active level signal control of the pull-up node P, so as to control a level state of the pull-down node Q;

optionally, as shown in fig. 8, the pull-down control module provided in the embodiment of the present application includes:

a fourth transistor M4 and a fifth transistor M5;

the gates of the fourth transistor M4 and the fifth transistor M5 are electrically connected to the pull-down node Q, the first terminals of the fourth transistor M4 and the fifth transistor M5 are electrically connected to the reference voltage terminal Vref, the second terminal of the fourth transistor M4 is electrically connected to the pull-up node P, and the second terminal of the fifth transistor M5 is electrically connected to the output terminal Gout.

Specifically, in the embodiment of the present application, the pull-down control module is configured to transmit the level signal output by the reference voltage terminal Vref to the pull-up node P and the output terminal Gout respectively according to the active level signal control of the pull-down node Q, so as to control the level states of the pull-up node P and the output terminal Gout.

Optionally, as shown in fig. 8, the first coupling module provided in the embodiment of the present application includes a first capacitor C1, and the second coupling module includes a second capacitor C2;

a first plate of the first capacitor C1 is electrically connected to the output terminal Gout, and a second plate of the first capacitor C1 is electrically connected to the pull-up node P;

a first plate of the second capacitor C2 is electrically connected to the first clock signal terminal CK1, and a second plate of the second capacitor C2 is electrically connected to the pull-down node Q.

Specifically, in the embodiment of the present application, the first coupling module is configured to couple a level signal at the output terminal Gout to the pull-up node P, so as to control and maintain the level signal at the pull-up node P; and the second coupling module is used for coupling the level signal output by the reference voltage terminal Vref to the pull-down node Q so as to control and maintain the level signal of the pull-down node Q.

The operation of the gate scan cell provided in this embodiment of the present application is described in detail with reference to fig. 8 and 9, and fig. 9 is a timing diagram provided in this embodiment of the present application. The working process of the gate scanning unit comprises a first stage T1, a second stage T2 and a third stage T3;

in the first phase T1, the first control signal terminal Set outputs a high level signal to control the first transistor M1 to be turned on, and the first transistor M1 transmits the high level signal output by the first voltage terminal DIR1 to the pull-up node P;

the pull-up node P of the high level controls the third transistor M3 and the output transistor Mout to be turned on, the third transistor M3 transmits the low level signal outputted from the reference voltage terminal Vref to the pull-down node Q, and the output transistor Mout transmits the low level signal outputted from the first clock signal terminal CK1 at this time to the output terminal Gout.

In the second stage T2, the output transistor Mout transmits the high level signal output by the first clock signal terminal CK1 at this time to the output terminal Gout, and the first capacitor C1 couples the high level signal of the output terminal Gout to the pull-up node P, so that the high level signal of the pull-up node P is pulled up again;

the pull-up node P keeps controlling the third transistor M3 to be turned on, and transmits the low level signal outputted from the reference voltage terminal Vref to the pull-down node Q.

In the third stage T3, the second control signal terminal Reset outputs a high level signal to control the second transistor M2 to turn on, and the second transistor M2 transmits a low level signal output by the second voltage terminal DIR2 to the pull-up node P, so that the transistors controlled by the pull-up node P are all turned off, and no signal output at the output terminal Gout is equivalent to a low level.

Further, referring to fig. 8, in an embodiment of the present invention, in order to ensure that the output terminal Gout outputs a low level signal in a time period before the third stage T3 and the scanning process of the subsequent gate driving circuit are ended, the gate scanning unit further includes:

a sixth transistor M6;

a gate of the sixth transistor M6 is electrically connected to the second clock signal terminal CK2, a first terminal of the sixth transistor M6 is electrically connected to the reference voltage terminal Vref, and a second terminal of the sixth transistor M6 is electrically connected to the output terminal Gout;

the clock signal output from the second clock signal terminal CK2 is inverted with respect to the clock signal output from the first clock signal terminal CK 1.

Optionally, the sixth transistor M6 is a multi-channel transistor.

Specifically, by providing the sixth transistor M6 as a multi-channel transistor, it is possible to prevent the sixth transistor M6 from having characteristic drift, and to keep the transmission signal of the sixth transistor M6 stable.

Before the third stage T3 and the subsequent scanning process of the gate driving circuit are finished, the second capacitor C2 can couple the high level signal output by the first clock signal terminal CK1 to the pull-down node Q, so as to control the third transistor M3 to be turned on, and the high level signal output by the second clock signal terminal CK2 controls the sixth transistor M6 to be turned on, and further, according to the inverted characteristic of the clock signal output by the second clock signal terminal CK2 and the clock signal output by the first clock signal terminal CK1, the third transistor M3 and the sixth transistor M6 alternately transmit the low level signal output by the reference voltage terminal Vref to the output terminal Gout, thereby ensuring the stability of the output signal of the output terminal Gout.

In addition, referring to fig. 10, fig. 10 is a schematic structural diagram of another gate scanning unit provided in the embodiment of the present application, and the reset module provided in the embodiment of the present application includes:

a seventh transistor M7 and an eighth transistor M8;

the gates of the seventh transistor M7 and the eighth transistor M8 are both connected to the reset control terminal R0, the first terminals of the seventh transistor M7 and the eighth transistor M8 are both connected to the reset signal terminal V0, the second terminal of the seventh transistor M7 is connected to the pull-up node P, and the second terminal of the eighth transistor M8 is connected to the output terminal Gout.

Before the gate driving circuit is scanned, the seventh transistor M7 and the eighth transistor M8 are controlled to be turned on by the reset control terminal R0 of the reset module, so that the reset signal output by the reset signal terminal V0 is respectively transmitted to the pull-up node P and the output terminal Gout by the seventh transistor M7 and the eighth transistor M8, thereby ensuring that the effect of the subsequent scanning process is high.

In the embodiment of the present application, the design of the multi-channel transistor can avoid the situation that the gate voltage is too high in the gate driving circuit to cause characteristic drift, and ensure that the display effect of the display device is high, that is, the first to eighth transistors and the output transistor can be all thin film transistors and are multi-channel transistors. In particular, when the first transistor and the second transistor are multi-channel transistors, high potential stability of the pull-up node can be ensured. And when the output transistor is a multi-channel transistor, the signal stability of the output end is ensured, and unnecessary scanning signals are avoided.

In an embodiment of the present application, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the output transistor are all multi-channel transistors.

Specifically, all transistors are set as multi-channel transistors, so that the condition that the characteristic drift is caused when the grid voltage of the transistors is too high is avoided, the stability of the grid driving circuit is high, and the display effect of the display device is high.

In another embodiment of the present application, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all single-channel transistors, and the output transistor is a multi-channel transistor.

Specifically, the output transistor is a multi-channel transistor, so that the condition of characteristic drift of the output transistor can be improved, and the high stability of an output signal at an output end is ensured; and because the first transistor to the eighth transistor are single-channel transistors and occupy small layout area, the layout area of the gate drive circuit is ensured to be small under the condition of ensuring the output signal of the output end to be stable, and the development trend of narrow frames of the display device is met.

In another embodiment of the present application, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the output transistor are single-channel transistors, and the first transistor and the second transistor are multi-channel transistors.

Specifically, the first transistor and the second transistor are provided with multi-channel transistors, so that the characteristic drift condition of the first transistor and the second transistor is improved, and the high potential stability of a pull-up node is ensured; and because the third transistor to the eighth transistor and the output transistor are single-channel transistors, the occupied layout area is small, the layout area of the gate drive circuit is ensured to be small under the condition that the pull-up node signals are stable, and the development trend of narrow frames of the display device is met.

On the other hand, the embodiment of the application also provides a display device, and the display device comprises the electronic paper provided by any one of the embodiments.

Referring to fig. 11a, fig. 11a is a schematic diagram of a partial top view structure of an electronic paper according to an embodiment of the present application, where the electronic paper includes:

a substrate 1, wherein a plurality of data lines 110 arranged along a first direction and extending along a second direction are arranged on a first side of the substrate 1, and the first direction intersects with the second direction;

a plurality of gate lines 120 arranged in the second direction and extending in the first direction on the first side of the base substrate 1, the gate lines 120 being insulated from the data lines 110;

the plurality of data lines 110 and the plurality of gate lines 120 intersect to define a plurality of pixel units, and pixel electrodes 2 are arranged in the pixel units;

specifically, the pixel unit may further include a driving transistor TFT, a gate electrode of the driving transistor TFT may be located on the same conductive layer as the gate line, and a source electrode and a drain electrode of the driving transistor TFT may be located on the same conductive layer as the data line; the driving electrode of the inner frame area and the pixel electrode can be positioned on the same conductive layer; wherein, the grid electrode of the driving transistor TFT is connected with gate line, the source electrode and drain electrode of the driving transistor TFT are connected with data link and pixel electrode 2 separately; in the display process, the gate driving circuit transmits a scanning signal to the gate line to scan and turn on the driving transistor TFT by the scanning signal transmitted through the gate line, and then the driving transistor TFT transmits a driving signal transmitted through the data line to the pixel electrode 2.

The common electrode 3 is located on the first side of the substrate base plate 1, and the electrophoretic film 4 is located between the common electrode 3 and the substrate base plate 1.

And, the electronic paper also includes a protective film 5 to protect the common electrode 3. The electrophoretic film 4 may be formed of a colored electrophoretic particle layer in which electrophoretic particles are interposed, the electrophoretic particles being capable of swimming under the influence of an electric field formed between the pixel electrode and the common electrode.

In the display process of the display device, in the picture conversion stage, the voltage applied to the two ends of the electrophoretic film 4 by the pixel electrode 2 and the common electrode 3 controls the position of the electrophoretic particles in the electrophoretic film 4, so that the intensity of the reflected light is controlled, and the gray scale display is realized. In the picture holding stage, the potentials at the two ends of the electrophoretic film 4 are equal, so that the electrophoretic particles are kept at the positions in the electrophoretic film 4, a static picture can be perfectly held with low energy consumption, and the display of the static picture is realized.

The colors of the electrophoretic particles include black and white to form electronic paper with black and white display, and of course, the electrophoretic particles may also include other colors to form electronic paper with color display, which is not limited in this application.

The embodiment of the application provides electronic paper and a display device, wherein the electronic paper comprises a gate driving circuit, the gate driving circuit comprises a multi-stage gate scanning unit, the gate scanning unit is used for providing gate driving signals for gate lines, and the gate scanning unit comprises a plurality of transistors; at least one of the plurality of transistors is a multi-channel transistor. As can be seen from the above, in the technical scheme provided in the embodiment of the present application, the pixels are driven by the gate driving circuit disposed in the electronic paper to achieve the purpose of displaying; in addition, the grid driving circuit comprises a multi-stage grid scanning unit, wherein at least one of the transistors included in the grid scanning unit is a multi-channel transistor, and the design of the multi-channel transistor can avoid the situation that the grid voltage is too high in the grid driving circuit to cause characteristic drift, so that the high display effect of the display device is ensured.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electronic paper, the electronic paper comprising a gate driving circuit, the gate driving circuit comprising a multi-stage gate scanning unit for providing gate driving signals to gate lines, wherein the gate scanning unit comprises a plurality of transistors;

at least one of the plurality of transistors is a multi-channel transistor;

wherein the gate scanning unit includes: the device comprises an input module, a pull-up node, a pull-up control module, a pull-down node, a pull-down control module, a first coupling module, a second coupling module, an output transistor and an output end;

the input module controls the on state between a first voltage end and the pull-up node in response to a signal of a first control end, and controls the on state between a second voltage end and the pull-up node in response to a signal of a second control end, wherein the levels of signals output by the first voltage end and the second voltage end are opposite;

the pull-up control module responds to a signal of the pull-up node to control the connection state between the pull-down node and a reference voltage end, and the pull-down control module responds to a signal of the pull-down node to control the connection state between the pull-up node and the reference voltage end and between the output end and the reference voltage end respectively;

the first coupling module is configured to couple a signal at the output end to the pull-up node, the second coupling module is configured to couple a clock signal at a first clock signal end to the pull-down node, and when the pull-up control module controls the connection between the pull-down node and the reference voltage end, the signal at the pull-down node is a signal output by the reference voltage end;

a gate of the output transistor is electrically connected to the pull-up node, a first terminal of the output transistor is electrically connected to the first clock signal terminal, and a second terminal of the output transistor is electrically connected to the output terminal.

2. The electronic paper of claim 1, wherein the gate scanning unit further comprises: and the reset module responds to a signal of a reset control end and controls the connection state between a reset signal end and the pull-up node and the output end respectively.

3. The electronic paper of claim 2, wherein the transistor included in at least one of the output transistor, the input module, the pull-up control module, the pull-down control module, and the reset module is the multi-channel transistor.

4. The electronic paper of claim 1, wherein the input module comprises:

a first transistor and a second transistor;

a gate of the first transistor is electrically connected to the first control terminal, a first terminal of the first transistor is electrically connected to the first voltage terminal, and a second terminal of the first transistor is electrically connected to the pull-up node;

the gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the second voltage terminal, and the second terminal of the second transistor is electrically connected to the pull-up node.

5. The electronic paper of claim 4, wherein the pull-up control module comprises:

a third transistor;

a gate of the third transistor is electrically connected to the pull-up node, a first terminal of the third transistor is electrically connected to the reference voltage terminal, and a second terminal of the third transistor is electrically connected to the pull-down node.

6. The electronic paper of claim 5, wherein the pull-down control module comprises:

a fourth transistor and a fifth transistor;

gates of the fourth transistor and the fifth transistor are electrically connected to the pull-down node, first terminals of the fourth transistor and the fifth transistor are electrically connected to the reference voltage terminal, a second terminal of the fourth transistor is electrically connected to the pull-up node, and a second terminal of the fifth transistor is electrically connected to the output terminal.

7. The electronic paper of claim 1, wherein the first coupling module comprises a first capacitor and the second coupling module comprises a second capacitor;

a first plate of the first capacitor is electrically connected to the output terminal, and a second plate of the first capacitor is electrically connected to the pull-up node;

the first plate of the second capacitor is electrically connected to the first clock signal terminal, and the second plate of the second capacitor is electrically connected to the pull-down node.

8. The electronic paper of claim 6, wherein the gate scanning unit further comprises:

a sixth transistor;

a gate of the sixth transistor is electrically connected to a second clock signal terminal, a first terminal of the sixth transistor is electrically connected to the reference voltage terminal, and a second terminal of the sixth transistor is electrically connected to the output terminal;

the clock signal output by the second clock signal end and the clock signal output by the first clock signal end are in reverse phase.

9. The electronic paper of claim 8, wherein the gate scanning unit further comprises a reset module, the reset module comprising:

a seventh transistor and an eighth transistor;

the gates of the seventh transistor and the eighth transistor are both connected to a reset control terminal, the first terminals of the seventh transistor and the eighth transistor are both connected to a reset signal terminal, the second terminal of the seventh transistor is connected to the pull-up node, and the second terminal of the eighth transistor is connected to the output terminal.

10. The electronic paper according to claim 9, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the output transistor are all the multi-channel transistors.

11. The electronic paper according to claim 9, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all single-channel transistors, and the output transistors are all the multi-channel transistors.

12. The electronic paper according to claim 9, wherein the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the output transistor are all single-channel transistors, and wherein the first transistor and the second transistor are all the multi-channel transistors.

13. The electronic paper of claim 8, wherein the sixth transistor is the multi-channel transistor.

14. The electronic paper of claim 1, 3, 10, 11, 12, or 13, wherein the multi-channel transistor is a double-channel transistor.

15. The electronic paper of claim 14, wherein the double-channel transistor comprises:

a gate electrode;

a semiconductor layer arranged opposite to the gate electrode and insulated therefrom;

and a source electrode and a drain electrode in contact with the semiconductor layer and provided insulated from the gate electrode;

the source electrode comprises at least one source electrode strip, the drain electrode comprises a plurality of drain electrode strips which extend in the same direction as the source electrode strips, the drain electrode strips comprise first sub-drain electrode strips and second sub-drain electrode strips, the source electrode strips and the drain electrode strips are alternately arranged, and the second sub-drain electrode strips are close to the source electrode strips;

the first end parts of all the source electrode strips are connected, the second end parts of all the first sub-drain electrode strips are connected, the first end parts of two adjacent second sub-drain electrode strips are connected or the second end parts of the two adjacent second sub-drain electrode strips are connected, and the end connection regions of the two adjacent second sub-drain electrode strips are not overlapped with the source electrode strips and the first sub-drain electrode strips, wherein the first end parts of the second sub-drain electrode strips are opposite to the second end parts of the second sub-drain electrode strips, and the first end parts of the source electrode strips are opposite to the second end parts of the first sub-drain electrode strips.

16. The electronic paper according to claim 1, wherein the electronic paper comprises a display area and a non-display area, the non-display area surrounds the display area, the non-display area comprises an inner frame area and an outer frame area, the inner frame area surrounds the display area, and the outer frame area surrounds the inner frame area;

the gate driving circuit is located in the non-display area, and at least a portion of the gate driving circuit is located in the inner frame area.

17. The electronic paper of claim 16, wherein the gate driving circuit is located in the inner bezel region.

18. The electronic paper according to claim 1 or 17, wherein the gate driving circuit is located at a first end in the extending direction of the gate line; or,

the gate driving circuit comprises a first sub-gate driving circuit and a second sub-gate driving circuit, and the first sub-gate driving circuit and the second sub-gate driving circuit are respectively positioned at two ends of the gate line in the extending direction.

19. A display device, characterized in that the display device comprises the electronic paper according to any one of claims 1 to 18.

20. The display device according to claim 19, wherein the electronic paper comprises:

the data line array comprises a substrate base plate, a plurality of data lines and a plurality of data lines, wherein the data lines are arranged along a first direction and extend along a second direction, and the first direction is intersected with the second direction;

a plurality of gate lines arranged in the second direction and extending in the first direction on the first side of the substrate base plate, the gate lines being insulated from the data lines;

the data lines and the gate lines are crossed to define a plurality of pixel units, and pixel electrodes are arranged in the pixel units;

the common electrode is positioned on the first side of the substrate base plate, and the electrophoretic film is positioned between the common electrode and the substrate base plate.