CN106973246A - Solid state image sensor and its control method, image sensing system and camera - Google Patents
Solid state image sensor and its control method, image sensing system and camera Download PDFInfo
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- CN106973246A CN106973246A CN201610906392.7A CN201610906392A CN106973246A CN 106973246 A CN106973246 A CN 106973246A CN 201610906392 A CN201610906392 A CN 201610906392A CN 106973246 A CN106973246 A CN 106973246A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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Abstract
The present invention provides a kind of solid state image sensor and its control method, image sensing system and camera.The solid state image sensor includes：Pixel, it is configured to picture element signal of the generation corresponding to incident light；Amplifying circuit, it is configured to amplify the picture element signal；Circuit is set, and it is configured to the comparative result between the picture element signal that amplifies based on threshold value and by the amplifying circuit, to set the gain of the amplifying circuit；And correcting circuit, it is configured to by using the first corrected value and the second corrected value, to be corrected to the picture element signal for being exaggerated the gain set by the setting circuit.First corrected value is the value corresponding to gain error, and second corrected value is value corresponding with the amplifying circuit biasing in the gain.
Description
Technical field
The present invention relates to solid state image sensor and its control method, image sensing system and camera.
Background technology
In order to realize wide dynamic range or high speed readout, it is known that exist and apply many to the picture element signal generated by pixel
The solid state image sensor of individual gain.Japanese Unexamined Patent Publication 2005-175517 publications and Japanese Unexamined Patent Publication 2014-131147 publications are each
From disclosing following method：To the picture element signal by making the given gain of picture element signal amplification and obtaining, according to being obtained
The level of signal amplify another gain.The picture element signal amplified is converted into by data signal by A/D converter.Should
Data signal divided by value corresponding with the gain for amplifying picture element signal, and obtain gain inequality correction pixels value.
The content of the invention
As described later, only by the way that by the data signal of amplification divided by the value corresponding to gain, the pixel value of generation is possible
Without the good linearity (linearity).An aspect of of the present present invention, which is provided, is allowing hand over the amplification of amplification picture element signal
In the solid state image sensor of the gain of circuit, the technology of pixel value of the generation with the good linearity.
According to some embodiments of the present invention, solid state image sensor includes pixel, its be configured to generation correspond into
Penetrate the picture element signal of light；Amplifying circuit, it is configured to amplify the picture element signal；Circuit is set, and it is configured to be based on threshold
Comparative result between value and the picture element signal amplified by the amplifying circuit, to set the gain of the amplifying circuit；
And correcting circuit, it is configured to by using the first corrected value and the second corrected value, to set electricity by described to being exaggerated
The picture element signal of gain that road is set is corrected, and first corrected value is the value corresponding to gain error, and described the
Two corrected values are value corresponding with the amplifying circuit biasing in the gain.
According to some other embodiments of the present invention, described image sensing system includes：Solid state image sensor and correction
Circuit, the solid state image sensor includes：Pixel, it is configured to picture element signal of the generation corresponding to incident light；Amplification electricity
Road, it is configured to amplify the picture element signal, and sets circuit, and it is configured to based on threshold value and by the amplifying circuit
Comparative result between the picture element signal of amplification, to set the gain of the amplifying circuit；The correcting circuit, it is by structure
Make the first corrected value for obtaining and being used for being corrected to the picture element signal for being exaggerated the gain set by the setting circuit
With the second corrected value, wherein, first corrected value be corresponding to gain error value, second corrected value be with described
Amplifying circuit in gain biases corresponding value.
According to some other embodiments of the present invention, the control method of solid state image sensor, the solid state image sensing
Device includes：Generation is configured to corresponding to the pixel of the picture element signal of incident light and is configured to amplify the picture element signal
Amplifying circuit, the control method includes：Ratio between the picture element signal amplified based on threshold value and by the amplifying circuit
Relatively result, to set the gain of the amplifying circuit；And by using the first corrected value and the second corrected value, come to being exaggerated
The picture element signal of the gain set by the setting circuit is corrected, and first corrected value is corresponding to gain error
Value, second corrected value for it is corresponding with the amplifying circuit biasing in the gain be worth.
Description by following (referring to the drawings) to exemplary embodiment, further characteristic of the invention will be clear.
Brief description of the drawings
Fig. 1 is the block diagram for illustrating the example of the arrangement of the solid state image sensor according to first embodiment；
Fig. 2A to Fig. 2 C is the figure for illustrating the example of each circuit arrangement of Fig. 1 solid state image sensor；
Fig. 3 is the timing diagram for illustrating the picture signal read operation of Fig. 1 solid state image sensor；
Fig. 4 is the curve map for illustrating the pixel value correct operation of Fig. 1 solid state image sensor；
Fig. 5 is for illustrating the timing diagram that the correction value of Fig. 1 solid state image sensor is operated；
Fig. 6 is the figure for illustrating the example of the circuit arrangement of the first modified example of Fig. 1 solid state image sensor；
Fig. 7 is the sequential for illustrating the picture element signal read operation of the first modified example of Fig. 1 solid state image sensor
Figure；
Fig. 8 is the block diagram for illustrating the example of the arrangement of the second modified example of Fig. 1 solid state image sensor；
Fig. 9 is the figure for illustrating the example of the circuit arrangement of the second modified example of Fig. 1 solid state image sensor；
Figure 10 is the sequential for illustrating the picture element signal read operation of the second modified example of Fig. 1 solid state image sensor
Figure；
Figure 11 is the block diagram for illustrating the example of the circuit arrangement of the 3rd modified example of Fig. 1 solid state image sensor；
Figure 12 is the block diagram for illustrating the example of the arrangement of the solid state image sensor according to second embodiment；
Figure 13 is the figure for illustrating the example of the circuit arrangement of Figure 12 solid state image sensor；
Figure 14 is the curve map for illustrating the pixel value correct operation of Figure 12 solid state image sensor；
Figure 15 is for illustrating the timing diagram that the correction value of Figure 12 solid state image sensor is operated；And
Figure 16 is the figure for illustrating the example of the arrangement of the image sensing system according to 3rd embodiment.
Embodiment
Embodiments of the invention are described below with reference to accompanying drawings.Through each embodiment, identical reference is by table
Show identical element, and its repeated description will be omitted.It can as needed change and combine each embodiment.
<First embodiment>
The circuit block diagram of reference picture 1 is described to the arrangement of the solid state image sensor IM1 according to first embodiment.Solid-state
Imaging sensor IM1 includes the part shown in Fig. 1.Pel array 101 is formed by multiple pixels 100 in a matrix.Such as Fig. 1
In example, by describe pel array 101 include 4 rows and 3 row pixels 100 situation.However, the arrangement of pel array 101
Not limited to this.According to the incident light to pixel 100, picture element signal is generated in each pixel 100.Form multiple pictures with a line
Element 100 is commonly connected to single drives line.By the control signal of the operation for controlling each pixel 100 via drives line from hang down
Straight scanning circuit 103 is supplied to pixel 100.The multiple pixels 100 for forming same row are also commonly connected to single vertical line 102.
The voltage signal for being fed into each amplifying circuit 104 via corresponding vertical line 102 is referred to as vertical line signal Vvl.To
Picture element signal is from the case that each pixel 100 reads into vertical line 102, and vertical line signal Vvl is changed into and picture element signal pair
The value answered.
Each amplifying circuit 104 generates amplified signal Vamp by amplifying vertical line signal Vvl, and by amplified signal
Vamp is supplied to corresponding setting circuit 105 and corresponding comparison circuit 107.Amplifying circuit 104 is by making vertical line signal Vvl
Amplify one in multiple gains (being described later on), to generate amplified signal Vamp.When vertical line signal Vvl corresponds to pixel
During the value of signal, the amplification picture element signal of amplifying circuit 104.
Each sets circuit 105 to be compared amplified signal Vamp with predetermined threshold voltage Vsh, and is based on comparing knot
Fruit sets the gain of corresponding amplifying circuit 104.The setting for setting circuit 105 that the gain for indicating amplifying circuit 104 is set
Signal ATT is supplied to amplifying circuit 104 and corresponding memory cell 109.As an example, each of the present embodiment sets circuit
Setting signal ATT is set to L level by 105 in the case where amplified signal Vamp is less than threshold voltage Vsh, and in amplified signal
Setting signal ATT is set to H level by Vamp in the case of being more than threshold voltage Vsh.Amplifying circuit 104 is according to setting signal
ATT level, to maintain or change the gain for amplifying vertical line signal Vvl.That is, setting circuit 105 to determine whether should
Change the gain of amplifying circuit 104.Change gain while amplifying circuit 104 amplifies picture element signal.
In addition to the amplified signal Vamp from amplifying circuit 104, by contrast signal Vr from contrast signal generative circuit
106 are supplied to each comparison circuit 107.Contrast signal generative circuit 106 is according to the instruction from control circuit 113, and output is oblique
Slope signal is used as contrast signal Vr.Ramp signal is the signal changed with elapsed time with estimated rate.Comparison circuit 107
Amplified signal Vamp is compared with contrast signal Vr, and comparison signal Vcmp corresponding with comparative result is supplied to pair
The memory cell 109 answered.As an example, each comparison circuit 107 of the present embodiment is more than with reference to letter in amplified signal Vamp
Comparison signal Vcmp is set to L level in the case of number Vr, and in the case where amplified signal Vamp is less than contrast signal Vr
Comparison signal Vcmp is set to H level.For example, being used as comparison circuit 107 using comparator.
Except carrying out the self-corresponding comparison letter for setting the setting signal ATT of circuit 105 and carrying out self-corresponding comparison circuit 107
Outside number Vcmp, count signal CNT is supplied to each memory cell 109 from counter 108.According to from control circuit
113 instruction, counter 108 supplies to start counting up together with the ramp signal for starting to be carried out by contrast signal generative circuit 106,
And the count value expressed by count signal CNT is counted up through coming over time.Each memory cell 109 includes storage
Device 109S, memory 109N and memory 109D.Memory 109D keeps the setting letter supplied from corresponding setting circuit 105
Number ATT level.When each level for being maintained at comparison signal Vcmp in memory 109S and memory 109N has switched
Count value.That is, contrast signal generative circuit 106, comparison circuit 107, counter 108 and the formation of memory cell 109 will
Amplified signal Vamp is converted into the A/D change-over circuits of digital value.Memory 109N is resetting the state of corresponding pixel 100
Under, keep digital value corresponding with the amplified signal Vamp exported by amplifying circuit 104.Memory 109S is from corresponding
Pixel 100 is read in the state of picture element signal, keeps numeral corresponding with the amplified signal Vamp exported by amplifying circuit 104
Value.
For each the independent arrangement of vertical line 102 amplifying circuit 104, circuit 105, comparison circuit 107 and storage are set
Device unit 109.Digital value is sequentially read into signal processing circuit by horizontal scanning circuit 110 from multiple memory cells 109
111.Signal processing circuit 111 is generated and each picture element signal pair based on the digital value read from each memory cell 109
The data signal D answered, and data signal D is output to solid state image sensor IM1 outside.Data signal D is expressed respectively
The pixel value of individual pixel 100.Circuit 113 is controlled by the way that control signal (being described later on) is supplied into solid state image sensor IM1
Each part, to control the operation of each part.
Next, described Fig. 2A, Fig. 2 B and Fig. 2 C are respectively referred to the pixel 100 in Fig. 1, amplifying circuit 104 and
The example of the circuit arrangement of circuit 105 is set.Fig. 2A describes the example of the circuit arrangement of pixel 100.Pixel 100 includes photoelectricity
Diode PD, amplifying transistor MSF, transfer transistor MTX, reset transistor MRS and selection transistor MSEL.The pole of photoelectricity two
Pipe PD produces electric charge corresponding with the incident light to pixel 100, and accumulates these electric charges.Supplied according to from vertical scanning circuit 103
Respective control signal φ PTX, control signal φ PRS and control signal φ PSEL, transfer transistor MTX, the reset crystalline substance given
Body pipe MRS and selection transistor MSEL are controlled as in the conduction state or nonconducting state.Amplifying transistor MSF grid
It is connected to floating diffusion FD.Amplifying transistor MSF source electrode is connected to vertical line 102 via selection transistor MSEL.Work as control
When signal psi PRS changes into H level, reset transistor MRS is changed to conducting state, and floating diffusion FD is connected to supply voltage
VDD, and floating diffusion FD voltage is reset.Reset to floating diffusion FD voltage is referred to as the reset to pixel 100.
When control signal φ PTX change into H level, transfer transistor MTX is changed in conducting state, and photodiode PD
The electric charge of accumulation is sent to floating diffusion FD.When control signal φ PSEL change into H level, selection transistor MSEL is changed
Conducting state is changed to, and electric current is fed into amplifying transistor MSF via vertical line 102 from current source (not shown).This makes
Signal (that is, picture element signal) that must be based on the voltage from floating diffusion FD is read out to vertical line 102.
Fig. 2 B describe the example of the circuit arrangement of amplifying circuit 104.Amplifying circuit 104 includes inverting amplifier AMP, electricity
Container CIN, CFB1 and CFB2, and switch Sw1 and switch Sw2.Vertical line signal Vvl is fed into instead via capacitor CIN
Phase amplifier AMP input terminal.Between inverting amplifier AMP input terminal and lead-out terminal, switch Sw1, capacitor
CFB1 and the switch Sw2 and capacitor CFB2 that are connected in series are connected in parallel.Capacitor CFB1 is grasped as feedback capacity
Make.Switch Sw2 on/off is controlled by setting signal ATT and control signal φ FB2 logical sum.When the logical sum is H
During level, switch Sw2 is switched on, and capacitor CFB2 is operated as feedback capacity.When control signal φ ARS are H electricity
Usually, switch Sw1 is switched on, and makes the resetting charge accumulated in capacitor CFB1 and capacitor CFB2.As an example, this reality
The capacitance for applying capacitor CIN, CFB1 and CFB2 of example is respectively C, C and 3C.Therefore, if switch Sw2 disconnects, amplification electricity
The gain on road 104 is arranged to 1 times, and if switch Sw2 is connected, then the gain of amplifying circuit 104 is arranged to 4 times.It is anti-phase
Amplifier AMP outputs are used as amplified signal Vamp by the signal for making the gain of vertical line signal Vvl amplification settings and obtaining.
According to the gain to be set in amplifying circuit 104, suitably to set each electric capacity CIN, CFB1 and CFB2 capacitance.
As an example, by the transistor M1 and M2 as nmos pass transistor and the transistor M3 and M4 as PMOS transistor
The NMOS common source amplifying circuits of formation, to realize the inverting amplifier AMP of the present embodiment.Transistor M1 amplifies as common source
Transistor is operated.Transistor M2 is operated as common gate amplifying transistor.In addition, transistor M3 and M4 is common for common source
Grid connect and form constant current load.DC bias voltages Vbn1, Vbp1 and Vbp2 be respectively supplied to transistor M2, M3 and
M4 grid.The operating point (operating point) of transistor is determined by these respective DC biass.
Fig. 2 C describe the example for the circuit arrangement for setting circuit 105.Circuit 105 is set to be latched including comparator CMP1, D
Circuit DL and AND-gate.Amplified signal Vamp is supplied to comparator CMP1 non-inverting input terminal.Threshold voltage Vsh is supplied
It is given to comparator CMP1 reversed input terminal.Comparator CMP1 determines that amplified signal Vamp and threshold voltage Vsh size is closed
System, and by with determining that the corresponding signal of result is supplied to D latch cicuits DL D terminals.Comparator CMP1 is in amplified signal
Vamp exports L level signal in the case of being less than threshold voltage Vsh, and is more than threshold voltage Vsh feelings in amplified signal Vamp
H level signal is exported under condition.D latch cicuits DL keeps being supplied to D terminals according to the control signal φ DL of E terminals are supplied to
The level of signal, and the level kept is supplied to the input terminal of AND-gate.Control signal φ DLO are supplied to AND-gate
Other input terminals.When control signal φ DLO are H level, AND-gate will be made by the signal of the D latch cicuits DL level kept
For setting signal ATT, the outside that circuit 105 is set is output to.In addition, when control signal φ DLO are L level, AND-gate is by L
Level signal is output to the outside for setting circuit 105 as setting signal ATT.
Next, reference picture 3 to Fig. 5 to be described to solid state image sensor IM1 operation.By controlling circuit 113 to control
The operation of solid state image sensor IM1 processed each part, to carry out solid state image sensor IM1 operation.By controlling circuit
113 control vertical scanning circuits 103 to carry out the operation of each pixel 100.By controlling the controlled level scanning circuit of circuit 113
110 digital value to carry out from each memory cell 109 to signal processing unit 111 is read.Solid state image sensor IM1 master
Carry out picture element signal read operation, correction value operation and calculated for pixel values operation.Picture element signal read operation is from each
Individual pixel reads picture element signal and digital value corresponding with the picture element signal is maintained at into the behaviour in corresponding memory cell 109
Make.Correction value operation is to calculate corrected value to correct the operation of the digital value.Calculated for pixel values operation is to correct the numeral
Value is to calculate the operation of pixel value.Solid state image sensor IM1 is operated according to correction value, picture element signal read operation and
The order of calculated for pixel values operation is operated.These operations are carried out for each pixel 100., will in following part
Order according to picture element signal read operation, calculated for pixel values operation and correction value operation is described.
The timing diagram of reference picture 3 is described to picture element signal read operation.Fig. 3, which is described, to be used for from single pixel 100 1
The secondary operation for reading picture element signal.For forming multiple pixels 100 of same a line while carrying out the operation described in Fig. 3.Solid-state
Imaging sensor IM1 carries out the behaviour described in Fig. 3 by each pixel on multiple pixel columns to forming pel array 101
Make, picture element signal is read from each pixel of pel array 101.Through the cycle shown in Fig. 3, vertical scanning circuit 103
The control signal φ PSEL for being fed into picture element signal read operation object pixel 100 maintain H level, and are fed into it
His the control signal φ PSEL of pixel 100 maintain L level.
When starting picture element signal read operation, vertical scanning circuit 103 is arrived by temporarily changing control signal φ PRS
H level resets pixel 100.Therefore, corresponding vertical line will be read into the corresponding signal of pixel 100 under reset state
102.The signal is referred to as pixel reset signal.When pixel reset signal is read into vertical line 102, vertical line signal Vv1
It is changed into value corresponding with the signal.Circuit 113 is controlled to arrive H level by temporarily changing control signal φ ARS and φ FB2, with
The reset of pixel concurrently, to make the resetting charge accumulated in capacitor CFB1 and CFB2.It will be controlled in vertical scanning circuit 103
Signal psi PRS changes to after L level, and control circuit 113, which changes control signal φ ARS and φ FB2, arrives L level.
During aforesaid operations, control signal φ DLO are set to L level by control circuit 113.As a result, by setting circuit
The setting signal ATT of 105 outputs changes into L level.Because both setting signal ATT and control signal φ FB2 are L level,
Therefore the switch Sw2 of amplifying circuit 104 is disconnected, and is connected to the capacitance of inverting amplifier AMP feedback condenser and is changed
For C.Because the capacitance for the input capacitor for being connected to inverting amplifier AMP is also C, therefore the gain quilt of amplifying circuit 104
It is set to 1 times.
Next, contrast signal generative circuit 106 is initially supplied ramp signal according to the instruction from control circuit 113
It is used as contrast signal Vr.In other words, contrast signal generative circuit 106 starts to change contrast signal Vr's with elapsed time
Value.Meanwhile, counter 108 is started from scratch according to the instruction from control circuit 113 and counts up output count value.Work as reference
Signal Vr exceed amplified signal Vamp and comparison signal Vcmp from L level be switched to H level when, memory 109N is maintained at this
Count value of the time point from counter 108.The count value corresponds to being obtained by making pixel reset signal amplify 1 times of gain
Amplified signal Vamp carry out A/D conversions and the digital value that obtains.Hereinafter, the digital value will be referred to as N.
Then, temporarily control signal φ PTX are changed arrive H level when, vertical scanning circuit 103 is by photodiode PD
The electric charge of middle accumulation is sent to floating diffusion FD.As a result, the picture element signal from pixel 100 is read into vertical line 102, and
Vertical line signal Vv1 changes into value corresponding with the picture element signal.Δ Vvl is represented and is being used the resetting time conduct of pixel 100
The knots modification (that is, the difference between picture element signal and pixel reset signal) of vertical line signal Vv1 at the time point of benchmark.Δ
Vvl has value corresponding with the incident light quantity to pixel 100.Amplified signal Vamp changes with vertical line signal Vv1 change
Become.The gain that Δ Vamp1 is expressed in amplifying circuit 104 is arranged to the knots modification of the amplified signal Vamp in the state of 1 times.
Here, threshold voltage Vsh be set equal to or out-put dynamic range less than amplifying circuit 104 1/4.Therefore, solid-state figure
It is less than threshold in the case where amplified signal Vamp is equal to or more than threshold voltage Vsh and in amplified signal Vamp as sensor IM1
Different operations are carried out in the case of threshold voltage Vsh.It is described below by making picture element signal amplify 1 times of gain and putting for obtaining
Big signal Vamp is more than threshold voltage Vsh situation.
After it have passed through the scheduled time control signal φ PTX are changed into L level from vertical scanning circuit 103, control
Control signal φ DL are temporarily changed into H level by circuit 113 processed.Because amplified signal Vamp is more than threshold voltage Vsh, therefore will
H level signal is maintained in D latch cicuits DL.Next, control signal φ DLO are changed into H level by control circuit 113.If
The signal kept in the output D latch cicuits of circuits 105 DL, and setting signal ATT is changed into H level.As a result, amplifying circuit
104 switch Sw2 is switched on, and capacitor CFB2 is connected to inverting amplifier AMP, and is connected to the anti-of inverting amplifier AMP
The capacitance of feedforward capacitor changes into 4C.Because the capacitance for the input capacitor for being connected to inverting amplifier AMP is C, therefore
The gain of amplifying circuit 104 is arranged to 1/4 times.Amplified signal Vamp value changes also with the setting.Δ Vamp2 is represented
It is arranged to the knots modification of the amplified signal Vamp in the state of 1/4 times in the gain of amplifying circuit 104.
Then, solid state image sensor IM1 with to the amplified signal Vamp by amplifying pixel reset signal and obtaining
A/D conversion identical modes are carried out, to carry out A/D conversions to the amplified signal Vamp by amplifying picture element signal and obtaining.Deposit
Reservoir 109S keeps the digital value that the amplified signal Vamp by amplifying picture element signal and obtaining is carried out A/D conversions and obtained.
Hereinafter, the digital value will be referred to as S.Then, memory 109D keeps setting signal ATT level.Finally, circuit is controlled
Control signal φ DLO are changed into L level by setting signal ATT by 113 changes into L level, to continue to move to next line reading
Go out.
By aforesaid operations, the level of the setting signal ATT when carrying out A/D conversions to picture element signal is maintained at storage
In device 109D, the digital value N for representing amplification pixel reset signal is maintained in memory 109N, and amplify pixel by representing
The digital value S of signal is maintained in memory 109S.As in the examples described above, change when by the gain of amplifying circuit 104 from 1 times
For 1/4 times when, H level setting signal ATT be maintained in memory 109D, and picture element signal will be represented be exaggerated 1/4 times
The digital value of gain is maintained in memory 109S.On the other hand, when by making picture element signal amplify 1 times of gain and putting for obtaining
When big signal Vamp is less than threshold voltage Vsh, the gain of amplifying circuit 104 is maintained at 1 times.In this case, by L level
Setting signal ATT is maintained in memory 109D, and the digital value S for representing picture element signal and being exaggerated 1 times of gain is maintained at
In memory 109S.When by the gain of amplifying circuit 104 from when changing into 1/4 times for 1 times and when gain is maintained at 1 times,
The digital value N for representing pixel reset signal and being exaggerated 1 times of gain is maintained in memory 109N.
Next, will description calculated for pixel values operation.Signal processing circuit 111 is based on keeping in memory cell 109
Digital value calculate pixel value.L level setting signal ATT is maintained to the situation in memory 109D by description first.
In this case, the digital value S for representing picture element signal and being exaggerated 1 times of gain is maintained in memory 109S, and will represented
The digital value N that pixel reset signal is exaggerated 1 times of gain is maintained in memory 109N.Therefore, signal processing circuit 111 passes through
Numeral CDS (Correlated Double Sampling, correlated-double-sampling) processing is carried out to calculate pixel value.Particularly, believe
Number process circuit 111 calculates S-N and the value is set into pixel value.
Next, H level setting signal ATT to be maintained to the situation in memory 109D by description.In this case,
The digital value S for representing picture element signal and being exaggerated 1/4 times of gain is maintained in memory 109S, and pixel-reset letter will be represented
The digital value N for number being exaggerated 1 times of gain is maintained in memory 109N.Therefore, signal processing circuit 111 is only by using numeral
Value S and digital value N, which simply carry out digital CDS processing, can not calculate correct pixel value.Reference picture 4 is explained to the reason
By.
The abscissa of curve map in Fig. 4 represents vertical line signal Vvl knots modification Δ Vvl.Curve map in Fig. 4 it is vertical
Coordinate represents digital value.Knots modification Δ Vvl corresponds to the incident light quantity of pixel 100.When vertical line signal Vvl is multiple with pixel
During the corresponding value of signal of position, knots modification Δ Vvl vanishing.
The knots modification Δ Vvl that the scope that the gain that line 401 is represented in amplifying circuit 104 is arranged to 1 times includes with it is logical
The relation crossed between the data signal D1 that following formula (1) is calculated,
D1=S-N ... (1)
Because both digital value S and digital value N are the life in the state of the gain of amplifying circuit 104 is arranged to 1 times
Into value, therefore suitably represent the data signal D1 of incident light quantity by carrying out numeral CDS processing to obtain.If for example,
Knots modification Δ Vvl (incident light quantity) is zero, then data signal D1 also changes into zero.When the gain of amplifying circuit 104 is arranged to 1
Times when (that is, when L level signal is maintained in memory 109D), the output digit signals D1 conducts of signal processing circuit 111
Above-mentioned data signal D.
The knots modification Δ Vvl that the scope that the gain that line 402 is represented in amplifying circuit 104 is arranged to 1/4 times includes with
Relation between the data signal D2 calculated by following formula (2),
D2=4 (S-N) ... (2)
Due to handling the inverse (4) that the S-N obtained has been multiplied by gain, therefore the slope and line of line 402 by digital CDS
401 slope matched.However, due to the feedthrough of switch Sw2 for generating etc. when connecting capacitor CFB2, therefore it is exaggerated 1 times
The pixel reset signal of gain has different biasings each other with the picture element signal for being exaggerated 1/4 times of gain.Therefore, such as Fig. 4 institutes
Show, in the Δ Vvl values that handoff gain is set, the offset alpha between generation data signal D2 and data signal D1.
Therefore, when the gain of amplifying circuit 104 is arranged to 1/4 times, signal processing circuit 111 is counted by following formula (3)
Data signal D3 is calculated,
D3=4 (S-N)-α ... (3)
The knots modification Δ Vvl that the scope that the gain that line 403 is represented in amplifying circuit 104 is arranged to 1/4 times includes with
Relation between the data signal D3 calculated according to above formula (3).As shown in figure 4, line 403 is with good relative to line 401
The linearity.When the gain of amplifying circuit 104 is arranged to 1/4 times (that is, when H level signal is maintained at into memory 109D
When), the output digit signals D3 of signal processing circuit 111 is used as data signal D.
Here, when the gain of amplifying circuit 104 is summarised as into G, signal processing circuit 111 is calculated by following formula (4)
Data signal D,
D=βG×(S-N)-αG ...(4)
Wherein, αGFor the corresponding bias correction value of biasing with amplifying circuit 104, and βGFor the gain with amplifying circuit 104
Corresponding gain correcting value.For each gain, α is setGAnd βG, and by αGAnd βGIt is maintained in memory 112.Show above-mentioned
In example, α1=0, α1/4=α, β1=1 and β1/4=4.In the present embodiment, it is exaggerated 1 times of gain due to representing pixel reset signal
Digital value N be used for digital CDS processing, therefore α1=0.Operate and (be described later on) by correction value to calculate α.
βGFor the inverse of gain.When manufacturing solid state image sensor IM1, based on being connected to inverting amplifier AMP capacitance logic meters
Calculate βG, and by βGStore in memory 112.The generation of signal processing circuit 111 represents the number of the pixel value calculated in the above described manner
Word signal D, and data signal D is output to solid state image sensor IM1 outside.As noted previously, as signal transacting is electric
Road 111 corrects the digital value S for representing picture element signal, therefore signal processing circuit 111 can be referred to as correcting circuit.
The timing diagram of reference picture 5 is described to correction value operation.Fig. 5 is described to be counted for an amplifying circuit 104
Calculate the operation of corrected value.The corrected value is used for the multiple pixels 100 for being commonly connected to corresponding amplifying circuit 104.Pel array
101 include being generated by not helping image and being used to calculate one or more rows that the pixel 100 of corrected value is formed.Through Fig. 5
Shown cycle, the control signal φ PSEL that vertical scanning circuit 103 is fed into correction value pixel 100 maintain H electricity
Put down, and be fed into the control signal φ PSEL of other pixels 100 and maintain L level.In addition, through the cycle shown in Fig. 5, hanging down
The control signal φ PRS that straight scanning circuit 103 is fed into correction value pixel 100 maintain H level, and by control signal
φ PTX maintain L level.Therefore, through the cycle shown in Fig. 5, supply pixel reset signal is used as vertical line signal Vvl.
By the operation carried out in cycle H 1 and the operation carried out in subsequent cycle H 2, to form correction value
Operation.In cycle H 1, control circuit 113 with the identical mode in picture element signal read operation, protected by digital value N1
Digital value S1 is maintained in memory 109S after holding in memory 109N.In cycle H 1, by controlling circuit 113 will
Control signal φ DLO are set to L level to export L level setting signal ATT.Therefore, both digital value N1 and digital value S1 generation
The amplified signal Vamp that table is obtained by 1 times of gain.The reading number value N1 of signal processing circuit 111 and digital value S1, and should
Readout is maintained in memory 112.
Next, in cycle H 2, control circuit 113 by carry out with cycle H 1 identical handle, by numeral
Digital value S2 is maintained in memory 109S by value N2 after being maintained in memory 109N.However, control circuit 113 is in generation
Before digital value S2, by switching to H level that the gain of amplifying circuit 104 is set into 1/4 times control signal φ FB2.
Therefore, digital value N2 represents the amplified signal Vamp obtained by 1 times of gain, and digital value S2 is represented and obtained by 1/4 times of gain
The amplified signal Vamp obtained.The reading number value N2 of signal processing circuit 111 and digital value S2, and the readout is maintained at storage
In device 112.
Next, signal processing circuit 111 calculates bias correction value α by following formula (5)1/4,
α1/4=(S2-N2)-(S1-N1) ... (5)
Obtained here, digital value N1 and digital value N2 are each represented by making pixel reset signal amplify 1 times of gain
Amplified signal Vamp value.Digital value S1 is represented to be obtained by the way that the picture element signal in Δ Vvl=0 is amplified into 1 times of gain
Amplified signal Vamp value.Digital value S2 is represented to be obtained by the way that the picture element signal in Δ Vvl=0 is amplified into 1/4 times of gain
Amplified signal Vamp value.Therefore, the α obtained by formula (5)1/4Matched with the α shown in Fig. 4.
As described above, according to this embodiment, it can removing feedthrough etc. caused by the gain for changing amplifying circuit 104
The biased error caused, and the solid state image sensor with good linearity can be realized.In the corrected value of the present embodiment
Calculate in operation, digital value S1 and digital value S2 are calculated based on pixel reset signal.However, instead of these values, can from
Other different voltage sources of pixel 100, amplifying circuit 104 is supplied to by the test signal of predetermined value.Can be in identical semiconductor
Solid state image sensor IM1 each part is realized on substrate.Alternatively, solid state image sensor IM1 can left
Remainder where semiconductor substrate other semiconductor substrates on realize signal processing circuit 111.
<First modified example of first embodiment>
Reference picture 6 and Fig. 7 are described to solid state image sensor IM1 the first modified example.In the first modified example, set
The arrangement of circuit 105 is different.The setting circuit 105 of first modified example have amplified signal Vamp slicings (clip) to be equal to or
Less than threshold voltage Vsh function.Fig. 6 describes the example of the circuit arrangement of the setting circuit 105 according to the first modified example.
Circuit 105 is set to include the transistor M5 and transistor M6 and crystalline substance as nmos pass transistor as PMOS transistor
Body pipe M7.Transistor M5 source electrode is connected to the lead-out terminal of amplifying circuit 104, and transistor M5 slicing amplified signals
Vamp.The threshold voltage Vsh of clipping operation is determined by the voltage Vclp for being input to transistor M5 grid.DC is biased into Vbn2
Transistor M6 grid is input to, and when transistor M5 carries out clipping operation, constant current is supplied to transistor M5's
Drain electrode.Transistor M5 drain electrode is also connected to phase inverter and transistor M7 grid.Transistor M7 source electrode is grounding to GND electricity
Gesture, and transistor M7 drain electrode is connected to the lead-out terminal of amplifying circuit 104.NOR processing is being carried out with control signal φ DRS
Afterwards, the output from phase inverter is input into RS latch cicuits LCH S terminals.Control signal φ DRS are input into as RS
The R terminals of latch cicuit LCH other input terminals.Therefore, when control signal φ DRS change into H level, due to R terminals
It is arranged to H level and S terminals is arranged to L level, therefore RS latch cicuits LCH is reset.From RS latch cicuits LCH
Output be changed into, from the output for setting circuit 105, and exporting setting signal ATT.
If amplified signal Vamp is less than threshold voltage Vsh, transistor M5 is in nonconducting state.Because DC biases quilt
Transistor M6 grid is input to, therefore transistor M7 grid voltage is arranged to almost GND level.Therefore, transistor M7
It is arranged to nonconducting state.In this case, transistor M5 and transistor M7 are both in nonconducting state and not
Influence inverting amplifier AMP operation.On the other hand, if amplified signal Vamp exceedes threshold voltage Vsh, transistor M5 changes
It is changed into conducting state.In this case, transistor M7 grid voltage rises, and transistor M7 changes into conducting state.
As a result, it is also fed with from the transistor M3 and transistor M4 inverting amplifier AMP supplied load current to setting circuit 105,
And load current is changed into the clipping state that amplified signal Vamp is hardly increased beyond threshold voltage Vsh.
The timing diagram of reference picture 7 is described to the picture element signal read operation according to the first modified example.According to the first modification
The correction value operation and calculated for pixel values operation of example can be operated and pixel with the correction value of above-mentioned first embodiment
It is identical that value calculates operation.According to the picture element signal read operation of the first modified example with being read according to the picture element signal of first embodiment
The difference of operation is：Circuit 113 is controlled to setting circuit 105 to supply control signal φ DRS, instead of control signal φ DL and
φDLO.Remaining point can be identical with first embodiment.
When start picture element signal read operation when, control circuit 113 temporarily by control signal φ DRS change into H level with
Reset RS latch cicuits LCH.As a result, circuit 105 is set to export L level setting signal ATT.Then, with first implement
In example after identical processing, read picture element signal from pixel 100 and change to corresponding vertical line 102, and vertical line signal Vvl
Change to the value corresponding to picture element signal.
If amplified signal Vamp is less than threshold voltage Vsh, transistor M7 grid voltage is in almost GND level.
Therefore, because L level signal continues to be input into RS latch cicuits LCH S terminals, therefore setting signal ATT maintains L level.
On the other hand, if amplified signal Vamp reaches threshold voltage Vsh, transistor M7 grid voltage also reaches the threshold of phase inverter
Value.As a result, the input of S terminals to RS latch cicuits LCH is inverted to H level.With and this, RS latch cicuits LCH output H
Level setting signal ATT simultaneously maintains this state.When setting signal ATT changes into H level, the gain quilt of amplifying circuit 104
1/4 times is changed into, amplified signal Vamp becomes less than or equal to threshold voltage Vsh, and cancels slicing.Now, due to setting
Signal ATT is maintained at H level, therefore vertical line signal Vvl is exaggerated 1/4 times of gain.Fully stabilize (settle)
After amplified signal Vamp, handle with the processing identical in first embodiment, and generate digital value S.
It can be obtained in the first modified example and first embodiment identical effect.In addition, in the first modified example, due to
The slicing function of circuit 105 is set, therefore amplified signal Vamp will go above threshold voltage Vsh.Therefore, threshold voltage Vsh
The output saturation level of amplifying circuit 104 is can be configured to, and the dynamic model of amplifying circuit 104 can be efficiently used
Enclose.Note, if amplified signal Vamp changes into the value close to clip voltage, amplified signal Vamp will be greatly by crystal
Pipe M5 influence and can not be with high-precision output signal.Therefore, except from when corresponding to the vertical line signal Vvl of picture element signal
Played when being input into amplifying circuit 104 when set circuit 105 be determined when during outside, setting circuit 105 can be made
Slicing disabler.If for example, control circuit 113 is before picture element signal is read out to vertical line 102 and is setting
Circuit 105 rises voltage Vclp after being determined, then can obtain the digital value with higher precision.
<Second modified example of first embodiment>
Reference picture 8 to Figure 10 is described to the solid state image sensing as solid state image sensor IM1 the second modified example
Device IM2.As shown in figure 8, according to the solid state image sensor IM2 of the second modified example it is different from solid state image sensor IM1's it
Be in：Including setting circuit 805, instead of setting circuit 105 and comparison circuit 107.Remaining point can be with solid state image sensing
Device IM1's is identical.Reference picture 9 is described to the example of the circuit arrangement of setting circuit 805.As shown in figure 9, setting circuit 805
The arrangement changed jointly including the setting circuit 105 and comparison circuit 107 shown in Fig. 1.
Next, the timing diagram of reference picture 10 to be described to the picture element signal read operation according to the second modified example.According to
The correction value operation and calculated for pixel values operation of second modified example can be with the correction values in above-mentioned first embodiment
Operation is identical with calculated for pixel values operation.According to the picture element signal read operation of the second modified example and the picture according to first embodiment
The difference of plain signal read operation is：The contrast signal Vr supplied by contrast signal generative circuit 106 is different.Remaining point
It can be basically the same as those in the first embodiment.After digital value N is maintained in memory 109N, control circuit 113 will be by reference
The value for the contrast signal Vr that signal generating circuit 106 is supplied changes into threshold voltage Vsh.As a result, by setting circuit 805 is come to putting
Big signal Vamp and threshold voltage Vsh is compared, and comparative result is output as into setting signal ATT.
<3rd modified example of first embodiment>
Reference picture 11 is described to the solid state image sensor IM3 as solid state image sensor IM1 the 3rd modified example.
As shown in figure 11, existed according to the solid state image sensor IM3 of the 3rd modified example and solid state image sensor IM1 difference
In：Including counter 1108 and memory cell 1109, instead of counter 108 and memory cell 109.Remaining point can be with consolidating
State imaging sensor IM1's is identical.
Individual count device 1108 has up/down tally function.Counter 1108 is arranged for each pixel column.When right
When carrying out A/D conversions by the amplified signal Vamp for amplifying pixel reset signal and obtaining, counter 1108 is according to from control
The instruction of circuit 113, starts to count downwards from zero.As a result, the symbol of the digital value N by changing first embodiment is obtained
Value be maintained in counter 1108.Next, when to the amplified signal Vamp progress A/D by amplifying picture element signal and obtaining
During conversion, counter 1108 is started according to the instruction from control circuit 113 using the value (that is ,-N) of holding as initial value
Count up.Counter 1108 exports value corresponding with the S-N in first embodiment in the time point of the A/D conversion ends.Each
The memory 1109V of memory cell 1109 keeps the value.Signal processing circuit 111 is by using in each memory 1109V
The value (S-N) of holding, to carry out above-mentioned calculated for pixel values operation.In addition, correction value operation in, due to S1-N1 and
The corresponding values of S2-N2 are maintained in memory 1109V, therefore signal processing circuit 111 calculates corrected value using these values.
<Second embodiment>
Reference picture 12 to Figure 15 is described to the solid state image sensor IM4 according to second embodiment.Solid state image sensing
Device IM4 and solid state image sensor IM1 difference are：Also include testing signal generation circuit 1201.Test signal is given birth to
Into each supply test signal of circuit 1201 into multiple vertical lines 102.In the first embodiment, using based on feedback capacity
The value (4) that the capacitance logical calculated of device goes out, is used as gain correcting value β1/4.However, due to being difficult to accurately control gain, because
Even if the gain of this amplifying circuit 104 is arranged to 1/4, actual amplified signal Vamp may also be exaggerated the gain of different value.
The abscissa of curve map in Figure 14 represents vertical line signal Vvl knots modification Δ Vvl.Curve map in Figure 14
Ordinate represents digital value.Knots modification Δ Vvl corresponds to the incident light quantity of pixel 100.When vertical line signal Vvl is and pixel
During the corresponding value of reset signal, knots modification Δ Vvl vanishing.
So that with the identical mode of line 401, the gain that line 1401 represents in amplifying circuit 104 is arranged in 1 times of scope
Including knots modification Δ Vvl and the data signal D1 that is calculated according to above formula (1) between relation.
The knots modification Δ Vvl that the scope that the gain that line 1402 is represented in amplifying circuit 104 is arranged to 1/4 times includes with
Relation between the data signal D2 calculated according to above formula (2).Gain is multiplied by due to handling the S-N obtained by digital CDS
Inverse (4), therefore the slope of line 1402 matches with the slope logic of line 1401.However, the slope of these lines is missed due to gain
Difference and may mismatch.In this case, even if such as having carried out bias correction in the embodiment in figure 1, data signal D also will
Without the good linearity.Therefore, the signal processing circuit 111 of second embodiment is not by logical value but based on actual
The amplified signal Vamp of upper acquisition, to determine the gain correcting value β of above-mentioned formula (4)1/4。
In one example, signal processing circuit 111, which calculates correction coefficient b, is used for correcting gain corrected value, and sets logical
The value for making the inverse (4) of the logic gain value be multiplied by correction coefficient b and obtain is crossed, gain correcting value β is used as1/4.Particularly,
Signal processing circuit 111 calculates correction coefficient b so that the line 1403 for the data signal D4 that expression is calculated by following formula (6)
Slope is by the slope matched with line 1401.
D4=4b (S-N) ... (6)
Correction coefficient b computational methods will be described later.
Then, signal processing circuit 111 from D4 by subtracting bias correction value α, to calculate digital value.That is, at signal
Reason circuit 111 calculates data signal D5 by following formula (7),
D5=4b (S-N)-α ... (7)
The knots modification Δ Vvl that the scope that the gain that line 1404 is represented in amplifying circuit 104 is arranged to 1/4 times includes with
Relation between the data signal D5 calculated according to above formula (7).As shown in figure 14, line 1404 has good relative to line 1401
The linearity.When the gain of amplifying circuit 104 is arranged to 1/4 times (that is, when H level signal is maintained at corresponding storage
During device 109D), the output digit signals D5 of signal processing circuit 111 is used as above-mentioned data signal D.
Reference picture 13 is described to the example of the circuit arrangement of testing signal generation circuit 1201.Testing signal generation circuit
1201 include the multiplexer MX1 controlled by control signal φ TS1, the multiplexer controlled by control signal φ TS2
MX2 and be connected to each row vertical line 102 transistor M8.Each transistor M8 is nmos pass transistor.Each transistor M8
Source electrode be connected to vertical line 102, and each transistor M8 drain electrode is connected to power supply.Each transistor M8 is according to by multichannel
The grid voltage of converter MX2 controls, to control the voltage of vertical line 102.Voltage V5 and the output from multiplexer MX1
It is fed into multiplexer MX2.Voltage V3 and voltage V4 are fed into multiplexer MX1.Multiplexer MX1 is in control
Output voltage V3 when signal psi TS1 is L level, and when control signal φ TS1 are H level output voltage V4.In voltage V3 quilts
In the case of the grid for being supplied to corresponding transistor M8, supplied from testing signal generation circuit 1201 to each vertical line 102
Signal be referred to as the first test signal.In the case where voltage V4 is fed into corresponding transistor M8 grid, by testing
The signal that signal generating circuit 1201 is supplied to each vertical line 102 is referred to as the second test signal.First test signal and
Two test signals have value different from each other.
When control signal φ TS2 change into L level, voltage V5 is simultaneously supplied to by multiplexer MX2 selection voltage V5
Each transistor M8 grid.On the other hand, when control signal φ TS2 change into H level, multiplexer MX2 selections come
Each transistor M8 grid is supplied to from multiplexer MX1 output and by voltage V3 or voltage V4.In correction value
In operation, control signal φ TS2 change into H level, and will voltage corresponding with voltage V3 or voltage V4 to be supplied to each vertical
Line 102, is used as vertical line signal Vvl.In picture element signal read operation, control signal φ TS2 change into L level, and root
Carry out slicing each vertical line 102 according to voltage V5.Testing signal generation circuit 1201, which has, to be prevented in locally increase picture element signal electricity
The slicing function that excess voltage in each vertical line 102 usually generated declines, and obtain stain (smear) suppression effect
Really.
The timing diagram of reference picture 15 is described to correction value operation.Operated in the correction value of second embodiment
In, also calculate gain correcting value and bias correction value.Figure 15 describes the corrected value for calculating single amplifying circuit 104
Operation.The corrected value is used for the multiple pixels 100 for being commonly connected to amplifying circuit 104.Through the cycle shown in Figure 15, vertically sweep
The control signal φ PSEL that scanning circuit 103 is fed into all calculating pixels 100 maintain L level.
By the operation carried out in continuous cycles H1 into cycle H 4, to form correction value operation.In each cycle
The operation of progress is identical with the operation carried out in Fig. 5 cycle H 1.Therefore, difference will be described mainly.
It is the state that the first test signal and its gain are arranged to 1 times in vertical line signal Vvl in cycle H 1
Under, generate digital value N1.Then, it is the state that the first test signal and its gain are arranged to 1 times in vertical line signal Vvl
Under, generate digital value S1.In cycle H 2, in vertical line signal Vvl be the first test signal and its gain is arranged to 1 times
In the state of, generate digital value N2.Then, it is the first test signal and its gain is arranged to 1/4 in vertical line signal Vvl
In the state of times, digital value S2 is generated.It is the first test signal and its gain quilt in vertical line signal Vvl in cycle H 3
It is set in the state of 1 times, generation digital value N3.Then, it is the second test signal and its gain quilt in vertical line signal Vvl
It is set in the state of 1 times, generation digital value S3.In cycle H 4, vertical line signal Vvl be the first test signal and its
Gain is arranged in the state of 1 times, generation digital value N4.Then, vertical line signal Vvl be the second test signal and its
Gain is arranged in the state of 1/4 times, generation digital value S4.Signal processing circuit 111 is by these digital values suitably from right
The memory cell 109 answered reads into memory 112.
Signal processing circuit 111 calculates correction coefficient b, gain correcting value β by following formula (8) to formula (10)GAnd biasing
Correction value alphaG,
B={ (S3-N3)-(S1-N1) }/{ (S4-N4)/G- (S2-N2)/G } ... (8)
βG=b/G ... (9)
αG=b (S2-N2)/G- (S1-N1) ... (10)
Wherein, G (1/4 in above-mentioned example) is the change gain set in amplifying circuit 104.Signal processing circuit
111 by the gain correcting value β calculated by this wayGWith bias correction value αGIt is stored in memory 112.Instead of formula (10),
Signal processing circuit 111 can calculate bias correction value α by formula (11)G,
αG=b (S4-N4)/G- (S3-N3) ... (11)
In the present embodiment, amplified signal Vamp can be based on, is realized by correcting the gain of amplifying circuit with more
The solid state image sensor of the favourable linearity.First modified example of first embodiment to the 3rd modified example can be implemented with second
Example combination.
In each above-described embodiment, it has been described that by calculating the corrected value for each pixel column come correction pixels
The situation of value.Instead, average value or median can be calculated by the corrected value calculated for each pixel column, and should
Value can be commonly used for correcting the pixel value from multiple pixel columns.In addition, in each above-described embodiment, it has been described that
The situation that amplifying circuit 104 is switched between two kinds of gain.However, the invention is not restricted to this, amplifying circuit 104
It can be switched among three or more gains.In this case, biased for each setting in multiple gains
Corrected value and gain correcting value.
<3rd embodiment>
Reference picture 16 is described to the image sensing system according to 3rd embodiment.In figure 16, image sensing system bag
Include the barrier 151 for lens protection, make subject optical imagery camera lens 152 of the formation on imaging sensor 154 and
Make by the variable aperture 153 of the light quantity of camera lens 152.Image sensing system also includes the letter to being exported from imaging sensor 154
Number signal processing unit handled 155.The signal exported from imaging sensor 154 is to be used to generate by shooting subject
And the image sensing signal of the image obtained.Signal processing unit 155 is as needed, to the figure exported from imaging sensor 154
As the various corrections of sensing signal progress and compression, and generate image.Camera lens 152 and the formation of aperture 153 make light gather image
The optical system of sensor 154.
The image sensing system amplified in Figure 16 also includes the buffer storage location 156 for temporary transient storage image data
With the external interface unit 157 for being communicated with outer computer.Image sensing system also includes being used to store or read
Dismountable storage medium 159 (for example, semiconductor memory etc.) of image sensing data and for storing or reading storage
The storage medium control interface 158 of medium 159.Image sensing system also includes controlling various calculating and the photograph of whole Digital Still
The control/computing unit 1510 of machine.
Image sensing system shown in Figure 16, which can have, to be constructed as below：It is disposed in what is separated with imaging sensor 154
Signal processing unit 155 on semiconductor substrate includes the signal processing circuit described in first embodiment and second embodiment
111.In this configuration, signal processing unit 155 is the signal processing unit for including correcting unit.Even if using the construction, root
It can also be obtained and the effect phase described in first embodiment and second embodiment according to the image sensing system of the 3rd embodiment
Same effect.It is used as other constructions, it is also possible to be constructed as below：It is disposed in the semiconductor substrate separated with imaging sensor 154
On control/computing unit 1510 include the signal processing circuit 111 described in first embodiment and second embodiment.In the structure
In the case of making, control/computing unit 1510 is the signal processing unit for including correcting unit.
It is constructed as below although the foregoing description of the present embodiment is assumed：Letter described in first embodiment and second embodiment
Number process circuit 111 is disposed in the outside of imaging sensor 154, but can also be constructed as below：Only some functions are disposed in
The outside of imaging sensor 154.For example, S1-N1, S2-N2, S3-N3 and S4-N4 are output to figure by signal processing circuit 111
As the outside of sensor 154.Signal processing unit 155 or control/computing unit 1510 calculate gain correcting value βGWith biasing school
On the occasion of αG.Signal processing unit 155 or control/computing unit 1510 are by the gain correcting value β obtainedGWith bias correction value αG
Return to the signal processing circuit 111 that imaging sensor 154 includes.The signal processing circuit 111 of imaging sensor 154 is used
These corrected values carry out picture element signal read operation.Even if using the construction, it is also possible to obtain real with first embodiment and second
Apply the effect identical effect described in example.
Can be stacked by the semiconductor substrate for being equipped with the semiconductor substrate of imaging sensor 154 and separating, at this
On the semiconductor substrate of separation, the signal processing unit 155 or control/computing unit 1510 as correction unit are equipped.
Although with reference to exemplary embodiment, invention has been described, but it is to be understood that aspect of the invention is not limited
In disclosed exemplary embodiment.Most wide explanation should be given to scope of the following claims so that its cover it is all
These modified examples and equivalent 26S Proteasome Structure and Function.
Claims (20)
1. a kind of solid state image sensor, the solid state image sensor includes：
Pixel, it is configured to picture element signal of the generation corresponding to incident light；
Amplifying circuit, it is configured to amplify the picture element signal；
Circuit is set, and it is configured to the comparison knot between the picture element signal that amplifies based on threshold value and by the amplifying circuit
Really, the gain of the amplifying circuit is set；And
Correcting circuit, it is configured to by using the first corrected value and the second corrected value, to set electricity by described to being exaggerated
The picture element signal of gain that road is set is corrected, and first corrected value is the value corresponding to gain error, and institute
Stating the second corrected value is and the corresponding value of amplifying circuit biasing in the gain.
2. solid state image sensor according to claim 1, wherein, the amplifying circuit is amplifying the picture element signal
Change the gain simultaneously.
3. solid state image sensor according to claim 1, wherein,
The solid state image sensor includes multiple pixels, and each pixel is configured to generation and believed corresponding to the pixel of incident light
Number, and
The gain for setting circuit that the amplifying circuit is set for each pixel.
4. solid state image sensor according to claim 3, wherein,
The multiple pixel is arranged to form multiple row,
The solid state image sensor includes multiple amplifying circuits, and each amplifying circuit is configured to the respective column from pixel
The picture element signal be amplified,
The correcting circuit is by using first corrected value and second corrected value, to by the multiple amplifying circuit
In the amplification of an amplifying circuit multiple picture element signals in a picture element signal be corrected, and by using each personal
In first corrected value and second corrected value that correct a picture element signal in the multiple picture element signal, to by
One other pixel signal in the multiple picture element signal of another amplifying circuit amplification in the multiple amplifying circuit enters
Row correction.
5. solid state image sensor according to claim 1, the solid state image sensor also includes：
A/D change-over circuits, its picture element signal for being configured to be amplified is converted into digital value,
Wherein, the correcting circuit is corrected to the picture element signal for being converted into digital value.
6. solid state image sensor according to claim 1, wherein,
The amplifying circuit will amplify the first gain from the pixel reset signal of the pixel supply under reset state,
In the case where the amplifying circuit to be set to first gain by the setting circuit, the correcting circuit is used
The pixel reset signal of first gain is exaggerated, to correct the picture element signal for being exaggerated first gain,
And
In the case where the amplifying circuit to be configured differently than to the second gain of first gain by the setting circuit,
The correcting circuit uses first corrected value, second corrected value and the pixel for being exaggerated first gain
Reset signal, to correct the picture element signal for being exaggerated second gain.
7. solid state image sensor according to claim 6, wherein, the correcting circuit is corrected according to β × (S-N)-α
The picture element signal,
Wherein, S is the value for the picture element signal for being exaggerated second gain, and N is be exaggerated first gain described
The value of pixel reset signal, β is first corrected value, and α is second corrected value.
8. solid state image sensor according to claim 1, wherein,
The amplifying circuit amplifies test signal by using each gain in multiple gains, to generate multiple amplification test letters
Number, and
The correcting circuit is based on the multiple amplification test signal, to determine second corrected value.
9. solid state image sensor according to claim 8, wherein, the test signal is the pixel under reset state
It is supplied to the signal of the amplifying circuit.
10. solid state image sensor according to claim 1, wherein,
The amplifying circuit amplifies the first test signal and the second test signal by using each gain in multiple gains, comes
Multiple amplification test signals are generated, second test signal has the value different from first test signal, and
The correcting circuit is based on the multiple amplification test signal, to determine first corrected value.
11. solid state image sensor according to claim 1, the solid state image sensor also includes：
Memory, it is configured to keep first corrected value and second corrected value,
Wherein, the correcting circuit is by using first corrected value and second correction read from the memory
Value, to correct amplified picture element signal.
12. solid state image sensor according to claim 1, wherein, the setting circuit is based on the threshold value with being put
Comparative result between big picture element signal, to determine whether the amplifying circuit should change the gain.
13. solid state image sensor according to claim 12, wherein, determine the amplifying circuit in the setting circuit
In the case of the gain should be changed, the amplifying circuit reduces the gain.
14. solid state image sensor according to claim 1, wherein, it is described that circuit is set to the picture element signal that is amplified
Carry out slicing.
15. a kind of camera, the camera includes：
Solid state image sensor according to any one of claim 1 to 14；And
Signal processing unit, it is configured to handle the pixel value obtained by the solid state image sensor.
16. a kind of image sensing system, described image sensing system includes：
Solid state image sensor, it includes：
Pixel, it is configured to picture element signal of the generation corresponding to incident light,
Amplifying circuit, it is configured to amplify the picture element signal, and
Circuit is set, and it is configured to the comparison knot between the picture element signal that amplifies based on threshold value and by the amplifying circuit
Really, the gain of the amplifying circuit is set；And
Correcting circuit, it, which is configured to obtain, is used for the picture element signal to being exaggerated the gain set by the setting circuit
The first corrected value and the second corrected value being corrected,
Wherein, first corrected value is the value corresponding to gain error, and
Second corrected value is value corresponding with the amplifying circuit biasing in the gain.
17. image sensing system according to claim 16, wherein,
The solid state image sensor also includes signal processing circuit, wherein from the correcting circuit to the signal processing circuit
First corrected value and second corrected value are have input, and
The signal processing circuit is by using first corrected value and second corrected value, to be set to being exaggerated by described
The picture element signal for the gain that circuits are set is corrected.
18. image sensing system according to claim 16, wherein,
The solid state image sensor is disposed on the first semiconductor substrate, and
The correcting circuit is disposed on the second semiconductor substrate different from first semiconductor substrate.
19. image sensing system according to claim 18, wherein, first semiconductor substrate is stacked in described
On two semiconductor substrates.
20. a kind of control method of solid state image sensor, the solid state image sensor includes：Generation is configured to correspond to
The pixel of the picture element signal of incident light and the amplifying circuit for being configured to amplify the picture element signal, the control method include
Following steps：
Comparative result between the picture element signal amplified based on threshold value and by the amplifying circuit, to set the amplification electricity
The gain on road；And
By using the first corrected value and the second corrected value, come to being exaggerated described in the gain set in the setting steps
Picture element signal is corrected, first corrected value be corresponding to gain error value, and second corrected value for institute
The amplifying circuit stated in gain biases corresponding value.
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| JP2015207496 | 2015-10-21 | ||
| JP2015-207496 | 2015-10-21 | ||
| JP2016164065A JP6739288B2 (en) | 2015-10-21 | 2016-08-24 | Solid-state imaging device, control method thereof, imaging system, and camera |
| JP2016-164065 | 2016-08-24 |
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| JP2019068267A (en) | 2017-09-29 | 2019-04-25 | キヤノン株式会社 | Imaging apparatus, imaging system, and mobile body |
| JP7361582B2 (en) * | 2019-11-29 | 2023-10-16 | キヤノン株式会社 | Photoelectric conversion devices, photoelectric conversion systems, and transportation equipment |
| JP2021121060A (en) | 2020-01-30 | 2021-08-19 | キヤノン株式会社 | Semiconductor device, system, and apparatus |
| JP2022069132A (en) | 2020-10-23 | 2022-05-11 | キヤノン株式会社 | Imaging apparatus, imaging system and driving method of imaging apparatus |
| JP2022069136A (en) | 2020-10-23 | 2022-05-11 | キヤノン株式会社 | Imaging apparatus, imaging system and driving method of imaging apparatus |
| JP2022069133A (en) | 2020-10-23 | 2022-05-11 | キヤノン株式会社 | Photoelectric conversion device, photoelectric conversion system, and mobile body |
| JP2023023220A (en) | 2021-08-04 | 2023-02-16 | キヤノン株式会社 | Photoelectric conversion device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7382298B1 (en) * | 2007-01-17 | 2008-06-03 | Analog Devices, Inc. | Code-correction structures and methods for digital displays |
| CN101873140A (en) * | 2009-04-24 | 2010-10-27 | 索尼公司 | Digital to analog converter, solid-state imaging device and camera system |
| CN102348074A (en) * | 2009-07-27 | 2012-02-08 | 索尼公司 | Solid-state imaging device and camera system |
| CN103119928A (en) * | 2010-09-30 | 2013-05-22 | 佳能株式会社 | Solid-state imaging apparatus |
| CN104137531A (en) * | 2012-03-02 | 2014-11-05 | 三菱电机株式会社 | Image processing device and method |
| CN104639850A (en) * | 2013-11-11 | 2015-05-20 | 联咏科技股份有限公司 | Image sensing device and black level control method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008053959A (en) * | 2006-08-23 | 2008-03-06 | Matsushita Electric Ind Co Ltd | Solid imaging device |
| JP2008236158A (en) * | 2007-03-19 | 2008-10-02 | Olympus Imaging Corp | Imaging module |
| JP5528283B2 (en) * | 2010-09-30 | 2014-06-25 | キヤノン株式会社 | Solid-state imaging device |
| JP5893550B2 (en) * | 2012-04-12 | 2016-03-23 | キヤノン株式会社 | Imaging apparatus and imaging system |
| JP5813067B2 (en) * | 2012-12-20 | 2015-11-17 | キヤノン株式会社 | Imaging device driving method, digital signal correction method, imaging device, imaging system driving method, and imaging system |
-
2016
- 2016-08-24 JP JP2016164065A patent/JP6739288B2/en active Active
- 2016-10-18 CN CN201610906392.7A patent/CN106973246B/en active Active
-
2020
- 2020-07-16 JP JP2020122344A patent/JP6998995B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7382298B1 (en) * | 2007-01-17 | 2008-06-03 | Analog Devices, Inc. | Code-correction structures and methods for digital displays |
| CN101873140A (en) * | 2009-04-24 | 2010-10-27 | 索尼公司 | Digital to analog converter, solid-state imaging device and camera system |
| CN102348074A (en) * | 2009-07-27 | 2012-02-08 | 索尼公司 | Solid-state imaging device and camera system |
| CN103119928A (en) * | 2010-09-30 | 2013-05-22 | 佳能株式会社 | Solid-state imaging apparatus |
| CN104137531A (en) * | 2012-03-02 | 2014-11-05 | 三菱电机株式会社 | Image processing device and method |
| CN104639850A (en) * | 2013-11-11 | 2015-05-20 | 联咏科技股份有限公司 | Image sensing device and black level control method thereof |
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| JP2020171061A (en) | 2020-10-15 |
| JP6739288B2 (en) | 2020-08-12 |
| CN106973246B (en) | 2020-05-01 |
| JP6998995B2 (en) | 2022-01-18 |
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