CN106971994A - 一种单层板封装结构及其工艺方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 230000008569 process Effects 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 239000005022 packaging material Substances 0.000 claims abstract description 9
- 239000003963 antioxidant agent Substances 0.000 claims abstract description 4
- 230000003078 antioxidant effect Effects 0.000 claims abstract description 4
- 235000006708 antioxidants Nutrition 0.000 claims abstract description 4
- 239000003973 paint Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000003384 imaging method Methods 0.000 claims description 3
- 238000010422 painting Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 238000005538 encapsulation Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
本发明涉及一种单层板封装结构及其工艺方法,所述结构包括绝缘线路层(1)和外引脚线路层(2),所述绝缘线路层(1)正面设置有内层金属层(3),所述内层金属层(3)与外引脚线路层(2)正面相连接,所述内层金属层(3)正面通过金属球(5)设置有芯片(4),所述绝缘线路层(1)、外引脚线路层(2)、内层线路层(3)以及芯片(4)***均包封有塑封料(6),所述外引脚线路层(2)背面设置有抗氧化金属层(7)。本发明一种单层板封装结构及其工艺方法,只需单层线路层就能起到常规引线框的作用,能够缩小半导体封装结构的尺寸,提高引脚和塑封料之间的结合性能。
Description
技术领域
本发明涉及一种单层板封装结构及其工艺方法,属于半导体封装技术领域。
背景技术
传统的半导体芯片是用引线框作为承载件来形成一半导体封装结构,封装过程为:将晶圆通过划片工艺后被切割为小的芯片(Die),然后将切割好的芯片用导电材料贴装到相应的引线框架的基岛上,再利用超细的金属(金锡铜铝)导线或者导电性树脂将芯片的焊垫连接到引线框架的相应引脚,并构成所要求的电路;然后再对独立的芯片用塑料外壳加以封装保护,形成半导体封装结构。以引线框架作为承载件的半导体的封装的形态种类繁多,随着半导体产品轻薄短小的发展趋势,传统的引线框往往因为厚度以及线路密度的限制,无法进一步的缩小封装件的整体高度。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种单层板封装结构及其工艺方法,只需单层线路层就能起到常规引线框的作用,能够缩小半导体封装结构的尺寸,提高引脚和塑封料之间的结合性能。
本发明解决上述问题所采用的技术方案为:一种单层板封装结构,它包括绝缘线路层和外引脚线路层,所述绝缘线路层正面设置有内层金属层,所述内层金属层与外引脚线路层正面相连接,所述内层金属层正面通过金属球设置有芯片,所述绝缘线路层、外引脚线路层、内层线路层以及芯片***均包封有塑封料,所述外引脚线路层背面设置有抗氧化金属层。
一种单层板封装结构的工艺方法,所述方法包括如下步骤:
步骤一、取一片金属板;
步骤二、在金属板的上表面涂覆一层绿漆;
步骤三、金属板的上表面进行曝光显影或者网版印刷的方式把绿漆形成线路形状;
步骤四、在金属板的上表面用化学电镀或溅镀的方式形成一薄铜层;
步骤五、金属板表面贴覆光阻膜;
步骤六、曝光显影,暴露出所需电镀线路的开口;
步骤七、电镀金属层,在光阻膜暴露开口部分电镀金属,形成内层线路层和外引脚线路层;
步骤八、去除光阻膜;
步骤九、微蚀,将多余的薄铜层用蚀刻方式去除;
步骤十、贴装芯片,包封;
步骤十一、金属板背面进行开窗或者全部蚀刻;
步骤十二、对外引脚进行处理;
步骤十三、切割成单品。
与现有技术相比,本发明的优点在于:
1、只需单层线路层就能起到常规引线框的作用,明显降低半导体封装结构的厚度;
2、线路层是用电镀形成,与常规引线框蚀刻相比,线路的密度和灵活性比较高,可适合多种类型的封装结构;
3、绝缘层形成线路形状,然后在其之上披覆金属层,既能将金属层部分绝缘,又能将后续包封的塑封料填充至线路层的中间,保证塑封料和引脚线路的结合性能。
附图说明
图1为本发明一种单层板封装结构的示意图。
图2~图14为本发明一种单层板封装结构工艺方法的各工序流程图。
其中:
绝缘线路层1
外引脚线路层2
内层线路层3
芯片4
金属球5
塑封料6
抗氧化金属层7。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
参见图1,本实施例中的一种单层板封装结构,它包括绝缘线路层1和外引脚线路层2,所述绝缘线路层1正面设置有内层金属层3,所述内层金属层3与外引脚线路层2正面相连接,所述内层金属层3正面通过金属球5设置有芯片4,所述绝缘线路层1、外引脚线路层2、内层线路层3以及芯片4***均包封有塑封料6,所述外引脚线路层2背面设置有抗氧化金属层7。
其工艺方法包括如下步骤:
步骤一、参见图2,取一片厚度合适的金属板;
步骤二、参见图3,在金属板的上表面涂覆一层绝缘层,如绿漆;
步骤三、参见图4,金属板的上表面进行曝光显影或者网版印刷的方式把绿漆形成线路形状;
步骤四、参见图5,在金属板的上表面用化学电镀或溅镀的方式形成一薄铜层,为了之后电镀工序的导电性;
步骤五、参见图6,金属板表面贴覆光阻膜;
步骤六、参见图7,曝光显影,暴露出绿漆部分以及其他所需的开口;
步骤七、参见图8,电镀金属层,在光阻膜暴露开口部分电镀金属,形成内层线路层和外引脚线路层;
步骤八、参见图9,去除光阻膜;
步骤九、参见图10,微蚀,将多余的薄铜层用蚀刻方式去除;
步骤十、参见图11,贴装芯片,包封;
步骤十一、参见图12,金属板背面进行开窗或者全部蚀刻;
步骤十二、参见图13,对外引脚进行处理,可根据需要披覆锡或者镍钯金等金属;
步骤十三、参见图14,切割成单品。
除上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。
Claims (2)
1.一种单层板封装结构,其特征在于:它包括绝缘线路层(1)和外引脚线路层(2),所述绝缘线路层(1)正面设置有内层金属层(3),所述内层金属层(3)与外引脚线路层(2)正面相连接,所述内层金属层(3)正面通过金属球(5)设置有芯片(4),所述绝缘线路层(1)、外引脚线路层(2)、内层线路层(3)以及芯片(4)***均包封有塑封料(6),所述外引脚线路层(2)背面设置有抗氧化金属层(7)。
2.一种单层板封装结构的工艺方法,其特征在于所述方法包括如下步骤:
步骤一、取一片金属板;
步骤二、在金属板的上表面涂覆一层绿漆;
步骤三、金属板的上表面进行曝光显影或者网版印刷的方式把绿漆形成线路形状;
步骤四、在金属板的上表面用化学电镀或溅镀的方式形成一薄铜层;
步骤五、金属板表面贴覆光阻膜;
步骤六、曝光显影,暴露出所需电镀线路的开口;
步骤七、电镀金属层,在光阻膜暴露开口部分电镀金属,形成内层线路层和外引脚线路层;
步骤八、去除光阻膜;
步骤九、微蚀,将多余的薄铜层用蚀刻方式去除;
步骤十、贴装芯片,包封;
步骤十一、金属板背面进行开窗或者全部蚀刻;
步骤十二、对外引脚进行处理;
步骤十三、切割成单品。
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US20070290306A1 (en) * | 2006-06-19 | 2007-12-20 | Shinko Electric Industries Co., Ltd. | Wiring substrate and manufacturing method thereof, and semiconductor apparatus |
JP4400802B2 (ja) * | 1999-08-23 | 2010-01-20 | 大日本印刷株式会社 | リードフレーム及びその製造方法並びに半導体装置 |
CN102842546A (zh) * | 2011-06-23 | 2012-12-26 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
CN105762132A (zh) * | 2014-12-04 | 2016-07-13 | 矽品精密工业股份有限公司 | 单层线路式封装基板及制法、单层线路式封装结构及制法 |
CN106298709A (zh) * | 2016-11-11 | 2017-01-04 | 三星半导体(中国)研究开发有限公司 | 低成本扇出式封装结构 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4400802B2 (ja) * | 1999-08-23 | 2010-01-20 | 大日本印刷株式会社 | リードフレーム及びその製造方法並びに半導体装置 |
US20070290306A1 (en) * | 2006-06-19 | 2007-12-20 | Shinko Electric Industries Co., Ltd. | Wiring substrate and manufacturing method thereof, and semiconductor apparatus |
CN102842546A (zh) * | 2011-06-23 | 2012-12-26 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
CN105762132A (zh) * | 2014-12-04 | 2016-07-13 | 矽品精密工业股份有限公司 | 单层线路式封装基板及制法、单层线路式封装结构及制法 |
CN106298709A (zh) * | 2016-11-11 | 2017-01-04 | 三星半导体(中国)研究开发有限公司 | 低成本扇出式封装结构 |
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