CN106971952B - Semiconductor device failure analyzes sample and preparation method thereof, failure analysis method - Google Patents
Semiconductor device failure analyzes sample and preparation method thereof, failure analysis method Download PDFInfo
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- CN106971952B CN106971952B CN201610020339.7A CN201610020339A CN106971952B CN 106971952 B CN106971952 B CN 106971952B CN 201610020339 A CN201610020339 A CN 201610020339A CN 106971952 B CN106971952 B CN 106971952B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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Abstract
The present invention provides a kind of semiconductor device failure analysis sample and preparation method thereof, failure analysis method, by opening up the bearing groove and the diversion channel slot for opening up at least one connection bearing groove that one is consistent with semiconductor devices sample on carrier, and electroconductive binder is placed in the bearing groove opened, heating or ultraviolet light carrier melt electroconductive binder, finally semiconductor devices sample is placed in bearing groove, light pressure semiconductor devices sample is allowed to flush with the ledge surface of carrying groove sidewall, pollution of the electroconductive binder to sample surfaces is avoided in this way, the appearance of the uneven grinding phenomenon of sample surfaces is more importantly avoided when grinding de-layer.
Description
Technical field
The present invention relates to semiconductor device processing technology field more particularly to a kind of semiconductor device failure analysis sample and
Preparation method, failure analysis method.
Background technique
In general, integrated circuit fails unavoidably in development, production and use process.As people are to product matter
The continuous improvement of amount and reliability requirement, failure analysis work also become more and more important, are analyzed by chip failure, Ke Yibang
Help Integrated circuit designers find the defect in design, the mismatch of technological parameter or design and operate in improper etc. ask
Topic.Specifically, the meaning of failure analysis is mainly manifested in the following aspects: 1) failure analysis is determining chip failure mechanism
Necessary means；2) failure analysis provides necessary information for effective fault diagnosis；3) failure analysis is design engineer
The design for continuously improving or repairing chip, being allowed to more coincide with design specification provides necessary feedback information；4) failure point
Analysis can assess the validity of different test vectors, provide necessary supplement for production test, mention for validation test process optimization
For necessary Information base.
During failure analysis, generally require to one or more layers internal structure circuit of fixed certain in sample chip
It is observed and is analyzed.With the continuous improvement of processing procedure, the minimum dimension of product component is constantly reducing, the thickness of product
It is constantly reducing, its thickness of the simple product of some functions is especially small.How to more and more thinner single product carry out grinding and
Observation becomes the problem of failure analysis.
Please refer to Figure 1A, a kind of currently used method is the encapsulating film modeling that ultra-thin sample 10 is wrapped up in first removal, then sharp
Ultra-thin sample 10 is pasted on slightly larger thick chip 11 with conductive paraffin 12 and is handled again, in conjunction with shown in Figure 1A and 1B, tool
Steps are as follows for body:
S101, sample 10 go to encapsulate；
S102 cleans sample 10；
S103 heats thick chip 11 and is laid with conductive paraffin 12 on thick chip 11；
S104 is sticked to sample 10 on thick chip 11 by conductive paraffin 12；
S105 carries out grinding to sample 10 and removes layer operation, to obtain preferable failure analysis surface；
S106 passes through scanning electron microscope (SEM) observing samples 10.
Inventors have found that the above method, other than taking a long time, there is also following disadvantages:
1. due to the soft characteristic of conductive paraffin 12, be located in practical operation the edge of the sample 10 of thick 11 top of chip with
And surface is easy the contamination by conductive paraffin 12；
2. since slim sample 10 is different from the material of conductive paraffin 12 of surrounding, and the edge of sample 10 and thick chip
A difference in height has been compared in the upper surface (i.e. not by part that conductive paraffin 12 is covered with sample 10) of 11 exposures, this will lead to sample
The grinding rate at its edge when being ground processing of product 10 will be faster than in-between position, be easy to cause the whole high of 10 surface of sample
That spends is uneven；
3. it be easy to cause sample 10 to be bent since the expansion coefficient difference of conductive paraffin 12 and sample 10 itself is larger,
In subsequent process of lapping, the bending of sample 10 can make its grinding level variable gradient big, and 10 local surfaces of sample are very uneven
It is whole, it is easily broken.
Therefore, it is necessary to a kind of new semiconductor device failure analysis samples and preparation method thereof, failure analysis method, to keep away
The pollution and grinding height unevenness for exempting from sample observation surface, improve the success rate of sample preparation.
Summary of the invention
The purpose of the present invention is to provide a kind of semiconductor device failure analysis samples and preparation method thereof, failure analysis side
Method improves the success rate of sample preparation to avoid the pollution and grinding height unevenness on sample observation surface.
To solve the above problems, the present invention proposes a kind of preparation method of semiconductor device failure analysis sample, comprising:
Semiconductor device sample and one is provided for carrying the carrier of the semiconductor devices sample；
The bearing groove for accommodating the semiconductor devices sample is formed on the carrier, and the depth of the bearing groove is big
In the thickness of the semiconductor devices sample；
The diversion channel slot of at least one connection bearing groove is formed on the carrier around the bearing groove；
Electroconductive binder is put into the bearing groove；
The semiconductor devices sample is put into the bearing groove, and presses the semiconductor devices sample until described
The upper surface of semiconductor devices sample is not higher than the ledge surface of surrounding bearing groove, described in extra electroconductive binder flows into
Diversion channel slot；
The upper surface of the semiconductor devices sample is ground, to obtain failure analysis sample.
Further, the quantity of the diversion channel slot is multiple, and multiple diversion channel slots are evenly distributed on the carrying
Around slot.
Further, the bearing groove and the diversion channel slot are all made of etching technics and are formed.
Further, the bearing groove and the diversion channel slot be all made of wet-etching technology, dry etch process or
Laser etching process is formed.
Further, after being put into electroconductive binder in the bearing groove, the semiconductor devices sample is put into institute
Before stating in bearing groove, one layer of reinforcement conductive layer is formed on the surface of the carrier and the electroconductive binder.
Further, the material for reinforcing conductive layer includes at least one of gold, silver and platinum.
Further, the reinforcement conductive layer is formed using vapor deposition or sputter deposition craft.
Further, it is described reinforce conductive layer with a thickness of 5nm~100nm.
Further, the electroconductive binder is conductive paraffin or conducting resinl.
Further, the conducting resinl includes that epoxide resin conductive adhesive, organic siliconresin conducting resinl, polyimide resin are led
In electric glue, phenolic resin conducting resinl, polyester resin conducting resinl, polyurethane resin conducting resinl and acrylic resin conducting resinl extremely
Few one kind.
Further, after being put into electroconductive binder in the bearing groove, heating or ultraviolet lighting are carried out to the carrier
It penetrates, until the electroconductive binder melts.
Further, the temperature heated to the carrier is 30 DEG C~150 DEG C；Carry out ultraviolet light time be
5s~20s.
Further, the semiconductor devices sample includes encapsulation overlay film, and the semiconductor devices sample is being put into institute
Before stating in bearing groove, the encapsulation overlay film of the semiconductor devices sample surfaces is removed.
Further, the semiconductor devices sample table is removed using chemical reagent etching process or mechanical polishing process
The encapsulation cladding in face.
Further, chemical reagent used in the chemical reagent etching process is fuming nitric aicd or hydrofluoric acid.
Further, after the encapsulation overlay film for removing the semiconductor devices sample surfaces, the semiconductor devices sample is cleaned
Product.
Further, the semiconductor devices sample is cleaned using ultrasonic cleaning process.
Further, cleaning solution used in the ultrasonic cleaning process is deionized water, dehydrated alcohol or acetone
Solution.
The present invention also provides a kind of semiconductor device failures to analyze sample, comprising:
Semiconductor devices sample；
Carrier is provided with the diversion channel slot of bearing groove and at least one connection bearing groove on the carrier, described
Bearing groove accommodates the semiconductor devices sample, and the bearing groove step table of the upper surface of the semiconductor devices sample and surrounding
Face flush or lower than surrounding bearing groove ledge surface；
Electroconductive binder, be located at the bearing groove in, for be bonded the bearing groove bottom surface and the semiconductor
The lower surface of device example.
Further, the quantity of the diversion channel slot is multiple, and the multiple diversion channel slot is evenly distributed on the carrying
Around slot.
Further, the quantity of the diversion channel slot is four, and four diversion channel slots are distributed in crosswise.
Further, semiconductor device failure analysis sample further includes reinforcing conductive layer, the reinforcement conductive layer
Be formed between the electroconductive binder upper surface and semiconductor devices sample lower surface and the carrying groove sidewall with
Between the semiconductor devices sample side wall.
Further, the material for reinforcing conductive layer includes at least one of gold, silver and platinum.
The present invention also provides a kind of semiconductor device failure analysis methods, comprising:
Semiconductor device failure analysis sample is prepared according to the preparation method of above-mentioned semiconductor device failure analysis sample
Product, or provide just like above-mentioned semiconductor device failure analysis sample and its upper surface is ground；
Failure analysis is carried out to semiconductor device failure analysis sample.
Further, aobvious using transmission electron microscope, scanning electron microscope, focused ion beam microscope or low-light
Micro mirror is observed semiconductor device failure analysis sample.
Compared with prior art, technical solution of the present invention has the advantage that
1. semiconductor devices sample is being bonded to bearing groove due to the setting of bearing groove and diversion channel slot in carrier
When middle, extra electroconductive binder will receive the extruding of semiconductor devices sample bottom and side wall, so as to pass through carrying
Diversion channel slot around slot directly guides, therefore can guarantee semiconductor devices sample surfaces not by the dirt of electroconductive binder
Dye, raising are prepared into power；
2. due to the depth and width of the bearing groove in carrier be it is customized according to the specification of semiconductor devices sample,
Therefore it can guarantee that semiconductor devices sample upper surface is equal to or slightly below carrier upper surface, so that semiconductor devices sample
Product upper surface its edge when being ground processing is identical with the intermediate grinding rate at position, and sample surfaces grinding is uniform, it is not easy to
Broken, raising is prepared into power；
3. be pressure bonded in bearing groove due to semiconductor devices sample, electroconductive binder is predominantly located at semiconductor devices sample
Bottom, in subsequent process of lapping, even if electroconductive binder can expand and even inflation, therefore electroconductive binder
It not will cause the bending of sample surfaces with the expansion coefficient difference of semiconductor devices sample, it is final to obtain failure analysis sample surface
It is smooth, uniform, it is not easy to which that broken, raising is prepared into power；
4. the setting of bearing groove and diversion channel slot, the grinding that can greatly reduce the upper surface of semiconductor devices sample is difficult
Degree, and then the operating time of failure analysis sample preparation can be reduced.
Detailed description of the invention
Figure 1A is a kind of the schematic diagram of the section structure of semiconductor device failure analysis sample in the prior art；
Figure 1B is a kind of preparation method flow chart of semiconductor device failure analysis sample in the prior art；
Fig. 2 is the preparation method flow chart of the semiconductor device failure analysis sample of the specific embodiment of the invention.
Fig. 3 A to 3E is device architecture cross-sectional view and top view in preparation method shown in Fig. 2.
Specific embodiment
To be clearer and more comprehensible the purpose of the present invention, feature, a specific embodiment of the invention is made with reference to the accompanying drawing
Further instruction, however, the present invention can be realized with different forms, it should not be to be confined to the embodiment described.
Referring to FIG. 2, the present embodiment proposes a kind of preparation method of semiconductor device failure analysis sample, comprising:
S201 provides semiconductor device sample and one for carrying the carrier of the semiconductor devices sample；
S202 forms the bearing groove for accommodating the semiconductor devices sample on the carrier, the bearing groove
Depth is greater than the thickness of the semiconductor devices sample；
S203 forms the diversion channel slot of at least one connection bearing groove on the carrier around the bearing groove；
S204 is put into electroconductive binder in the bearing groove；
The semiconductor devices sample is put into the bearing groove by S205, and it is straight to press the semiconductor devices sample
The ledge surface of surrounding bearing groove, extra electroconductive binder stream are not higher than to the upper surface of the semiconductor devices sample
Enter the diversion channel slot；
S206 grinds the upper surface of the semiconductor devices sample, to obtain failure analysis sample.
Fig. 3 A is please referred to, in step s 201, the semiconductor devices sample 30 to be observed provided can be transmitted electron
Microscope (Transmission electron microscope, hereinafter referred to as TEM) sample, scanning electron microscope
(Scanning Electron Microscope, hereinafter referred to as SEM) sample, focused ion beam microscope (Focus Ion
Beam Microscope, FIB) sample or low-light microscope (Emission Microscope, hereinafter referred to as EMMI) sample.
Wherein TEM is the important tool of electron micrology, and TEM is commonly used in the pattern of the film of detection composition semiconductor devices, size
With feature etc..After TEM sample is put into tem observation room, the main operational principle of TEM are as follows: when high-power electron beam penetrates TEM sample
Phenomena such as scattering, absorption, interference and diffraction occurs, so that contrast is formed in imaging plane, so that the image of TEM sample is formed,
Subsequent to be observed image, measured and analyzed, the TEM sample for TEM failure analysis can be one about 100 nanometers
The chip sample of thickness, this ultra-thin sample usually require to obtain by way of plane sample preparation (plan view).SEM is
Most-often used failure analysis apparatus, main working principle are high energy electron incidence solid sample surface, the original with sample
Elasticity or inelastic scattering occur for daughter nucleus and electron outside nucleus, and excitation sample is generated various physical signals and connect using electronic detectors
The collection of letters number forms an image.Subtle observation can be carried out to sample in cross section or surface and to the ingredient of sample to be tested using SEM
Confirm etc..SEM amplification factor can be from thousands of times to hundreds of thousands of times, and resolution ratio reaches 3nm, and a sample can check number
Thousand even tens of thousands of a MOS transistors, thus can satisfy at this stage or even the following many decades integrated circuit microstructure observing
Demand.FIB is now widely used for semiconductor electronic industry and integrated circuit (IC) industrially, and the working principle of FIB is to pass through
A kind of heavy metal ion hits sample and effectively controls removal material, using high energy ion beam (IB) incidence solid sample, with
Elasticity or inelastic scattering occur for the atomic nucleus and electron outside nucleus of sample, and excitation sample generates secondary electron, passes through electron beam
(EB) scanner or detector receive generated secondary electron signal and form image to be observed.EMMI is a kind of phase
When useful and ultrahigh in efficiency analysis tool, internal the released photon of integrated circuit (IC) can be detected, class of leaking electricity is mainly used for
The fixed point of failure is analyzed, and main operational principle is the luminescence phenomenon that semiconductor is utilized, there is electric leakage, breakdown, heat to carry
It in the device for flowing sub- effect, has photon and is emitted from failpoint, sample can be positioned plus voltage by microscope and lost
Imitate position.
In the present embodiment, the semiconductor devices sample 30 provided in step s 201 has upper surface (i.e. front, for losing
Effect analysis) and lower surface (i.e. the back side or bottom surface, for being bonded), it is enclosed at least one surface and encapsulates overlay film and (do not scheme
Show), which is mainly used for preventing aqueous vapor etc. from entering semiconductor devices sample 30, avoids causing semiconductor devices sample
30 surface oxidations etc., material can be polymer, such as epoxy resin etc..It is placed by the semiconductor devices sample 30
Before on carrier 31, need to remove the encapsulation overlay film, it specifically, can be using chemical reagent etching process or mechanical polishing work
Skill removes the encapsulation cladding of the semiconductor devices sample surfaces.Wherein, chemistry used in the chemical reagent etching process
Reagent can be fuming nitric aicd or hydrofluoric acid, and certainly, those skilled in the art can select according to the specific material of encapsulation cladding
Select corresponding chemical reagent.After the encapsulation overlay film for removing the semiconductor devices sample surfaces, the semiconductor is preferably cleaned
Device example 30 in the present embodiment, cleans the semiconductor device using ultrasonic cleaning process to provide the processing surface of crystallization
Semiconductor devices sample 30 is put into the solution such as deionized water, dehydrated alcohol or acetone soln and is surpassed by part sample
Sound wave room temperature constant temperature oscillation, duration of oscillation are 30s~10min, and the residue for remaining in 30 surface of semiconductor devices sample is gone
Fall, and spontaneously dries after taking out semiconductor devices sample 30 or it is dried using nitrogen.
In step s 201, the carrier 31 provided can be pure silicon (Si) substrate, silicon-on-insulator (SOI) substrate, germanium silicon
(SiGe) substrate, carbon silicon (SiC) substrate, aluminium oxide (Al2O3) substrate or GaAs (GaAs) substrate, quartz (SiO2) substrate etc.,
These substrates can also be referred to as " chip ", be also possible to the chip with some test pins, can also be glass or plastics.
Preferably, carrier upper surface be that one layer identical as the material of layer to be ground of semiconductor devices sample and thickness be more than or equal to should be to
The material layer of grinding layer.
Fig. 3 B is please referred to, in step S202, is being carried using etching modes such as wet etching, dry etching, laser ablations
31 surface of body forms bearing groove 310, and wherein shape, depth and length-width ratio of bearing groove 310 etc. are by semiconductor devices sample
30 specification determines, when semiconductor devices sample 30 is pressure bonded to holding groove 310 and is bonded by electroconductive binder therein secured
When, upper surface and other exposures around it that the optimum depth of holding groove 310 makes semiconductor devices sample 30 at this time just
Surface flushes, i.e., when 31 upper surface of carrier is without other layer, the upper surface of bonding semiconductor devices sample 30 and carrier 31
Upper surface flush, if 31 upper surface of carrier has other layer, the upper surface of bonding semiconductor devices sample 30 and its week
The topsheet surface on carrier 31 enclosed flushes (in such as Fig. 3 E on the upper surface of semiconductor devices sample 30 and surrounding carrier 31
Reinforcement conductive layer 33 upper surface), the optimum width of holding groove 310 can clamp bonding semiconductor devices sample just
30.Certainly, in order to reduce the etching difficulty of holding groove, those skilled in the art can directly be etched the specification of holding groove 310
To the specification for being slightly larger than semiconductor devices sample 30, that is, the depth of the bearing groove 310 is greater than the semiconductor devices sample 30
The sum of thickness and the thickness of electroconductive binder that is subsequently inputted into (as shown in Figure 3D), the width of the bearing groove 310 is greater than institute
State the width of semiconductor devices sample 30.
Please continue to refer to Fig. 3 B, in step S203, at least one is etched on the carrier 31 around the bearing groove 310
Item is connected to the diversion channel slot 311 of the bearing groove 310, and wherein the etching technics of diversion channel slot 311 can be with the quarter of bearing groove 310
Etching technique is identical, can also be different, and the depth of diversion channel slot 311 is identical as bearing groove 310, and the Excess conductive for shunting bonds
Agent.A bearing groove 310 is formd on 31 surface of carrier using laser etching process in the present embodiment and surrounds bearing groove 310
And 4 equally distributed diversion channel slots, 311,4 diversion channel slots 311 being connected to bearing groove 310 are distributed in crosswise.Wherein,
The wavelength of laser beam used in laser etching process be 150nm to 250nm, e.g. wavelength be 193nm or 248nm laser
Beam.In other embodiments of the invention, the quantity of diversion channel slot is more than or equal to 1, when being greater than 2, preferably, all curbs
Slot is evenly distributed on around the bearing groove.
Fig. 3 C is please referred to, in step S204, the conduction of solid-state or flow-like can be put into the bearing groove 310
Adhesive 32.Electroconductive binder 32 can include epoxide resin conductive adhesive for conductive paraffin or conducting resinl, the conducting resinl, organic
Silicone resin conducting resinl, polyimide resin conducting resinl, phenolic resin conducting resinl, polyester resin conducting resinl, polyurethane resin are conductive
At least one of glue and acrylic resin conducting resinl.Preferably, solid electroconductive binder is put into bearing groove 310
32, which can become fluid under heating or ultraviolet light, to give the semiconductor devices sample
Product 30 are put into the fully operational time that bonding is pressed in bearing groove 310, while guaranteeing to realize preferable adhesive property.It is being put into half
Before conductor device sample 30, heating or ultraviolet light carrier 31 can be such that solid electroconductive binder 32 melts, then
After being put into semiconductor devices sample 30, under normal temperature environment electroconductive binder 32 slowly restore solid-state and by bearing groove 310 with
Semiconductor devices sample 30 bonds together.Wherein, the temperature and time or progress ultraviolet lighting carrier 31 heated
The time penetrated depends on the property of electroconductive binder 32, such as when electroconductive binder 32 is conductive paraffin, adds to carrier 31
It is 30 DEG C~150 DEG C that the temperature of heat, which can choose,；Electroconductive binder 32 be epoxy conductive adhesive when, to the carrier into
The time of row ultraviolet light can choose as 5s~20s.
Further, in order to increase the electric conductivity of electroconductive binder entirety, charge when subsequent failure analysis and observation is reduced
Accumulation can be deposited one layer by conductions such as gold, silver or platinum after being put into electroconductive binder 32 on the surface of electroconductive binder 32
The reinforcement conductive layer 33 that metal is formed can be with this when electroconductive binder 32 becomes fluid after heating or ultraviolet light
Reinforce conductive layer 33 to mix, to greatly strengthen the whole electric conductivity of electroconductive binder 32, and then can be in subsequent failure point
The charge of accumulation is guided when analysis observation in time.The reinforcement conductive layer 33 of formation can be only located at the conductive adhesion in bearing groove 310
In the bottom surface of the bearing groove 310 on the surface and exposure of agent 32, the institute in addition to 311 surface of diversion channel slot can also be located at
On the surface for having the electroconductive binder 32 in carrier surface and bearing groove 310.It in other embodiments of the invention, can be with
The reinforcements conductive layer 33 is formed using sputtering or gas-phase deposition, formation reinforce conductive layer with a thickness of 5nm~
100nm。
3D and 3E are please referred to, in step S205, semiconductor devices sample 30 is put into the bearing groove 310, it is light to press
Semiconductor devices sample 30 is allowed to preferably be bonded with 310 bottom of bearing groove, and the optimum state gently pressed is to make semiconductor devices sample
30 lower surface of product preferable and 30 upper surface of semiconductor devices sample Nian Jie with 310 bottom of bearing groove and the upper table for reinforcing conductive layer 33
Face flushes (as shown in FIGURE 3 E).In this way, when can to grind the upper surface of semiconductor devices sample 30 in step S206,
It can guarantee the uniformity of grinding.Certainly since the depth of the bearing groove of etching 310 is slightly larger than the thickness of semiconductor devices sample 30
Degree can also slightly over-voltage semiconductor so preferable bonding in order to there is semiconductor devices sample 30 with 310 bottom of bearing groove
Device example 30 makes 30 upper surface of semiconductor devices sample slightly below reinforce conductive layer 33, or even is somewhat below the carrier of surrounding
In this case the upper surface of semiconductor devices sample 30 is ground in step S206 31 upper surface (as shown in Figure 3D)
When, the part that removal is higher than the upper surface of semiconductor devices sample 30 can be first ground, then to semiconductor devices sample 30
Upper surface carries out grinding with good uniformity together with carrier around.No matter the upper surface of semiconductor devices sample 30 and its week
How is the height of the ledge surface enclosed, and during gently pressure semiconductor devices sample 30, extra electroconductive binder 32 can be from holding
It carries 310 bottom of slot and flows into the diversion channel slot 311, and then guided, thereby may be ensured that the upper table of semiconductor devices sample 30
The cleanliness in face, and avoid the top edge of semiconductor devices sample 30 contaminated.
In step S206, the upper surface of the semiconductor devices sample 30 can be used and grind the incremental side of fineness
Formula is ground stage by stage, to obtain failure analysis sample.Such as granularity is first used to cooperate for 1 μm~5 μm of silicon nitride sand paper
The diamond grinding fluid that granularity is 0.5 μm~1 μm carries out rough lapping to the upper surface of semiconductor devices sample 30, removes semiconductor
The passivation layer etc. of 30 upper surface of device example；Then, then granularity is used to cooperate granularity for 0.01 μm~0.5 μm of silicon nitride sand paper
Diamond grinding fluid for 0.05 μm~0.1 μm tentatively grinds the upper surface of semiconductor devices sample 30, until exposure
The layer to be seen of 30 upper surface of semiconductor devices sample out；It is finally 0.001 μm~0.05 μm with polisher lapper cooperation granularity
Polishing fluid or polishing powder layer surface to be seen is polished, formed failure analysis sample.
3B is please referred to, and is combined shown in Fig. 3 D or Fig. 3 E, the present embodiment also provides a kind of semiconductor device failure analysis sample
Product, comprising:
Semiconductor devices sample 30；
Carrier 31 is provided with the water conservancy diversion of bearing groove 310 and at least one connection bearing groove 310 on the carrier 31
Groove 311, the bearing groove 310 accommodate the semiconductor devices sample 30, and the upper surface of the semiconductor devices sample 30
It is flushed with the ledge surface of 310 side wall of bearing groove of surrounding or the ledge surface of 310 side wall of bearing groove lower than surrounding；
Electroconductive binder 32 is located in the bearing groove 310, and for be bonded the bottom surface of the bearing groove 310 with
The lower surface of the semiconductor devices sample 30；
Reinforce conductive layer 33, is formed in 32 upper surface of electroconductive binder and 30 lower surface of semiconductor devices sample
Between, the load between 310 side wall of the bearing groove and 30 side wall of semiconductor devices sample and around the bearing groove 310
On the upper surface of body 31, wherein the material for reinforcing conductive layer 33 may include at least one of gold, silver and platinum.
In other embodiments of the invention, in the stronger situation of the electric conductivity of electroconductive binder 32, it is convenient to omit reinforce
Conductive layer 33；The quantity of diversion channel slot is preferably several, and all diversion channel slots are evenly distributed on around the bearing groove, such as
The quantity of diversion channel slot shown in Fig. 3 B is four, and four diversion channel slots are distributed in crosswise.
The present invention also provides a kind of semiconductor device failure analysis methods, comprising the following steps:
Above-mentioned semiconductor device failure analysis sample is provided；
The upper surface of semiconductor device failure analysis sample is ground, until exposing layer to be seen；
Using transmission electron microscope, scanning electron microscope or low-light microscope to the semiconductor device failure point
Analysis sample is observed.
The present invention also provides a kind of semiconductor device failure analysis methods, comprising the following steps:
Firstly, providing semiconductor device sample and one for carrying the carrier of the semiconductor devices sample；
Then, the bearing groove for accommodating the semiconductor devices sample is formed on the carrier, the bearing groove
Depth is greater than the thickness of the semiconductor devices sample；
Then, the diversion channel slot of at least one connection bearing groove is formed on the carrier around the bearing groove；
Then, electroconductive binder is put into the bearing groove；
Then, the semiconductor devices sample is put into the bearing groove, and it is straight to press the semiconductor devices sample
The ledge surface of surrounding bearing groove, extra electroconductive binder stream are not higher than to the upper surface of the semiconductor devices sample
Enter the diversion channel slot；
Then, the upper surface of the semiconductor devices sample is ground, to obtain failure analysis sample；
Then, using transmission electron microscope, scanning electron microscope or low-light microscope to the semiconductor devices
Failure analysis sample is observed.
In conclusion technical solution provided by the invention, by opening up one and semiconductor devices sample phase on carrier
The bearing groove of symbol and the diversion channel slot for opening up at least one connection bearing groove, and conductive adhesion is placed in the bearing groove opened
Agent, heating or ultraviolet light carrier melt electroconductive binder, finally semiconductor devices sample are placed in bearing groove,
Light pressure semiconductor devices sample is allowed to flush with the ledge surface of carrying groove sidewall, avoids electroconductive binder in this way to sample
The pollution on surface, it is often more important that the appearance of the uneven grinding phenomenon of sample surfaces is avoided when grinding de-layer.
Obviously, those skilled in the art can carry out various modification and variations without departing from spirit of the invention to invention
And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it
Interior, then the present invention is also intended to include these modifications and variations.
Claims (22)
1. a kind of preparation method of semiconductor device failure analysis sample characterized by comprising
Semiconductor device sample and one is provided for carrying the carrier of the semiconductor devices sample；
The bearing groove for accommodating the semiconductor devices sample is formed on the carrier, and the depth of the bearing groove is greater than institute
State the thickness of semiconductor devices sample；
The diversion channel slot of at least one connection bearing groove is formed on the carrier around the bearing groove；
Solid electroconductive binder is put into the bearing groove, and viscous in the carrier and the conduction using conductive metal
One layer of reinforcement conductive layer is formed on the surface of mixture, the conductive layer of reinforcing is located at owning in addition to the diversion channel slot surface
On the surface of electroconductive binder in carrier surface and bearing groove；
The semiconductor devices sample is put into the bearing groove, heating or ultraviolet light are carried out to the carrier, so that
The electroconductive binder melts and becomes fluid, and presses the semiconductor devices sample up to the semiconductor devices sample
Upper surface is lower than the upper surface of the reinforcement conductive layer of the bearing groove periphery, and the institute of semiconductor devices sample bottom
It states reinforcement conductive layer to mix with the electroconductive binder, extra electroconductive binder flows into the diversion channel slot, until conductive viscous
Mixture restores solid-state and the bearing groove and the semiconductor devices sample bonds together；
First grinding removal is higher than the part of the upper surface of the semiconductor devices sample, then to the upper of the semiconductor devices sample
Surface is ground together with the carrier of surrounding, to obtain failure analysis sample.
2. preparation method as described in claim 1, which is characterized in that the quantity of the diversion channel slot be it is multiple, it is multiple described
Diversion channel slot is evenly distributed on around the bearing groove.
3. preparation method as described in claim 1, which is characterized in that the bearing groove and the diversion channel slot are all made of quarter
Etching technique is formed.
4. preparation method as claimed in claim 3, which is characterized in that the bearing groove and the diversion channel slot are all made of wet
Method etching technics, dry etch process or laser etching process are formed.
5. preparation method as described in claim 1, which is characterized in that the material for reinforcing conductive layer includes gold, silver and platinum
At least one of.
6. preparation method as claimed in claim 5, which is characterized in that form described add using vapor deposition or sputter deposition craft
Dense conducting layer.
7. preparation method as described in claim 1, which is characterized in that it is described reinforce conductive layer with a thickness of 5nm~100nm.
8. preparation method as described in claim 1, which is characterized in that the electroconductive binder is conductive paraffin or conducting resinl.
9. preparation method as claimed in claim 8, the conducting resinl includes epoxide resin conductive adhesive, organic siliconresin conduction
Glue, polyimide resin conducting resinl, phenolic resin conducting resinl, polyester resin conducting resinl, polyurethane resin conducting resinl and propylene
At least one of acid resin conducting resinl.
10. preparation method as described in claim 1, which is characterized in that the temperature heated to the carrier is 30 DEG C~
150℃；The time for carrying out ultraviolet light is 5s~20s.
11. preparation method as described in claim 1, which is characterized in that the semiconductor devices sample includes encapsulation overlay film,
Before the semiconductor devices sample is put into the bearing groove, the encapsulation for removing the semiconductor devices sample surfaces is covered
Film.
12. preparation method as claimed in claim 11, which is characterized in that use chemical reagent etching process or mechanical polishing
Technique removes the encapsulation cladding of the semiconductor devices sample surfaces.
13. preparation method as claimed in claim 12, which is characterized in that chemistry used in the chemical reagent etching process
Reagent is fuming nitric aicd or hydrofluoric acid.
14. preparation method as claimed in claim 11, which is characterized in that remove the encapsulation of the semiconductor devices sample surfaces
After overlay film, the semiconductor devices sample is cleaned.
15. preparation method as claimed in claim 14, which is characterized in that clean the semiconductor using ultrasonic cleaning process
Device example.
16. preparation method as claimed in claim 15, which is characterized in that cleaning solution used in the ultrasonic cleaning process
For deionized water, dehydrated alcohol or acetone soln.
17. a kind of semiconductor device failure analyzes sample, which is characterized in that according to claim 1 to described in any one of 16
Semiconductor device failure analyzes the preparation method preparation of sample, and includes:
Semiconductor devices sample；
Carrier is provided with the diversion channel slot of bearing groove and at least one connection bearing groove, the carrying on the carrier
Slot accommodates the semiconductor devices sample, and the upper surface of the semiconductor devices sample and the bearing groove ledge surface of surrounding are neat
It is flat；
Electroconductive binder, be located at the bearing groove in, for be bonded the bearing groove bottom surface and the semiconductor devices
The lower surface of sample；And
Reinforce conductive layer, the reinforcement conductive layer is formed under the electroconductive binder upper surface and the semiconductor devices sample
Between surface and between the carrying groove sidewall and the semiconductor devices sample side wall, and it is formed in the electroconductive binder
Upper surface and the electroconductive binder mix.
18. semiconductor device failure as claimed in claim 17 analyzes sample, which is characterized in that the quantity of the diversion channel slot
To be multiple, the multiple diversion channel slot is evenly distributed on around the bearing groove.
19. semiconductor device failure as claimed in claim 18 analyzes sample, which is characterized in that the quantity of the diversion channel slot
It is four, four diversion channel slots are distributed in crosswise.
20. semiconductor device failure as claimed in claim 17 analyzes sample, which is characterized in that the material for reinforcing conductive layer
Material includes at least one of gold, silver and platinum.
21. a kind of semiconductor device failure analysis method characterized by comprising
It is led according to claim 1 to the preparation method preparation half of the analysis sample of semiconductor device failure described in any one of 16
Body component failure analyzes sample；
Failure analysis is carried out to semiconductor device failure analysis sample.
22. semiconductor device failure analysis method as claimed in claim 21, which is characterized in that use transmission electron microscopy
Mirror, scanning electron microscope, focused ion beam microscope or low-light microscope analyze sample to the semiconductor device failure
It is observed.
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| CN108535628A (en) * | 2018-03-20 | 2018-09-14 | 力特半导体（无锡）有限公司 | A kind of power semiconductor chip failure positioning method avoiding burn |
| CN113514300A (en) * | 2021-07-09 | 2021-10-19 | 长鑫存储技术有限公司 | Semiconductor structure processing jig and manufacturing method thereof |
| CN113311309B (en) * | 2021-07-30 | 2021-10-12 | 度亘激光技术（苏州）有限公司 | Method for stripping covering layer of semiconductor structure and method for analyzing failure of semiconductor structure |
| CN117655058A (en) * | 2022-08-23 | 2024-03-08 | 闻泰通讯股份有限公司 | Part extraction method in packaging structure and grinding jig |
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| CN102519771A (en) * | 2011-12-30 | 2012-06-27 | 青岛大学 | Method for preparing cross section transmission electron microscope sample |
| CN204271065U (en) * | 2014-12-23 | 2015-04-15 | 中芯国际集成电路制造(北京)有限公司 | Wafer sort sample |
| CN204450180U (en) * | 2015-01-14 | 2015-07-08 | 中芯国际集成电路制造(北京)有限公司 | A kind of sample lapping aid |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102519771A (en) * | 2011-12-30 | 2012-06-27 | 青岛大学 | Method for preparing cross section transmission electron microscope sample |
| CN204271065U (en) * | 2014-12-23 | 2015-04-15 | 中芯国际集成电路制造(北京)有限公司 | Wafer sort sample |
| CN204450180U (en) * | 2015-01-14 | 2015-07-08 | 中芯国际集成电路制造(北京)有限公司 | A kind of sample lapping aid |
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