CN106960686B - Reading method and flash memory device - Google Patents
Reading method and flash memory device Download PDFInfo
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- CN106960686B CN106960686B CN201710208361.9A CN201710208361A CN106960686B CN 106960686 B CN106960686 B CN 106960686B CN 201710208361 A CN201710208361 A CN 201710208361A CN 106960686 B CN106960686 B CN 106960686B
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Abstract
The invention discloses a reading method and a flash memory device, wherein the reading method is applied to the flash memory device, the flash memory device comprises a nonvolatile semiconductor memory cell array, and the reading method comprises the following steps: judging whether all memory cells of the nonvolatile semiconductor memory cell array are read or not, and if so, applying voltage to corresponding word lines of all the memory cells to perform first induction operation; and performing a second sensing operation on the memory cell which is determined to be in an off state after the first sensing operation, wherein the difference value between the voltage applied to the word line in the first sensing operation and the voltage applied to the word line in the second sensing operation is within a preset range, and the sensing time corresponding to the second sensing operation is not less than that corresponding to the first sensing operation. According to the technical scheme provided by the invention, the flash memory device can be read through two induction operations, so that the noise of the common source line is reduced, and the high accuracy of the reading operation is ensured.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a reading method and a flash memory device.
Background
NAND-type flash memory, a type of non-volatile memory, has become an important key component of mass storage devices due to its highly integrated nature. However, since the NAND flash memory has all the grounding terminals of the memory cells constituting the non-volatile memory cell array connected together through the common source line, the common source line noise is more and more affected and even causes a read operation error when the read operation is performed by the all bit line read method as the memory cell array is enlarged, and therefore, it is important to reduce the common source line noise when the read operation is performed.
Disclosure of Invention
In view of this, the present invention provides a reading method and a flash memory device, in which a first sensing operation is performed on all memory cells, a second sensing operation is performed on a memory cell determined to be in an off state, and the flash memory device is read through the two sensing operations, so as to reduce noise of a common source line and ensure high accuracy of the reading operation.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a reading method applied to a flash memory device including a nonvolatile semiconductor memory cell array, comprising:
judging whether all memory cells of the nonvolatile semiconductor memory cell array are read or not, and if so, applying voltage to corresponding word lines of all the memory cells to perform first induction operation;
and performing a second sensing operation on the memory cell which is determined to be in an off state after the first sensing operation, wherein the difference value between the voltage applied to the word line in the first sensing operation and the voltage applied to the word line in the second sensing operation is within a preset range, and the sensing time corresponding to the second sensing operation is not less than that corresponding to the first sensing operation.
Optionally, the voltage applied to the word line in the first sensing operation is the same as the voltage applied to the word line in the second sensing operation;
and the induction time corresponding to the first induction operation is shorter than the induction time corresponding to the second induction operation. Optionally, when it is determined that the nonvolatile semiconductor memory cell array is read but not all the memory cells and a preset number of memory cells are read, applying a voltage to a corresponding word line of the memory cells and performing a preset sensing operation on the preset number of memory cells, where the voltage applied to the word line during the preset sensing operation is the same as the voltage applied to the word line during the first sensing operation and the second sensing operation, and the sensing time corresponding to the preset sensing operation is not less than the sensing time corresponding to the second sensing operation.
Optionally, the preset number of storage units is half of all storage units, and the preset sensing time corresponding to the sensing operation is the same as the sensing time corresponding to the second sensing operation.
Optionally, the preset number of storage units is one fourth of all the storage units, and the sensing time corresponding to the preset sensing operation is not less than the sensing time corresponding to the second sensing operation.
Accordingly, the present invention also provides a flash memory device including a nonvolatile semiconductor memory cell array, further including:
a judging unit for judging whether or not to read all the memory cells of the nonvolatile semiconductor memory cell array;
the processing unit is used for applying voltage to corresponding word lines of all the memory cells to perform first sensing operation when judging that all the memory cells of the nonvolatile semiconductor memory cell array are read; and performing a second sensing operation on the memory cell which is determined to be in an off state after the first sensing operation, wherein the difference value between the voltage applied to the word line in the first sensing operation and the voltage applied to the word line in the second sensing operation is within a preset range, and the sensing time corresponding to the second sensing operation is not less than that corresponding to the first sensing operation.
Optionally, the voltage applied to the word line in the first sensing operation is the same as the voltage applied to the word line in the second sensing operation.
Optionally, when it is determined that the nonvolatile semiconductor memory cell array is read but not all the memory cells and a preset number of memory cells are read, the processing unit is configured to apply a voltage to the corresponding word lines of the memory cells and perform a preset sensing operation on the preset number of memory cells, where the voltage applied to the word lines during the preset sensing operation is the same as the voltage applied to the word lines during the first sensing operation and the second sensing operation, and the sensing time corresponding to the preset sensing operation is not less than the sensing time corresponding to the second sensing operation.
Optionally, the preset number of storage units is half of all the storage units, wherein the sensing time corresponding to the preset sensing operation is the same as the sensing time corresponding to the second sensing operation;
and the induction time corresponding to the first induction operation is shorter than the induction time corresponding to the second induction operation.
Optionally, the preset number of storage units is one fourth of all the storage units, and the sensing time corresponding to the preset sensing operation is not less than the sensing time corresponding to the second sensing operation.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a reading method and a flash memory device, wherein the reading method is applied to the flash memory device, the flash memory device comprises a nonvolatile semiconductor memory cell array, and the reading method comprises the following steps: judging whether all memory cells of the nonvolatile semiconductor memory cell array are read or not, and if so, applying voltage to corresponding word lines of all the memory cells to perform first induction operation; and performing a second sensing operation on the memory cell which is determined to be in an off state after the first sensing operation, wherein the difference value between the voltage applied to the word line in the first sensing operation and the voltage applied to the word line in the second sensing operation is within a preset range, and the sensing time corresponding to the second sensing operation is not less than that corresponding to the first sensing operation.
As can be seen from the above, in the technical solution provided by the present invention, two sensing operations are performed on the nonvolatile semiconductor memory cell array, first sensing operation is performed on all memory cells, and then second sensing operation is performed on the memory cell determined to be in the off state, wherein the first sensing operation time is shorter than the second sensing operation time. Because the first sensing time is short, only the memory cell with larger on-state current is judged to be in an on state, the rest memory cells with smaller on-state current are judged to be in an off state, and then the second sensing operation is carried out on the memory cells judged to be in the off state. Therefore, the technical scheme provided by the invention can read the flash memory device through two times of induction operation so as to reduce the noise of the common source line and ensure the high accuracy of the reading operation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a reading method according to an embodiment of the present application;
FIG. 2a is a schematic diagram of an LSB read operation according to an embodiment of the present disclosure;
FIG. 2b is a diagram illustrating an MSB read operation according to an embodiment of the present disclosure;
FIG. 3 is a flow chart of another reading method provided by the embodiments of the present application;
fig. 4 is a schematic structural diagram of a flash memory device according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, since the NAND type flash memory has all the memory cells constituting the nonvolatile memory cell array with their ground terminals connected together by the common source line, the influence of the common source line noise is increased and the read operation is even wrong when the read operation is performed by the all bit line read method as the memory cell array is enlarged, and therefore, it becomes more important to reduce the common source line noise when the read operation is performed.
Based on this, the embodiment of the application provides a reading method and a flash memory device, which includes performing a first sensing operation on all memory cells, performing a second sensing operation on the memory cells determined to be in an off state, and reading the flash memory device through the two sensing operations, so that noise of a common source line is reduced, and the accuracy of the reading operation is high. In order to achieve the above object, the technical solutions provided by the embodiments of the present application are described in detail below, specifically with reference to fig. 1 to 4.
Referring to fig. 1, a flow chart of a reading method provided in the present application is shown, where the reading method is applied to a flash memory device including a nonvolatile semiconductor memory cell array, and the reading method includes:
s1, determining whether to read all the memory cells of the nonvolatile semiconductor memory cell array;
s2, if yes, applying voltage to the corresponding word lines of all the memory cells to perform a first sensing operation;
and S3, performing a second sensing operation on the memory cell determined to be in the off state after the first sensing operation, wherein a difference between a voltage applied to the word line during the first sensing operation and a voltage applied to the word line during the second sensing operation is within a preset range, and a sensing time corresponding to the second sensing operation is not less than a sensing time corresponding to the first sensing operation.
As can be seen from the above, in the technical solution provided in the embodiment of the present application, two sensing operations are performed on the nonvolatile semiconductor memory cell array, first sensing operation is performed on all memory cells, and then second sensing operation is performed on the memory cell determined to be in the off state, where the first sensing operation time is shorter than the second sensing operation time. Because the first sensing time is short, only the memory cell with larger on-state current is judged to be in an on state, the other memory cells with smaller on-state current are judged to be in an off state, and then the memory cell judged to be in the off state is subjected to second sensing operation. The second sensing time is longer than the first sensing time and is within a specified range, so that the rest of the on-state storage units can be sensed to complete the whole reading operation. Therefore, the technical scheme provided by the embodiment of the application can read the flash memory device through two times of induction operation, so that the noise of the common source line is reduced, and the high accuracy of the reading operation is ensured.
In an embodiment of the present application, the voltage applied to the word line in the first sensing operation is the same as the voltage applied to the word line in the second sensing operation.
And preferably, the induction time corresponding to the first induction operation is shorter than the induction time corresponding to the second induction operation, so that the final induction is more accurate.
The following describes the reading method provided by the embodiment of the present application in detail with reference to fig. 2a and fig. 2 b. It should be noted that, one read operation includes three parts of bit line precharge, sensing and latching on the bit line, and the corresponding times correspond to Tpre, Tdev and Tsense, respectively, which is the same as the prior art, and therefore, redundant description is not repeated.
Referring to fig. 2a, for an LSB read operation provided in this embodiment of the present application, the times for the first sensing operation corresponding to bit line precharging, sensing and latching are Tpre1, Tdev1 and Tsense1, respectively, and the times for the second sensing operation corresponding to bit line precharging, sensing and latching are Tpre2, Tdev2 and Tsense2, respectively. In which Vrd2 is applied to the word line WL of the memory cell, a full LSB read operation includes two sense operations, a first sense operation and a second sense operation. The sensing time Tdev1 of the first sensing operation is less than the sensing time Tdev2 of the second sensing operation. Since the first sensing time is shorter than the second sensing time, only the memory cell with a large on-state current is determined to be in an on-state. And the second sensing will read out the remaining memory states as on-state memory cells on the basis of the first sensing. Also, since the number of bit lines that need to be precharged at the time of the second sensing operation is reduced, the bit line precharge time Tpre2 of the second sensing operation is less than the bit line precharge time Tpre1 of the first sensing operation.
Referring to fig. 2b, a schematic diagram of an MSB read operation provided in this embodiment of the present application includes two reads for the MSB read operation, and each read includes two sense operations, that is, the first read includes a first sense operation and a second sense operation, where the times of bit line precharge, sense and latch for the first sense operation in the first read correspond to Tpre3, Tdev3 and Tsense3, respectively, and the times of bit line precharge, sense and latch for the second sense operation correspond to Tpre4, Tdev4 and Tsense4, respectively; in the second reading, the times of the first sensing operation corresponding to the bit line precharging, sensing and latching are Tpre3 ', Tdev 3' and Tsense3 ', respectively, and the times of the second sensing operation corresponding to the bit line precharging, sensing and latching are Tpre 4', Tdev4 'and Tsense 4', respectively. In the method, a voltage Vrd1 is applied to the word line WL in the first reading, and a voltage Vrd3 is applied to the word line WL in the second reading, wherein the sensing time of the first sensing operation in each reading is shorter than that of the second sensing operation, and only the memory cell with larger on-state current is determined to be in the on-state because the first sensing time is short. And the second sensing is to read out the rest storage state as an on-state storage unit on the basis of the first sensing. Specifically, referring to fig. 3, a flowchart of another reading method provided in this embodiment of the present application is shown, where when it is determined that the nonvolatile semiconductor memory cell array is not read from all the memory cells and it is determined that a preset number of the memory cells are read, S4 applies a voltage to a word line corresponding to the memory cell, and performs a preset sensing operation on the preset number of the memory cells (where the preset number of the memory cells are sensed by controlling a bit line), where a voltage applied to the word line during the preset sensing operation is the same as a voltage applied to the word line during the first sensing operation and the second sensing operation, and a sensing time corresponding to the preset sensing operation is not shorter than a sensing time corresponding to the second sensing operation.
The number of the partial memory cells may be 1/2, that is, the preset number of the memory cells is half of the total memory cells, and the sensing time corresponding to the preset sensing operation is the same as the sensing time corresponding to the second sensing operation.
In addition, the number of the partial memory cells may also be 1/4, that is, the preset number of memory cells is one fourth of the total memory cells, wherein the preset sensing time corresponding to the sensing operation is not less than the second sensing time corresponding to the sensing operation.
It should be noted that, some memory cells may also be other numbers of memory cells, and this application is not specifically limited, and needs to be specifically designed according to practical applications, and the sensing time corresponding to the preset sensing operation is set to be not less than the sensing time corresponding to the second sensing operation, so as to ensure that the noise of the common source line is low, and ensure that the reading accuracy is high.
Accordingly, an embodiment of the present application further provides a flash memory device, and referring to fig. 4, a schematic structural diagram of the flash memory device provided in the embodiment of the present application is shown, where the flash memory device includes a nonvolatile semiconductor memory cell array, and further includes:
a judging unit 100 for judging whether or not to read all the memory cells of the nonvolatile semiconductor memory cell array;
and a processing unit 200, when determining to read all the memory cells of the nonvolatile semiconductor memory cell array, the processing unit 200 is configured to apply a voltage to corresponding word lines of all the memory cells to perform a first sensing operation; and performing a second sensing operation on the memory cell which is determined to be in an off state after the first sensing operation, wherein the difference value between the voltage applied to the word line in the first sensing operation and the voltage applied to the word line in the second sensing operation is within a preset range, and the sensing time corresponding to the second sensing operation is not less than that corresponding to the first sensing operation.
WL <0> to WL < m > are word lines of the flash memory device, S1 to S4 are bit lines, SSL is a gate terminal control line of a switching tube connected to the bit lines, GSL is a gate terminal control line of a switching tube connected to the common source line GL, and each bit line is connected to a bit line detection circuit.
In an embodiment of the present application, the voltage applied to the word line in the first sensing operation is the same as the voltage applied to the word line in the second sensing operation.
And preferably, the induction time corresponding to the first induction operation is shorter than the induction time corresponding to the second induction operation, so that the final induction is more accurate.
In an embodiment of the present application, a portion of the memory cells may also be read. Specifically, when it is determined that the nonvolatile semiconductor memory cell array is not read from all the memory cells and a preset number of memory cells are read, the processing unit 200 is configured to apply a voltage to the corresponding word lines of the memory cells and perform a preset sensing operation on the preset number of memory cells, where the voltage applied to the word lines during the preset sensing operation is the same as the voltage applied to the word lines during the first sensing operation and the second sensing operation, and the sensing time corresponding to the preset sensing operation is not less than the sensing time corresponding to the second sensing operation.
The number of the partial memory cells may be 1/2, that is, the preset number of the memory cells is half of the total memory cells, and the sensing time corresponding to the preset sensing operation is the same as the sensing time corresponding to the second sensing operation.
In addition, the number of the partial memory cells may also be 1/4, the preset number of the memory cells is one fourth of the total memory cells, and the sensing time corresponding to the preset sensing operation is not less than the sensing time corresponding to the second sensing operation.
It should be noted that, some memory cells may also be other numbers of memory cells, and this application is not specifically limited, and needs to be specifically designed according to practical applications, and the sensing time corresponding to the preset sensing operation is set to be not less than the sensing time corresponding to the second sensing operation, so as to ensure that the noise of the common source line is low, and ensure that the reading accuracy is high.
An embodiment of the present application provides a reading method and a flash memory device, where the reading method is applied to a flash memory device, and the flash memory device includes a nonvolatile semiconductor memory cell array, and includes: judging whether all memory cells of the nonvolatile semiconductor memory cell array are read or not, and if so, applying voltage to corresponding word lines of all the memory cells to perform first induction operation; and performing a second sensing operation on the memory cell which is determined to be in an off state after the first sensing operation, wherein the difference value between the voltage applied to the word line in the first sensing operation and the voltage applied to the word line in the second sensing operation is within a preset range, and the sensing time corresponding to the second sensing operation is not less than that corresponding to the first sensing operation.
As can be seen from the above, in the technical solution provided in the embodiment of the present application, two sensing operations are performed on the nonvolatile semiconductor memory cell array, first sensing operation is performed on all memory cells, and then second sensing operation is performed on the memory cell determined to be in the off state, where the first sensing operation time is shorter than the second sensing operation time. Because the first sensing time is short, only the memory cell with larger on-state current is judged to be in an on state, the rest memory cells with smaller on-state current are judged to be in an off state, and then the second sensing operation is carried out on the memory cells judged to be in the off state. Therefore, the technical scheme provided by the embodiment of the application can read the flash memory device through two times of induction operation, so that the noise of the common source line is reduced, and the high accuracy of the reading operation is ensured.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A reading method applied to a flash memory device including a nonvolatile semiconductor memory cell array, comprising:
judging whether all memory cells of the nonvolatile semiconductor memory cell array are read or not, and if so, applying voltage to corresponding word lines of all the memory cells to perform first induction operation;
performing a second sensing operation on the memory cell which is determined to be in an off state after the first sensing operation, wherein the voltage applied to the word line in the first sensing operation is the same as the voltage applied to the word line in the second sensing operation;
the induction time corresponding to the first induction operation is shorter than the induction time corresponding to the second induction operation;
and when the nonvolatile semiconductor memory cell array is judged not to be read from all the memory cells and a preset number of memory cells are judged to be read, applying voltage to corresponding word lines of the memory cells and carrying out preset induction operation on the preset number of memory cells, wherein the voltage applied to the word lines in the preset induction operation is the same as the voltage applied to the word lines in the first induction operation and the second induction operation, and the corresponding induction time of the preset induction operation is not less than the corresponding induction time of the second induction operation.
2. The reading method according to claim 1, wherein the predetermined number of memory cells is half of the total memory cells, and the sensing time corresponding to the predetermined sensing operation is the same as the sensing time corresponding to the second sensing operation.
3. The reading method according to claim 1, wherein the predetermined number of memory cells is one fourth of the total memory cells, and the sensing time corresponding to the predetermined sensing operation is not less than the sensing time corresponding to the second sensing operation.
4. A flash memory device comprising an array of non-volatile semiconductor memory cells, further comprising:
a judging unit for judging whether or not to read all the memory cells of the nonvolatile semiconductor memory cell array;
the processing unit is used for applying voltage to corresponding word lines of all the memory cells to perform first sensing operation when judging that all the memory cells of the nonvolatile semiconductor memory cell array are read; performing a second sensing operation on the memory cell which is determined to be in an off state after the first sensing operation, wherein the voltage applied to the word line in the first sensing operation is the same as the voltage applied to the word line in the second sensing operation;
the induction time corresponding to the first induction operation is shorter than the induction time corresponding to the second induction operation;
and when the nonvolatile semiconductor memory cell array is judged to be read not to be all the memory cells and the preset number of memory cells are judged to be read, the processing unit is used for applying voltage to the corresponding word lines of the memory cells and carrying out preset induction operation for the preset number of the memory cells, wherein the voltage applied to the word lines in the preset induction operation is the same as the voltage applied to the word lines in the first induction operation and the second induction operation, and the corresponding induction time of the preset induction operation is not less than the corresponding induction time of the second induction operation.
5. The flash memory device of claim 4, wherein the predetermined number of memory cells is half of the total number of memory cells, and wherein the predetermined sensing time is the same as the second sensing time.
6. The flash memory device of claim 4, wherein the predetermined number of memory cells is one fourth of the total number of memory cells, and wherein the predetermined sensing time is not less than the second sensing time.
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| CN106356095A (en) * | 2016-09-13 | 2017-01-25 | 中国科学院微电子研究所 | Read operation method and device for nonvolatile storage |
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| CN101084556A (en) * | 2002-09-24 | 2007-12-05 | 桑迪士克股份有限公司 | Non-volatile memory and method with improved sensing |
| CN106356095A (en) * | 2016-09-13 | 2017-01-25 | 中国科学院微电子研究所 | Read operation method and device for nonvolatile storage |
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