CN106935646B - 埋藏沟道晶体管及其形成方法 - Google Patents

埋藏沟道晶体管及其形成方法 Download PDF

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CN106935646B
CN106935646B CN201511021410.5A CN201511021410A CN106935646B CN 106935646 B CN106935646 B CN 106935646B CN 201511021410 A CN201511021410 A CN 201511021410A CN 106935646 B CN106935646 B CN 106935646B
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type
impurity ions
doped
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CN106935646A (zh
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邱慈云
克里夫·德劳利
辜良智
江宇雷
余达强
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to EP16207183.1A priority patent/EP3188226A1/en
Priority to US15/394,592 priority patent/US10062704B2/en
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Abstract

一种埋藏沟道晶体管及其形成方法，所述形成方法包括：提供半导体衬底，在所述半导体衬底内形成阱区；在阱区内形成反型掺杂区，反型掺杂区中掺杂的类型与阱区中掺杂的类型相反，且反型掺杂区的深度小于阱区的深度；在所述反型掺杂区的上方的半导体衬底表面上形成栅极结构，所述栅极结构包括栅介质层和位于栅介质层上的栅电极，所述栅电极的中掺杂有杂质离子，所述栅电极中掺杂的类型与阱区的类型相同；在所述栅极结构两侧的半导体衬底内形成源区和漏区，所述源区和漏区中掺杂类型与阱区中的杂质离子类型相反，源区和漏区的深度小于阱区的深度且大于反型掺杂区的深度。本发明方法形成的晶体管防止了闪烁噪音的产生，提高了器件的性能。

Description

埋藏沟道晶体管及其形成方法
技术领域
本发明涉及半导体制作领域，特别涉及一种埋藏沟道晶体管及其形成方法。
背景技术
金属-氧化物-半导体(MOS)晶体管是半导体制造中的最基本器件，其广泛适用于各种集成电路中，根据主要载流子以及制造时的掺杂类型不同，分为NMOS和PMOS晶体管。
现有技术提供了一种MOS晶体管的制作方法。包括：提供半导体基底，在所述半导体基底形成隔离结构，所述隔离结构之间的半导体基底为有源区，在所述有源区内形成阱区(未示出)；通过第一离子注入在阱区表面掺杂杂质离子，以调节后续形成的晶体管的阈值电压；在所述隔离结构之间的半导体基底上依次形成栅介质层和栅电极，所述栅介质层和栅电极构成栅极结构；进行氧化工艺，形成覆盖所述栅极结构的氧化层；进行浅掺杂离子注入，在栅极结构两侧的半导体基底内形成源/漏延伸区；以所述栅极结构为掩膜，对栅极结构两侧的阱区进行深掺杂离子注入，深掺杂离子注入的能量和剂量大于浅掺杂离子注入的能量和剂量，在栅极结构两侧的阱区内形成源区和漏区，所述源区和漏区的深度大于源/漏延伸区的深度。
但是，现有技术形成的晶体管的性能仍有待提升。
发明内容
本发明解决的问题是怎样防止现有的晶体管的闪烁噪音的产生。
为解决上述问题，本发明提供了一种埋藏沟道晶体管的形成方法，包括：
提供半导体衬底，在所述半导体衬底内形成阱区；在所述阱区内形成反型掺杂区，所述反型掺杂区中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相反，且反型掺杂区的深度小于阱区的深度；在所述反型掺杂区的上方的半导体衬底表面上形成栅极结构，所述栅极结构包括栅介质层和位于栅介质层上的栅电极，所述栅电极的中掺杂有杂质离子，所述栅电极中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相同；在所述栅极结构两侧的半导体衬底内形成源区和漏区，所述源区和漏区中掺杂的杂质离子的类型与阱区中的杂质离子类型相反，源区和漏区的深度小于阱区的深度且大于反型掺杂区的深度。
可选的，当形成的晶体管为N型的晶体管时，所述阱区中掺杂的杂质离子中的杂质离子类型为P型，反型掺杂区中掺杂的杂质离子的类型为N型，栅电极中掺杂的杂质离子的类型为P型，源区和漏区中掺杂的杂质离子的类型为N型。
可选的，当形成的晶体管为P型的晶体管时，所述阱区中掺杂的杂质离子中的杂质离子类型为N型，反型掺杂区中掺杂的杂质离子的类型为P型，栅电极中掺杂的杂质离子的类型为N型，源区和漏区中掺杂的杂质离子的类型为P型。
可选的，所述杂质离子类型为N型时，所述杂质离子为磷离子、砷离子或锑离子中的一种或几种；所述杂质离子类型为P型时，所述杂质离子为硼离子、镓离子或铟离子中的一种或几种。
可选的，所述反型掺杂区的形成工艺为离子注入。
可选的，晶体管工作时，所述反型掺杂区与阱区之间形成的PN结作为埋藏沟道。
可选的，所述反型掺杂区的宽度大于栅电极的宽度。
可选的，所述栅介质层和栅电极的形成过程为：在所述半导体衬底表面上形成栅介质材料层；在所述栅介质材料层表面形成栅电极材料层，所述栅电极材料层中掺杂有掺杂离子；在所述栅电极材料层表面形成图形化的硬掩膜层；以所述图形化的硬掩膜层为掩膜，刻蚀所述栅电极材料层和栅介质材料层，在半导体衬底表面上形成栅介质层和栅电极。
可选的，通过离子注入工艺在栅电极材料层中掺杂杂质离子，或者通过原位自掺杂工艺在栅电极材料层中掺杂杂质离子。
可选的，所述栅极结构还包括位于栅介质层和栅电极的两侧侧壁的侧墙。
可选的，所述源区和漏区的形成过程为：以硬掩膜层和栅极结构为掩膜，对栅极结构两侧的半导体衬底进行离子注入，在栅极结构两侧的半导体衬底内形成源区和漏区。
可选的，所述源区和漏区的形成过程为：形成覆盖所述半导体衬底、栅极结构上的硬掩膜层和栅极结构的半导体材料层；刻蚀去除硬掩膜层表面上以及半导体衬底上的部分半导体材料层，在所述侧墙的表面以及侧墙两侧的半导体衬底表面上形成源漏区材料层；对所述源漏区材料层以及侧墙两侧的半导体衬底进行离子注入，形成源区和漏区。
可选的，所述半导体材料层的材料为多晶硅、硅锗或碳化硅。
可选的，在形成栅介质层和栅电极之前，还包括：在所述阱区内形成防穿通区，所述防穿通区中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相同，且防穿通区深度大于反型掺杂区的深度。
可选的，所述栅电极的杂质离子的浓度与反型掺杂区杂质离子的浓度正相关。
本发明还提供了一种埋藏沟道晶体管，包括：
半导体衬底，所述半导体衬底内形成有阱区；位于所述阱区内的反型掺杂区，所述反型掺杂区中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相反，且反型掺杂区的深度小于阱区的深度；位于所述反型掺杂区的上方的半导体衬底表面的形成栅极结构，所述栅极结构包括栅介质层和位于栅介质层上的栅电极，所述栅电极的中掺杂有杂质离子，所述栅电极中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相同；位于所述栅极结构两侧的半导体衬底内的源区和漏区，所述源区和漏区中掺杂的杂质离子的类型与阱区中的杂质离子类型相反，源区和漏区的深度小于阱区的深度且大于反型掺杂区的深度。
可选的，所述晶体管为N型的晶体管，所述阱区中掺杂的杂质离子中的杂质离子类型为P型，反型掺杂区中掺杂的杂质离子的类型为N型，栅电极中掺杂的杂质离子的类型为P型，源区和漏区中掺杂的杂质离子的类型为N型。
可选的，所述晶体管为P型的晶体管，所述阱区中掺杂的杂质离子中的杂质离子类型为N型，反型掺杂区中掺杂的杂质离子的类型为P型，栅电极中掺杂的杂质离子的类型为N型，源区和漏区中掺杂的杂质离子的类型为P型
与现有技术相比，本发明的技术方案具有以下优点：
本发明的掩埋沟道晶体管的形成方法，在形成阱区后，在阱区中形成反型掺杂区，反型掺杂区的深度小于阱区的深度，所述形成反型掺杂区位于半导体衬底的表面与阱区的底部之间，即反型掺杂区是位于半导体衬底的内部，反型掺杂区上方和下方均是与其掺杂类型相反的阱区，反型掺杂区与阱区的接触区域会形成PN结，后续在形成栅电极后，当在栅电极上施加工作电压时，PN结附近区域会形成反型区，由于PN结附近区域的势垒要小于半导体衬底表面的势垒，因而载流子会通过PN结附近区域形成的反型区传输，因而，本发明形成的晶体管载流子的传输通道是位于半导体衬底的内部，载流子的传输不会受到半导体衬底表面存在的缺陷的影响，防止了闪烁噪音的产生，提高了器件的性能；另外，所述栅电极中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相同，即栅电极中掺杂的杂质离子的类型与晶体管的类型相反，这与常规的晶体管的栅电极掺杂类型与晶体管的类型相同存在明显不同，本发明申请这样做的目的是，由于栅电极底部的阱区中形成有反型掺杂区，反型掺杂区的掺杂类型与阱区掺杂类型相同，反型掺杂区的存在会对晶体管的阈值电压产生较大的影响，栅电极中掺杂的杂质离子与反型掺杂区中掺杂杂质离子类型相反(或者与阱区中掺杂的杂质离子的类型相同)，以调节形成的晶体管的阈值电压。
本发明的掩埋沟道晶体管，反型掺杂区是位于半导体衬底的内部，反型掺杂区上方和下方均是与其掺杂类型相反的阱区，反型掺杂区与阱区的接触区域会形成PN结，后续在形成栅电极后，当在栅电极上施加工作电压时，PN结附近区域会形成反型区，由于PN结附近区域的势垒要小于半导体衬底表面的势垒，因而载流子会通过PN结附近区域形成的反型区传输，因而，本发明形成的晶体管载流子的传输通道是位于半导体衬底的内部，载流子的传输不会受到半导体衬底表面存在的缺陷的影响，防止了闪烁噪音的产生，提高了器件的性能；另外，栅电极中掺杂的杂质离子与反型掺杂区中掺杂杂质离子类型相反(或者与阱区中掺杂的杂质离子的类型相同)，以调节反型掺杂区对晶体管阈值电压的影响。
附图说明
图1～9为本发明实施例埋藏沟道晶体管的形成过程的结构示意图。
具体实施方式
如背景技术所言，现有技术形成的晶体管的性能仍有待提升，比如现有的晶体管在工作时存在1/f噪音或闪烁噪音(flicker noise)，1/f噪音或闪烁噪音的产生跟导电沟道的光滑程度具有较大的关联性，而现有的晶体管形成的导电沟道基本为表面沟道，在制作工艺中，衬底的表面的光滑性很难保证，不可避免的衬底表面会存在缺陷，缺陷的存在会影响载流子的传输，因而现有的晶体管在工作时，易产生闪烁噪音，影响了器件的性能。
为此，本发明提供了一种掩埋沟道晶体管及其形成方法，通过在阱区中形成反型掺杂区，晶体管在工作时载流子会沿着反型掺杂区与阱区之间形成PN附近区域传输，因而，本发明形成的晶体管载流子的传输通道是位于半导体衬底的内部，载流子的传输不会受到半导体衬底表面存在的缺陷的影响，防止了闪烁噪音的产生，提高了器件的性能；另外，栅电极中掺杂的杂质离子与反型掺杂区中掺杂杂质离子类型相反(或者与阱区中掺杂的杂质离子的类型相同)，以调节反型掺杂区对晶体管阈值电压的影响。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。在详述本发明实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图1～9为本发明实施例埋藏沟道晶体管的形成过程的结构示意图。
参考图1，提供半导体衬底200，在所述半导体衬底200内形成阱区203。
所述半导体衬底200的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中，所述半导体衬底200的材料为硅。
所述阱区203通过离子注入工艺形成，根据形成的晶体管的类型不同，所述阱区203中掺杂不同类型的杂质离子，具体的，当形成的晶体管为N型的晶体管时，所述阱区中掺杂的杂质离子中的杂质离子类型为P型，P型的杂质离子可以为硼离子、镓离子或铟离子中的一种或几种；当形成的晶体管为P型的晶体管时，所述阱区中掺杂的杂质离子中的杂质离子类型为N型，N型的杂质离子可以为磷离子、砷离子或锑离子中的一种或几种。
所述半导体衬底200中还形成有若干浅沟槽隔离结构201，所述浅沟槽隔离结构201用于隔离相邻的有源区。在一实施例中，所述浅沟槽隔离结构201形成过程为：刻蚀所述半导体衬底，形成凹槽；在凹槽中填充满隔离材料，形成浅沟槽隔离结构。在另一实施例中，在凹槽中填充隔离材料之前，在所述凹槽的侧壁和底部表面上还形成衬垫层，在形成衬垫层后在衬垫层上形成填充凹槽的隔离材料层。所述衬垫层的材料可以氧化硅，所述隔离材料可以为氧化硅、氮氧化硅或碳氧化硅。
参考图2，在所述阱区203内形成反型掺杂区204，所述反型掺杂区204中掺杂的杂质离子的类型与阱区203中掺杂的杂质离子的类型相反，且反型掺杂区204的深度小于阱区203的深度。
所述反型掺杂区204的形成工艺为离子注入，所述反型掺杂区204中掺杂的杂质离子的类型与阱区203中掺杂的杂质离子的类型相反，具体的，当形成的晶体管为N型的晶体管时，所述阱区203中掺杂的杂质离子中的杂质离子类型为P型，反型掺杂区204中掺杂的杂质离子的类型为N型，N型的杂质离子可以为磷离子、砷离子或锑离子中的一种或几种；当形成的晶体管为P型的晶体管时，所述阱区203中掺杂的杂质离子中的杂质离子类型为N型，反型掺杂区204中掺杂的杂质离子的类型为P型，P型的杂质离子可以为硼离子、镓离子或铟离子中的一种或几种。
反型掺杂区204的深度小于阱区203的深度，所述形成反型掺杂区204位于半导体衬底200的表面与阱区204的底部之间，且反型掺杂区204距离半导体衬底200的表面相对于距离阱区204的底部的距离较近，因而反型掺杂区204是位于半导体衬底200的内部，反型掺杂区204上方和下方均是与其掺杂类型相反的阱区，反型掺杂区204与阱区204的接触区域会形成PN结，后续在形成栅电极后，当在栅电极上施加工作电压时，PN结附近区域会形成反型区，由于PN结附近区域的势垒要小于半导体衬底表面的势垒，因而载流子会通过PN结附近区域形成的反型区传输，因而，本发明形成的晶体管载流子的传输通道是位于半导体衬底的内部，载流子的传输不会受到半导体衬底表面存在的缺陷的影响，防止了闪烁噪音的产生，提高了器件的性能。需要说明的是，本发明中的指反型掺杂区204深度是指反型掺杂区204的底部与半导体衬底200表面的垂直距离，阱区203的深度是指阱区203的底部与半导体衬底200表面的垂直距离，后续形成的防穿通区和源区和漏区的深度定义类似。
所述反型掺杂区204的宽度大于后续形成的栅电极的宽度。
在形成栅介质层和栅电极之前，还包括：在所述阱区203内形成防穿通区205，所述防穿通区205中掺杂的杂质离子的类型与阱区203中掺杂的杂质离子的类型相同，且防穿通区205深度大于反型掺杂区204的深度小于阱区203的深度。在一实施例中，当形成的晶体管为N型的晶体管时，所述阱区203中掺杂的杂质离子中的杂质离子类型为P型，所述防穿通区205中掺杂的杂质离子的类型也为P型，P型的杂质离子可以为硼离子、镓离子或铟离子中的一种或几种；在另一实施例中，当形成的晶体管为P型的晶体管时，所述阱区203中掺杂的杂质离子中的杂质离子类型为N型，反型掺杂区204中掺杂的杂质离子的类型为N型，N型的杂质离子可以为磷离子、砷离子或锑离子中的一种或几种。
结合参考图3和图4，在所述反型掺杂区204的上方的半导体衬底200表面上形成栅极结构，所述栅极结构包括栅介质层208和位于栅介质层208上的栅电极209，所述栅电极209的中掺杂有杂质离子，所述栅电极209中掺杂的杂质离子的类型与阱区203中掺杂的杂质离子的类型相同。
所述栅介质层208和栅电极209的形成过程为：在所述半导体衬底200表面上形成栅介质材料层205；在所述栅介质材料层205表面形成栅电极材料层206，所述栅电极材料层206中掺杂有掺杂离子；在所述栅电极材料层206表面形成图形化的硬掩膜层207；以所述图形化的硬掩膜层207为掩膜，刻蚀所述栅电极材料层206和栅介质材料层205，在半导体衬底200表面上形成栅介质层208和栅电极209。
所述栅介质层205的材料为氧化硅，可以通过热氧化硅工艺或化学气相沉积工艺形成所述栅介质层。所述栅电极材料层206的材料为多晶硅，所述栅电极材料层206的形成工艺可以为化学气相沉积工艺。
可以通过离子注入工艺在栅电极材料层206中掺杂杂质离子，或者在化学气相沉积工艺形成栅电极材料层206时，通过原位自掺杂工艺在栅电极材料层206中掺杂杂质离子。栅电极材料层206掺杂的杂质离子类型和浓度即为形成的栅电极209中掺杂的杂质离子的类型和浓度。
所述栅电极209中掺杂的杂质离子的类型与阱区203中掺杂的杂质离子的类型相同，即栅电极209中掺杂的杂质离子的类型与晶体管的类型相反，这与常规的晶体管的栅电极掺杂类型与晶体管的类型相同存在明显不同，本发明申请这样做的目的是，由于栅电极底部的阱区203中形成有反型掺杂区204，反型掺杂区204的掺杂类型与阱区203掺杂类型相同，反型掺杂区204的存在会对晶体管的阈值电压产生较大的影响，栅电极209中掺杂的杂质离子与反型掺杂区204中掺杂杂质离子类型相反(或者与阱区203中掺杂的杂质离子的类型相同)，以调节形成的晶体管的阈值电压。
所述栅电极209的杂质离子的浓度与反型掺杂区204的杂质离子的浓度正相关，即反型掺杂区204中的杂质离子浓度越大，相应的栅电极209中掺杂的杂质离子的浓度越大。
所述图形化的硬掩膜层207可以为单层或多层(≥2层)堆叠结构，图形化的硬掩膜层207的材料为氮化硅、氮氧化硅或碳化硅。
参考图5，在所述栅电极209和栅介质层208的两侧侧壁表面上形成侧墙210。
所述侧墙210的形成过程为：形成覆盖所述半导体衬底表面、栅电极209和栅介质层208的两侧侧壁表面以及图形化的硬掩膜层207的侧壁和顶部表面的侧墙材料层；采用无掩膜等离子体刻蚀工艺刻蚀所述侧墙材料层，在所述栅电极209和栅介质层208的两侧侧壁表面上形成侧墙210，所述侧墙还覆盖图形化的硬掩膜层207侧两侧侧壁。
所述侧墙210作为栅极结构的一部分。
所述侧墙210的材料可以为氧化硅、氮化硅、氮氧化硅、氮碳化硅。
所述侧墙210可以为单层或多层(≥2层)堆叠结构，在一实施例中，所述侧墙210为双层堆叠结构，包括位于栅电极209和栅介质层208的两侧侧壁表面上的第一侧墙，和位于第一侧墙表面的第二侧墙，第一侧墙和第二侧墙的材料不相同。
结合参考图7和图8，在所述栅极结构两侧的半导体衬底内形成源区和漏区，所述源区和漏区中掺杂的杂质离子的类型与阱区中的杂质离子类型相反，源区和漏区的深度小于阱区的深度且大于反型掺杂区的深度。
本实施例中，所述源区和漏区的形成过程为：形成覆盖所述半导体衬底、栅极结构上的硬掩膜层207和栅极结构的半导体材料层211；刻蚀去除硬掩膜层207表面上以及半导体衬底200上的部分半导体材料层，在所述侧墙210的表面以及侧墙210两侧的半导体衬底200表面上形成源漏区材料层213；对所述源漏区材料层213以及侧墙210两侧的半导体衬底200进行离子注入，形成源区和漏区，所述形成源区和漏区包括位于侧墙210的表面以及侧墙210两侧的半导体衬底200表面掺杂有杂质离子的源漏区材料层213和位于侧墙210两侧的半导体衬底200内的掺杂区212。
所述半导体材料层211的材料可以为多晶硅、硅锗或碳化硅
本发明实施例中，所述源区和漏区包括位于侧墙210的表面以及侧墙210两侧的半导体衬底200表面掺杂有杂质离子的源漏区材料层213和位于侧墙210两侧的半导体衬底200内的与源漏区材料层接触的掺杂区212，由于源漏区材料层213部分位于半导体衬底200表面上，部分位于侧墙210的表面上，源漏区材料层213为后续形成与源漏区电连接的金属插塞提供了足够的接触空间，并且为晶体管的导通提供了足够的载流子，因而本发明的源区和漏区在半导体衬底上占据的横向尺寸相对于现有晶体管的源区和漏区占据的横向尺寸可以较小，因而可以提高器件的集成度。
在其他实施例中，所述源漏区材料层213除了部分位于半导体衬底200表面上，部分位于侧墙210的表面上还可以有部分位于浅沟槽隔离结构201的表面上，在减小源区和漏区占据的横向尺寸的同时，充分利用浅沟槽隔离结构上的空间，进一步有利于后续形成与源区和漏区电连接的插塞。
所述形成的掺杂区212的深度大于反型掺杂区201的深度小于防穿通区205和阱区203的深度。
还包括：去除所述图形化的硬掩膜层207；形成覆盖所述半导体衬底200、源区和漏区、以及栅极结构的介质层；在介质层中形成分别与源区、漏区和栅电极209电连接的金属插塞。
在本发明的其他实施例中，请参考图9，所述源区和漏区的形成过程为：以硬掩膜层207和栅极结构为掩膜，对栅极结构两侧的半导体衬底200进行离子注入，在栅极结构两侧的半导体衬底200内形成源区和漏区214。
本发明实施例中还提供了一种埋藏沟道晶体管，请参考图8，包括：
半导体衬底200，所述半导体衬底内形成有阱区203；
位于所述阱区203内的反型掺杂区204，所述反型掺杂区204中掺杂的杂质离子的类型与阱区203中掺杂的杂质离子的类型相反，且反型掺杂区204的深度小于阱区203的深度；
位于所述反型掺杂区204的上方的半导体衬底200表面的栅极结构，所述栅极结构包括栅介质层208和位于栅介质层208上的栅电极209，所述栅电极209的中掺杂有杂质离子，所述栅电极209中掺杂的杂质离子的类型与阱区203中掺杂的杂质离子的类型相同；
位于所述栅极结构两侧的半导体衬底内的源区和漏区，所述源区和漏区中掺杂的杂质离子的类型与阱区中的杂质离子类型相反，源区和漏区的深度小于阱区的深度且大于反型掺杂区的深度。
在一实施例中，所述晶体管为N型的晶体管，所述阱区中掺杂的杂质离子中的杂质离子类型为P型，反型掺杂区中掺杂的杂质离子的类型为N型，栅电极中掺杂的杂质离子的类型为P型，源区和漏区中掺杂的杂质离子的类型为N型。
在另一实施例中，所述晶体管为P型的晶体管，所述阱区中掺杂的杂质离子中的杂质离子类型为N型，反型掺杂区中掺杂的杂质离子的类型为P型，栅电极中掺杂的杂质离子的类型为N型，源区和漏区中掺杂的杂质离子的类型为P型。
所述栅极结构还包括位于栅介质层208和栅电极209两侧侧壁表面的侧墙210。
所述源区和漏区包括位于侧墙210的表面以及侧墙210两侧的半导体衬底200表面掺杂有杂质离子的源漏区材料层213和位于侧墙210两侧的半导体衬底200内的与源漏区材料层接触的掺杂区212。
在另一实施例中，请参考图9，所述源区和漏区214直接位于栅极结构两侧的半导体衬底内。
需要说明的是，关于埋藏沟道晶体管其他限定或描述请参考前述埋藏沟道晶体管形成过程部分的相关限定或描述，在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (16)

1.一种埋藏沟道晶体管的形成方法，其特征在于，包括：
提供半导体衬底，在所述半导体衬底内形成阱区；
在所述阱区内形成反型掺杂区，所述反型掺杂区中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相反，且反型掺杂区的深度小于阱区的深度；
在所述阱区内形成防穿通区，所述防穿通区中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相同，且所述防穿通区中掺杂的杂质离子的类型与反型掺杂区中掺杂的杂质离子的类型相反；所述防穿通区深度大于后续步骤中形成的源区和漏区的深度，且与源区和漏区不接触；
在所述反型掺杂区的上方的半导体衬底表面上形成栅极结构，所述栅极结构包括栅介质层、位于栅介质层上的栅电极以及位于栅介质层和栅电极的两侧侧壁的侧墙，所述栅电极的中掺杂有杂质离子，所述栅电极中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相同；
在所述栅极结构两侧的半导体衬底内形成源区和漏区，所述源区和漏区中掺杂的杂质离子的类型与阱区中的杂质离子类型相反，源区和漏区的深度小于阱区的深度且大于反型掺杂区的深度；
所述源区和漏区包括位于侧墙的表面以及侧墙两侧的半导体衬底表面掺杂有杂质离子的源漏区材料层和位于侧墙两侧的半导体衬底内的与源漏区材料层接触的掺杂区，所述源漏区材料层为后续形成与源漏区电连接的金属插塞提供接触空间，并且为晶体管的导通提供载流子，因而减小源区和漏区在半导体衬底上占据的横向尺寸。
2.如权利要求1所述的埋藏沟道晶体管的形成方法，其特征在于，当形成的晶体管为N型的晶体管时，所述阱区中掺杂的杂质离子中的杂质离子类型为P型，反型掺杂区中掺杂的杂质离子的类型为N型，栅电极中掺杂的杂质离子的类型为P型，源区和漏区中掺杂的杂质离子的类型为N型。
3.如权利要求1所述的埋藏沟道晶体管的形成方法，其特征在于，当形成的晶体管为P型的晶体管时，所述阱区中掺杂的杂质离子中的杂质离子类型为N型，反型掺杂区中掺杂的杂质离子的类型为P型，栅电极中掺杂的杂质离子的类型为N型，源区和漏区中掺杂的杂质离子的类型为P型。
4.如权利要求2或3所述的埋藏沟道晶体管的形成方法，其特征在于，所述杂质离子类型为N型时，所述杂质离子为磷离子、砷离子或锑离子中的一种或几种；所述杂质离子类型为P型时，所述杂质离子为硼离子、镓离子或铟离子中的一种或几种。
5.如权利要求1所述的埋藏沟道晶体管的形成方法，其特征在于，所述反型掺杂区的形成工艺为离子注入。
6.如权利要求1所述的埋藏沟道晶体管的形成方法，其特征在于，晶体管工作时，所述反型掺杂区与阱区之间形成的PN结作为埋藏沟道。
7.如权利要求1所述的埋藏沟道晶体管的形成方法，其特征在于，所述反型掺杂区的宽度大于栅电极的宽度。
8.如权利要求1所述的埋藏沟道晶体管的形成方法，其特征在于，所述栅介质层和栅电极的形成过程为：在所述半导体衬底表面上形成栅介质材料层；在所述栅介质材料层表面形成栅电极材料层，所述栅电极材料层中掺杂有掺杂离子；在所述栅电极材料层表面形成图形化的硬掩膜层；以所述图形化的硬掩膜层为掩膜，刻蚀所述栅电极材料层和栅介质材料层，在半导体衬底表面上形成栅介质层和栅电极。
9.如权利要求8所述的埋藏沟道晶体管的形成方法，其特征在于，通过离子注入工艺在栅电极材料层中掺杂杂质离子，或者通过原位自掺杂工艺在栅电极材料层中掺杂杂质离子。
10.如权利要求8所述的埋藏沟道晶体管的形成方法，其特征在于，所述源区和漏区的形成过程为：以硬掩膜层和栅极结构为掩膜，对栅极结构两侧的半导体衬底进行离子注入，在栅极结构两侧的半导体衬底内形成源区和漏区。
11.如权利要求8所述的埋藏沟道晶体管的形成方法，其特征在于，所述源区和漏区的形成过程为：形成覆盖所述半导体衬底、栅极结构上的硬掩膜层和栅极结构的半导体材料层；刻蚀去除硬掩膜层表面上以及半导体衬底上的部分半导体材料层，在所述侧墙的表面以及侧墙两侧的半导体衬底表面上形成源漏区材料层；对所述源漏区材料层以及侧墙两侧的半导体衬底进行离子注入，形成源区和漏区。
12.如权利要求11所述的埋藏沟道晶体管的形成方法，其特征在于，所述半导体材料层的材料为多晶硅、硅锗或碳化硅。
13.如权利要求1所述的埋藏沟道晶体管的形成方法，其特征在于，所述栅电极的杂质离子的浓度与反型掺杂区杂质离子的浓度正相关。
14.一种埋藏沟道晶体管，其特征在于，包括：
半导体衬底，所述半导体衬底内形成有阱区；
位于所述阱区内的反型掺杂区，所述反型掺杂区中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相反，且反型掺杂区的深度小于阱区的深度；
位于所述阱区内的防穿通区，所述防穿通区中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相同，且所述防穿通区中掺杂的杂质离子的类型与反型掺杂区中掺杂的杂质离子的类型相反；所述防穿通区深度大于后续步骤中形成的源区和漏区的深度，且与源区和漏区不接触；
位于所述反型掺杂区的上方的半导体衬底表面的形成栅极结构，所述栅极结构包括栅介质层、位于栅介质层上的栅电极以及位于栅介质层和栅电极的两侧侧壁的侧墙，所述栅电极的中掺杂有杂质离子，所述栅电极中掺杂的杂质离子的类型与阱区中掺杂的杂质离子的类型相同；
位于所述栅极结构两侧的半导体衬底内的源区和漏区，所述源区和漏区中掺杂的杂质离子的类型与阱区中的杂质离子类型相反，源区和漏区的深度小于阱区的深度且大于反型掺杂区的深度；
所述源区和漏区包括位于侧墙的表面以及侧墙两侧的半导体衬底表面掺杂有杂质离子的源漏区材料层和位于侧墙两侧的半导体衬底内的与源漏区材料层接触的掺杂区，所述源漏区材料层为后续形成与源漏区电连接的金属插塞提供接触空间，并且为晶体管的导通提供载流子，因而减小源区和漏区在半导体衬底上占据的横向尺寸。
15.如权利要求14所述的埋藏沟道晶体管，其特征在于，所述晶体管为N型的晶体管，所述阱区中掺杂的杂质离子中的杂质离子类型为P型，反型掺杂区中掺杂的杂质离子的类型为N型，栅电极中掺杂的杂质离子的类型为P型，源区和漏区中掺杂的杂质离子的类型为N型。
16.如权利要求14所述的埋藏沟道晶体管，其特征在于，所述晶体管为P型的晶体管，所述阱区中掺杂的杂质离子中的杂质离子类型为N型，反型掺杂区中掺杂的杂质离子的类型为P型，栅电极中掺杂的杂质离子的类型为N型，源区和漏区中掺杂的杂质离子的类型为P型。
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