CN106911329A - A kind of single-phase phase-locked loop based on FPGA - Google Patents

Abstract

A kind of single-phase phase-locked loop based on FPGA, the phase voltage of net side one in collection transmission system, it is v to make_i(t), by v_i(t) and control system inner synchronousing signal v_oT () is multiplied and is compared, and this signal is filtered, and filters the second harmonic component and noise of the output of multiplication phase discriminator, tries to achieve error voltage signal v_do(t)；Then by error voltage signal v_doT () obtains v by PI regulations_e(t), by v_eT () obtains Δ after a recursion is averaging filtering_e(t), then use this Δ_eT () calculates real-time frequency f, the frequency conversion for obtaining into the cycle, this periodic quantity is to be considered control system inner synchronousing signal periodic quantity, then this periodic quantity is carried out decile, moment per decile is all once exported to control system synchronizing signal, as real-time phase information sin θ.The present invention utilizes analog hardware principle of phase lock loop, realizes that program is simple, and stability is high, can also stablize under the operating mode for having harmonic wave to disturb and effectively run.

Description

A kind of single-phase phase-locked loop based on FPGA

Technical field

The present invention relates to a kind of single-phase phase-locked loop based on FPGA, belong to electric and electronic technical field.

Background technology

With the deep development of Power Electronic Technique, various power electronic equipments such as PWM rectifier, static reacance occur Device, uninterrupted power source, new energy power generation grid-connection device etc. are more widely applied.The performance of these devices is relied heavily on In the service behaviour of phaselocked loop.

The implementation of single-phase phase-locked loop is numerous, and regulation lock is equal to have zero passage to lock mutually and instantaneously.Zero passage phase-lock technique is simple, Detect input signal phase by capturing the zero crossing of input signal, because its governing speed is slower, when input signal interference compared with Greatly, lock is may result in when there is multiple zero crossings mutually to fail.The scheme that instantaneous regulation lock is mutually implemented is complicated, consumes multiprocessing Device resource.

The content of the invention

The purpose of the present invention is, in order to solve the problems, such as existing single-phase phase-locked loop, while considering harmonic wave in power network Problem, the present invention proposes a kind of single-phase phase-locked loop based on FPGA.

Realize the technical scheme is that, a kind of single-phase phase-locked loop based on FPGA, lock phase step it is as follows：

(1) the single-phase voltage signal v that will be collected_i(t) and control system inner synchronousing signal v_oT () is multiplied and is compared, And export an error voltage signal v for corresponding to two signal phase differences_d(t)；

(2) according to the error voltage signal asked, error voltage signal is filtered, filters two in multiplication phase discriminator Order harmonic components and noise；

(3) the treated error voltage signal for obtaining is obtained into v by PI regulations_e(t),

By v_eT () obtains Δ after a recursion is averaging filtering_e(t), then use this Δ_eT () calculates real-time frequency f, from And realize the locking at phase angle and draw real-time phase signal sin θ；

(4) Δ is used_eT () calculates real-time frequency f, so as to realize the locking at phase angle and draw real-time phase signal sin θ.

Collection voltages in the step (1) are as follows with the expression formula that control system inner synchronousing signal is multiplied：

Wherein：V_iIt is the amplitude of input signal；ω_iIt is input signal angular frequency；θ_iT () is input signal with its ω_iIt is ginseng The instantaneous phase angle examined；V_oIt is the amplitude of control system inner synchronousing signal；ω_oIt is control system inner synchronousing signal angular frequency；It is the inherent frequency error of voltage controlled oscillator；K is the proportionality coefficient of multiplier.

It is described that error voltage signal is filtered, using recursion method is averaging to filter second harmonic, obtain v_do(t) =V_dsin[θ₁(t)]；Wherein,

The locking for realizing phase angle and the step of draw real-time phase signal sin θ it is as follows：

According to the Δ tried to achieve_eT (), obtains real-time system electric voltage frequency；The frequency conversion that will be tried to achieve into the cycle, this periodic quantity It is considered control system inner synchronousing signal periodic quantity, then this periodic quantity is carried out 2ⁿDecile, the moment per decile is all to control System synchronization signal processed is once exported, as real-time phase information sin θ；

F=F_clk/{2ⁿ*[Dpd+Δ_e(t)]}；

F in formula_clkIt is the input clock frequency of FPGA system, Dpd is system constant.

The single-phase phase-locked loop includes sampling module, multiplication phase discriminator module, voltage differential signal filtration module, PI regulation moulds Block, error signal filtration module and computing module；Sampling module collection single-phase voltage signal v_i(t), it is same with control system inside Step signal v_oT () is multiplied, after multiplication phase discriminator module is compared, output error voltage signal v_d(t)；Through voltage differential signal Filtration module is filtered to error voltage signal；Error voltage signal v after filtered treatment_doT () is by PI adjustment modules Obtain v_e(t)；By v_eT () after the filtering of error signal filtration module by obtaining Δ_e(t)；This Δ is used again_eT () passes through computing module Real-time frequency f is calculated, so as to realize the locking at phase angle and draw real-time phase signal sin θ.

The beneficial effects of the invention are as follows the present invention is using analog hardware principle of phase lock loop single-phase lock phase of the design based on FPGA Ring, realizes that program is simple, and stability is high, can also stablize under the operating mode for having harmonic wave to disturb and effectively run.

Brief description of the drawings

Fig. 1 is the module frame chart of embodiment of the present invention phaselocked loop；

Fig. 2 is the visual programming logic diagram of embodiment of the present invention filtering；

Fig. 3 is the visual programming logic diagram of embodiment of the present invention PI regulations；

Fig. 4 is the visual logic block diagram that the embodiment of the present invention obtains real-time phase information.

Specific embodiment

The present invention is described in further detail with reference to the accompanying drawings and examples.

As shown in figure 1, being a kind of single-phase phase-locked loop module frame chart based on FPGA of the present embodiment.This is realized in the present embodiment The main flow of inventive method is followed successively by：Acquisition system net survey any phase voltage, carry out signal comparing, voltage differential signal filtering, PI regulations, error signal filter, calculate real-time frequency and try to achieve real-time phase information；Comprise the following steps that：

Step 1, acquisition system net survey any phase voltage：

Setting program performs counter, often count down to Dpd+ Δs_eT (), is just once sampled.

Step 2, signal compare：

(t)=Kv_i(t)v_o(t)=KV_icos[ω_ot+θ₁(t)]V_osin(ω_ot)

=KV_iV_osin[2ω_ot+θ₁(t)]+KV_iV_osin[θ₁(t)]

Step 3, voltage differential signal filtering：

As shown in Fig. 2 by v_dT () is averaging method and is filtered treatment by recursion, filter second harmonic, obtains signal v_do(t)。

Step 4, PI regulations：

As shown in figure 3, proportion of utilization amplifier and integral element are to v_doT () signal carries out proportional integral regulation, missed Difference signal v_e(t)。

Step 5, error signal filtering

Logical AND Fig. 2 block diagrams are the same, by signal v_eT () is filtered treatment, obtain Δ_e(t)。

Step 6, seek real-time frequency：

According to the Δ obtained after filtering_eT (), calculates real-time frequency value f.

Step 7, try to achieve real-time phase information

As shown in figure 4, the frequency signal tried to achieve using step 6, the frequency conversion tried to achieve into the cycle, this periodic quantity is to recognize To be control system inner synchronousing signal periodic quantity, then this periodic quantity is carried out decile, the moment per decile is all to control system Synchronizing signal is once exported, as real-time phase information sin θ.

Claims (5)

1. a kind of single-phase phase-locked loop based on FPGA, it is characterised in that the lock phase step of the single-phase phase-locked loop is as follows：

(1) the single-phase voltage signal v that will be collected_i(t) and control system inner synchronousing signal v_oT () is multiplied and is compared, and defeated Go out an error voltage signal v for corresponding to two signal phase differences_d(t)；

(2) according to the error voltage signal asked, error voltage signal is filtered, is filtered secondary humorous in multiplication phase discriminator Wave component and noise；

(3) the treated error voltage signal for obtaining is obtained into v by PI regulations_e(t),

$v_e\left(t\right)=K_p{v}_{do}\left(t\right)+K_i{\∫}_0^t{v}_{do}\left(t\right)dt;$

By v_eT () obtains Δ after a recursion is averaging filtering_e(t), then use this Δ_eT () calculates real-time frequency f, so that real Show the locking at phase angle and draw real-time phase signal sin θ；

(4) Δ is used_eT () calculates real-time frequency f, so as to realize the locking at phase angle and draw real-time phase signal sin θ.

2. a kind of single-phase phase-locked loop based on FPGA according to claim 1, it is characterised in that in the step (1) Collection voltages are as follows with the expression formula that control system inner synchronousing signal is multiplied：

$\begin{array}{c}{v}_d\left(t\right)={\mathrm{Kv}}_i\left(t\right)v_o\left(t\right)={\mathrm{KV}}_i\cos \[{\mathrm{\ω}}_{o}t+{\mathrm{\θ}}_1\left(t\right)\]V_o\sin \left({\mathrm{\ω}}_{o}t\right)\\ =\frac{1}{2}{\mathrm{KV}}_i{V}_o\sin \[2{\mathrm{\ω}}_{o}t+{\mathrm{\θ}}_1\left(t\right)\]+\frac{1}{2}{\mathrm{KV}}_i{V}_o\sin \[{\mathrm{\θ}}_1\left(t\right)\]\end{array}$

${\mathrm{\θ}}_1\left(t\right)=({\mathrm{\ω}}_i-{\mathrm{\ω}}_o)t+{\mathrm{\θ}}_1\left(t\right)={\mathrm{\Δ}}_{{\mathrm{\ω}}_{o}t}+{\mathrm{\θ}}_1\left(t\right)$

Wherein：V_iIt is the amplitude of input signal；ω_iIt is input signal angular frequency；θ_iT () is input signal with its ω_iIt is reference Instantaneous phase angle；V_oIt is the amplitude of control system inner synchronousing signal；ω_oIt is control system inner synchronousing signal angular frequency； It is the inherent frequency error of voltage controlled oscillator；K is the proportionality coefficient of multiplier.

3. a kind of single-phase phase-locked loop based on FPGA according to claim 1, it is characterised in that described to believe error voltage Number it is filtered, is averaging method using recursion to filter second harmonic, obtains v_do(t)=V_dsin[θ₁(t)]；Wherein,

4. a kind of single-phase phase-locked loop based on FPGA according to claim 1, it is characterised in that the phase angle of realizing The step of locking and draw real-time phase signal sin θ is as follows：

According to the Δ tried to achieve_eT (), obtains real-time system electric voltage frequency；Into the cycle, this periodic quantity is to recognize to the frequency conversion that will be tried to achieve To be control system inner synchronousing signal periodic quantity, then this periodic quantity is carried out 2ⁿDecile, the moment per decile is all to control system System synchronizing signal is once exported, as real-time phase information sin θ；

F=F_clk/{2ⁿ*[Dpd+Δ_e(t)]}；

F in formula_clkIt is the input clock frequency of FPGA system, Dpd is system constant.

5. a kind of single-phase phase-locked loop based on FPGA according to claim 1, it is characterised in that the single-phase phase-locked loop bag Include sampling module, multiplication phase discriminator module, voltage differential signal filtration module, PI adjustment modules, error signal filtration module and meter Calculate module；Sampling module collection single-phase voltage signal v_i(t), with control system inner synchronousing signal v_oT () is multiplied, in multiplication mirror After phase device module is compared, output error voltage signal v_d(t)；Error voltage signal is entered through voltage differential signal filtration module Row filtering；Error voltage signal after filtered treatment obtains v by PI adjustment modules_e(t)；By v_eT () filters by error signal Δ is obtained after ripple module filtered_e(t)；This Δ is used again_eT () calculates real-time frequency f by computing module, so as to realize phase angle Lock and draw real-time phase signal sin θ.