CN106897628A - A kind of secure processing device for preventing summand side channel information from revealing and method - Google Patents
A kind of secure processing device for preventing summand side channel information from revealing and method Download PDFInfo
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- CN106897628A CN106897628A CN201510949994.6A CN201510949994A CN106897628A CN 106897628 A CN106897628 A CN 106897628A CN 201510949994 A CN201510949994 A CN 201510949994A CN 106897628 A CN106897628 A CN 106897628A
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Abstract
The present invention relates to a kind of safety device or chip and security processing that prevent summand side channel information from revealing；The safety device includes register, modified adder, modified single-bit full adder, modified half adder and multiplier；Wherein, the modified adder is made up of 32 modified single-bit full adders；In one embodiment, the modified half adder realizes circuit, and the computing for calculating one's own department or unit result is decomposed into several xor operations, first mask and addend is carried out into XOR, and the result for obtaining carries out XOR with the summand by mask again；The present invention uses improved adder circuit and its security processing, realizes the migration from XOR to add operation with hardware circuit so that safe handling efficiency is greatly improved.
Description
Technical field
The invention belongs to field of information security technology, more particularly to a kind of safety for preventing summand side channel information from revealing
Circuit or chip and security processing.
Background technology
Current information security field, various cryptanalysis means are continued to bring out.With the ordinary cryptographic for security algorithm point
Analysis mode is different, and side Multiple Channel Analysis focus more on feature when security algorithm runs within hardware, by with power consumption, electromagnetism spoke
Penetrate, the information revealed of mode such as mistake induction, the confidential data relevant with security algorithm is obtained to the utmost.
Based on logic semiconductor, gate is made up of encryption hardware a large amount of transistors, when being discharged in gate
During phenomenon, electronics flows through from silicon substrate, consumed energy, while electromagnetic radiation is produced, and energy spectrometer is exactly the work(for monitoring hardware
The change of the energy information such as consumption or electromagnetic radiation, is divided the side information being collected into using statistical method and attack experience
Analysis；Energy spectrometer technology mainly has following four：Simple power consumption analysis（Simple Power Analysis), simple electromagnetism spoke
Penetrate analysis（Simple Electromagnetic Analysis) and corresponding differential power consumption analysis（Differential
Power Analysis) and difference electromagnetic radiation analysis (Differential Electromagnetic Analysis)；Mesh
Before, especially differential power analysis are widely used the data protected with the electronic device that snatches password to energy spectrometer technology.
Due to the side-channel attack for being related to energy spectrometer touched and just it is deeper and deeper have influence on bank, finance,
Industry and commerce and people's daily life；The research report in terms of Attacks defence also progressively occurs both at home and abroad, its main flow skill
Art includes：Mask technology, clock upset technology in algorithm and its hardware realization etc., wherein mask method can due to realizing cost
Control and the working characteristics of digital circuit is not influenceed, received significant attention.
For side-channel attack, conventional mask guard technology is：During each data transfer, made using a random number
It is data mask（MASK）；Data and mask are different or, the data for obtaining for transmitting or carry out other behaviour in the chips
Make；Because transmitting used mask each time to differ, the information of the waveform leakage that attacker's multi collect is obtained
Differ, such attacker will be unable to obtain the actual value of data.
If however, important information carries out add operation by being needed after transmission；It is typically only capable to by the data of mask first
It is different with mask or, obtain real data, then carry out add operation；So the information of this significant data will be revealed again；At present
Solve the problems, such as the common method of such addition, classical documents " On boolean and arithmetic masking
against differential power analysis”, Lecture Notes in Conputer Science
Volume 1965,2000, pp231-237., Coron, J.S. and L.Goubin, two authors have been described in detail；
The method carries out the computing of many sub-additions and XOR by software to data, and addition is obtained in the case of not leak data information
As a result, it is desirable to use 1 random number.
The deficiencies in the prior art part, in the chips generally by protected data and a random mask（MASK）XOR,
Mask protection is carried out to data, because the mask MASK for using every time is differed；Usual data a is obtained with mask m phase XORs（）.To realize add operation, because addition and XOR are different computings, it is typically only capable to elder generation
By mask data（）A is obtained with mask m phase XORs, then is added with data b, the work(of a will so occurs
Consumption information, can be found by attacker.
The content of the invention
For above-mentioned the deficiencies in the prior art, summand side channel is prevented it is an object of the present invention to provide one kind
The safety circuit or chip and security processing of information leakage, the safety circuit and security processing can be solved
Mask data protection problem in side-channel attack, realizes being shifted from XOR to add operation, and avoid power consumption using hardware
Information leakage.
The present invention is to solve the scheme that is used of its technical problem, a kind of peace for preventing summand side channel information from revealing
Full processing unit, the secure processing device includes：
Register, for inputoutput data, is write by CPU by bus, and output data is deposited in a register, is led to by CPU
Cross bus reading；
Modified adder, is made up of 32 modified single-bit full adders, and its input port is 32 and is added by mask
Number, 32 addends, 32 bitmasks, 1 CIB carry-into bit, its output：32 data, 1 carry-out
Position, for calculating, mask is obtained with by the summand phase XOR of mask value XOR
To summand, then by summand and addend carry out add operation to addition results；
Modified single-bit full adder, is made up of modified half adder, and its input port is：1 summand by mask, 1
Bitmask, 1 addend, 1 carry, its carry-out bit is：1 one's own department or unit result, 1 carry result；
Modified half adder, its input port is：1 summand by mask, 1 bitmask, 1 addend, its carry-out bit
For：1 half adder one's own department or unit result, 1 half adder carry result；
Multiplier, its input port is：32 multiplicands and 32 multipliers, its output port is：64 multiplication results.
Preferably, the modified half adder realizes circuit, the computing for calculating one's own department or unit result is decomposed into several different
Or operation, mask and addend are first carried out into XOR, the result for obtaining carries out XOR with the summand by mask again.
Preferably, the modified half adder realizes circuit, the computing for calculating one's own department or unit result is decomposed into several different
Or operation, first XOR being carried out by the summand of mask and addend, the result for obtaining carries out XOR with mask again.
Preferably, the modified half adder realizes circuit, and the computing for calculating carry end value is deformed, and decomposes
It is three operations of intermediate data logical AND, intermediate data 1 is by the summand of mask and the logic of mask or computing, centre
Data 2 are to carry out the result that logic or operation are obtained by the logic NOT of the summand of mask and the logic NOT of mask, are first carried out
Intermediate data 2 is operated with the logical AND of addend, and the result for obtaining carries out logical AND operation with intermediate data 1.
Preferably, the modified half adder realizes circuit, and the computing for calculating carry end value is deformed, and decomposes
It is three operations of intermediate data logical AND, intermediate data 1 is by the summand of mask and the logic of mask or computing, centre
Data 2 are to carry out the result that logic or operation are obtained by the logic NOT of the summand of mask and the logic NOT of mask, are first carried out
Intermediate data 1 is operated with the logical AND of addend, and the result for obtaining carries out logical AND operation with intermediate data 2.
Preferably, this prevents the secure processing device of summand side channel information leakage from using modified adder and multiplication
Device, realizes that multiplication is operated, and its input data is：By the multiplicand of mask, mask, multiplier, random number；Output data is：Multiplication result, implementation method is：Take random number, it is calculated using modified adder, then calculateThe result for obtaining。
A kind of Research on Integrated Circuit Security chip, including the safe handling for preventing the channel information leakage of summand side described above
Device.
A kind of security processing for preventing summand side channel information from revealing, comprises the following steps that：
1）By input data storage in a register, write by bus by CPU, output data is deposited in a register, there is CPU
Read by bus；
2）Modified adder is configured to, is made up of 32 modified single-bit full adders, the modified single-bit full adder
Input bit be：1 summand by mask, 1 bitmask, 1 addend, 1 carry, its carry-out bit is：1 one's own department or unit knot
Really, 1 carry result；
3）Modified half adder is configured to, the input of modified half adder is：1 summand by mask, 1 bitmask, 1
Position addend, its carry-out bit is：1 half adder one's own department or unit result, 1 half adder carry result；
4）Modified single-bit full adder is configured to, is made up of modified half adder, its input port is：1 by mask
Summand, 1 bitmask, 1 addend, 1 carry, its carry-out bit is：1 one's own department or unit result, 1 carry result；
5）It is that its input port is by multiplier arrangement：32 multiplicands and 32 multipliers, its output port is：64 multiplication
As a result.
Preferably, this prevents the security processing of summand side channel information leakage, in the reality of the modified half adder
In existing circuit, the computing for calculating one's own department or unit result is decomposed into several xor operations, mask and addend is first carried out into XOR,
The result for obtaining carries out XOR with the summand by mask again.
Preferably, this prevents the security processing of summand side channel information leakage, in the reality of the modified half adder
In existing circuit, the computing for calculating one's own department or unit result is decomposed into several xor operations, first by by the summand and addend of mask
XOR is carried out, the result for obtaining carries out XOR with mask again.
Preferably, this prevents the security processing of summand side channel information leakage, in the reality of the modified half adder
In existing circuit, the computing for calculating carry end value is deformed, be decomposed into three operations of intermediate data logical AND, mediant
According to 1 be by the summand of mask and the logic of mask or computing, intermediate data 2 be by the summand of mask logic NOT with
The logic NOT of mask carries out the result that logic or operation are obtained, and first carries out intermediate data 2 and is operated with the logical AND of addend, obtains
Result carries out logical AND operation with intermediate data 1.
Preferably, this prevents the security processing of summand side channel information leakage, in the reality of the modified half adder
In existing circuit, the computing for calculating carry end value is deformed, be decomposed into three operations of intermediate data logical AND, mediant
According to 1 be by the summand of mask and the logic of mask or computing, intermediate data 2 be by the summand of mask logic NOT with
The logic NOT of mask carries out the result that logic or operation are obtained, and first carries out intermediate data 1 and is operated with the logical AND of addend, obtains
Result carries out logical AND operation with intermediate data 2.
Preferably, this prevents the security processing of summand side channel information leakage, using modified adder and multiplies
Musical instruments used in a Buddhist or Taoist mass, realizes that multiplication is operated, and its input data is：By the multiplicand of mask, mask, multiplier, random number；Output data is：Multiplication result, implementation method is：Take random number, it is calculated using modified adder, then calculateThe result for obtaining。
The beneficial effects of the invention are as follows this circuit uses improved adder circuit and its security processing, uses hardware
Migration of the circuit realiration from XOR to add operation so that safe handling efficiency is greatly improved.
The present invention will be further described with reference to the accompanying drawings and detailed description.
Brief description of the drawings
Fig. 1 is modified adder structure schematic diagram of the invention.
Fig. 2 is modified adder logic computing schematic diagram of the invention.
Fig. 3 is modified adder of the invention and multiplier multiplying specific implementation illustration.
Fig. 4 is that the security processing for preventing the channel information leakage of summand side of the invention is embodied illustration.
Specific embodiment
Referring to shown in Fig. 1, modified adder structure schematic diagram；The input port of the modified adder is respectively：32
Position by mask summand data, 32 addend data, 32 bitmask data, and CIB carry-into bit, output
Port is：32 addition results Sum, and 1 carry-out position；32 modified single-bit full adders are included in circuit,
The input port of each modified single-bit full adder is：1 summand by mask, 1 addend, one is covered
Code, 1 carry, the output port of each single-bit full adder is：1 result, 1 carry。
Referring to shown in Fig. 1, the input data of modified adder32, respectively correspond to 32 modified single-bits
Full adderPort；The input data of modified adderIn 32, respectively correspond to 32 modified single-bits add entirely
DevicePort；32 of the input data m of modified adder, correspond to 32 modified single-bit full adders respectively
Port；The input data of modified adderWith the 1st input port of modified single-bit full adderIt is connected；Often
The output port of individual modified single-bit full adderWith the input port of next modified single-bit full adderIt is connected
Connect；32nd output port of modified single-bit full adderWith the output port of modified adderIt is connected.
Referring to shown in Fig. 2, being modified adder logic computing specific embodiment schematic diagram；AddendElder generation and mask dataLogic XOR is carried out, intermediate data d1 is obtained, by intermediate data d1 and summandLogic XOR is carried out,
Obtain intermediate data, willWith input carryCarry out logic XOR and obtain output result, willWith input carryCarry out logic and operation and obtain intermediate data, summandFirst negate and obtain, maskNegate and obtain,
Will be of the invertedWith it is of the invertedCarry out logic or computing obtains intermediate data d2, willWithCarry out logic
Or computing obtains intermediate data d3, by intermediate data d2 and addendCarry out logic and operation and obtain intermediate data d4, then by d4
Logic and operation is carried out with d3 obtain intermediate data, by intermediate dataWith intermediate dataCarry out logic or computing obtains defeated
Go out result。
Referring to the specific embodiment schematic diagram for shown in Fig. 3, being modified adder of the invention and multiplier realization；This changes
Enter type adder and multiplier, realize that multiplication is operated, its input data is：By the multiplicand of mask, mask, multiplier, random number；Output data is：Multiplication result, implementation method is：Take random number, using modified plus
Musical instruments used in a Buddhist or Taoist mass is calculated, then calculateThe result for obtaining。
Referring to shown in Fig. 4, being of the invention a kind of there is embodiment, the safety circuit processing method；
1）32 summands by mask, 32 addends, 32 bitmasks and 1 CIB carry-into bit are write into register by CPU
In；
2）32 summands by mask deposited in register, 32 addends, 32 bitmasks and 1 CIB carry-into bit are connected
Modified adder respective input mouthful is connected to as data input；
3）From 32 summands by mask of modified adder port input, 32 addends, 32 bitmasks are connected respectively
It is connected on 32 modified single-bit full adders, with 1 summand end by mask on each modified single-bit full adder
Mouthful, 1 bitmask port, 1 addend port is corresponding, and 1 CIB carry-into bit of modified adder is connected to the 1st modified
On 1 carry input mouthful of single-bit full adder；
4）1 summand port by mask in modified single-bit full adder, 1 bitmask port, 1 addend port leads to
The calculating of modified half adder is crossed, the operation result of the modified half adder, including 1 half adder one's own department or unit result and 1 is obtained
Half adder carry result；
5）Using the CIB carry-into bit of one's own department or unit output result of modified half adder and modified single-bit full adder it is different or, as
1 one's own department or unit output result of modified single-bit full adder, by one's own department or unit output result of modified half adder and modified digital ratio
The CIB carry-into bit of special full adder is carried out and computing, then is carried out or computing with the carry-out result of modified half adder, as
1 carry-out result of modified single-bit full adder；
6）By modified single-bit full-adder carry-out result, the carry input of next modified single-bit full adder is connected to
Mouthful；
7）One's own department or unit result of all 32 modifieds single-bit full adders is merged, as 32 addition knots of modified adder
Fruit export, using the 32nd carry result of modified single-bit full adder as modified adder carry-out；
8）32 addition results and 1 carry-out of modified adder are preserved in a register, by CPU from register
Middle reading.
Specific embodiment of the invention is above are only, those of ordinary skill in the art are not departing from the technology of the present invention thinking
On the basis of can have many deformations and change, these apparent technical schemes for being formed are also contained in the technology model of present invention protection
In enclosing, therefore all any modifications within the spirit and principles in the present invention, made, equal replacement, improvement etc., should be included in this
Within the rights protection scope of invention.
Claims (13)
1. a kind of secure processing device for preventing the leakage of summand side channel information, it is characterised in that the secure processing device bag
Include,
Register, for inputoutput data, is write by CPU by bus, and output data is deposited in a register, is led to by CPU
Cross bus reading；
Modified adder, is made up of 32 modified single-bit full adders, and its input port is 32 and is added by mask
Number, 32 addends, 32 bitmasks, 1 CIB carry-into bit, its output：32 data, 1 carry-out
Position, for calculating, mask is obtained with by the summand phase XOR of mask value XOR
To summand, then by summand and addend carry out add operation to addition results；
Modified single-bit full adder, is made up of modified half adder, and its input port is：1 summand by mask, 1
Bitmask, 1 addend, 1 carry, its carry-out bit is：1 one's own department or unit result, 1 carry result；
Modified half adder, its input port is：1 summand by mask, 1 bitmask, 1 addend, its carry-out bit
For：1 half adder one's own department or unit result, 1 half adder carry result；
Multiplier, its input port is：32 multiplicands and 32 multipliers, its output port is：64 multiplication results.
2. the secure processing device of summand side channel information leakage is prevented as claimed in claim 1, it is characterised in that this changes
That enters type half adder realizes circuit, and the computing for calculating one's own department or unit result is decomposed into several xor operations, first by mask with plus
Number carries out XOR, and the result for obtaining carries out XOR with the summand by mask again.
3. the secure processing device of summand side channel information leakage is prevented as claimed in claim 1, it is characterised in that this changes
That enters type half adder realizes circuit, and the computing for calculating one's own department or unit result is decomposed into several xor operations, first will be by mask
Summand and addend carry out XOR, the result for obtaining carries out XOR with mask again.
4. the secure processing device of summand side channel information leakage is prevented as claimed in claim 1, it is characterised in that this changes
That enters type half adder realizes circuit, and the computing for calculating carry end value deformed, and is decomposed into three intermediate data logics
With operation, intermediate data 1 is that intermediate data 2 is by mask by the summand of mask and the logic of mask or computing
The logic NOT of summand carries out the result that logic or operation are obtained with the logic NOT of mask, first carries out intermediate data 2 with addend
Logical AND is operated, and the result for obtaining carries out logical AND operation with intermediate data 1.
5. the secure processing device of summand side channel information leakage is prevented as claimed in claim 1, it is characterised in that this changes
That enters type half adder realizes circuit, and the computing for calculating carry end value deformed, and is decomposed into three intermediate data logics
With operation, intermediate data 1 is that intermediate data 2 is by mask by the summand of mask and the logic of mask or computing
The logic NOT of summand carries out the result that logic or operation are obtained with the logic NOT of mask, first carries out intermediate data 1 with addend
Logical AND is operated, and the result for obtaining carries out logical AND operation with intermediate data 2.
6. the secure processing device of multiplicand side channel information leakage is prevented as claimed in claim 1, it is characterised in that used
Modified adder and multiplier, realize that multiplication is operated, and its input data is：By the multiplicand of mask, cover
Code, multiplier, random number；Output data is：Multiplication result, implementation method is：Take random number, use modified
Adder is calculated, then calculateThe result for obtaining。
7. a kind of Research on Integrated Circuit Security chip, it is characterised in that including preventing summand as described in claim any one of 1-6
The secure processing device of side channel information leakage.
8. a kind of security processing for preventing the leakage of summand side channel information, it is characterised in that comprise the following steps that：
1）By input data storage in a register, write by bus by CPU, output data is deposited in a register, there is CPU
Read by bus；
2）Modified adder is configured to, is made up of 32 modified single-bit full adders, the modified single-bit full adder
Input bit be：1 summand by mask, 1 bitmask, 1 addend, 1 carry, its carry-out bit is：1 one's own department or unit knot
Really, 1 carry result；
3）Modified half adder is configured to, the input of modified half adder is：1 summand by mask, 1 bitmask, 1
Position addend, its carry-out bit is：1 half adder one's own department or unit result, 1 half adder carry result；
4）Modified single-bit full adder is configured to, is made up of modified half adder, its input port is：1 by mask
Summand, 1 bitmask, 1 addend, 1 carry, its carry-out bit is：1 one's own department or unit result, 1 carry result；
5）It is that its input port is by multiplier arrangement：32 multiplicands and 32 multipliers, its output port is：64 multiplication
As a result.
9. the security processing of summand side channel information leakage is prevented as claimed in claim 8, it is characterised in that this changes
That enters type half adder realizes circuit, and the computing for calculating one's own department or unit result is decomposed into several xor operations, first by mask with plus
Number carries out XOR, and the result for obtaining carries out XOR with the summand by mask again.
10. the security processing of summand side channel information leakage is prevented as claimed in claim 8, it is characterised in that should
Modified half adder realizes circuit, and the computing for calculating one's own department or unit result is decomposed into several xor operations, first will be by covering
The summand of code carries out XOR with addend, and the result for obtaining carries out XOR with mask again.
11. security processings for preventing summand side channel information from revealing as claimed in claim 8, it is characterised in that should
Modified half adder realizes circuit, and the computing for calculating carry end value deformed, and is decomposed into three intermediate data and patrols
Volume and operation, intermediate data 1 is that intermediate data 2 is by mask by the summand of mask and the logic of mask or computing
The logic NOT of summand and the logic NOT of mask carry out the result that logic or operation are obtained, first carry out intermediate data 2 and addend
Logical AND operation, the result that obtains carries out logical AND operation with intermediate data 1.
12. security processings for preventing summand side channel information from revealing as claimed in claim 8, it is characterised in that should
Modified half adder realizes circuit, and the computing for calculating carry end value deformed, and is decomposed into three intermediate data and patrols
Volume and operation, intermediate data 1 is that intermediate data 2 is by mask by the summand of mask and the logic of mask or computing
The logic NOT of summand and the logic NOT of mask carry out the result that logic or operation are obtained, first carry out intermediate data 1 and addend
Logical AND operation, the result that obtains carries out logical AND operation with intermediate data 2.
A kind of 13. security processings for preventing summand side channel information from revealing as claimed in claim 8, its feature exists
In, using modified adder and multiplier, realize that multiplication is operated, its input data is：By the multiplicand of mask, mask, multiplier, random number；Output data is：Multiplication result, implementation method is：Take random number, it is calculated using modified adder, then calculateThe result for obtaining。
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| CN107508663A (en) * | 2017-09-05 | 2017-12-22 | 成都三零嘉微电子有限公司 | A kind of Boolean XOR mask turns the protection circuit of arithmetic addition mask |
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