CN106886210A - Based on the priming system timing sequence testing device that sequence triggering is taken pictures - Google Patents
Based on the priming system timing sequence testing device that sequence triggering is taken pictures Download PDFInfo
- Publication number
- CN106886210A CN106886210A CN201710005475.3A CN201710005475A CN106886210A CN 106886210 A CN106886210 A CN 106886210A CN 201710005475 A CN201710005475 A CN 201710005475A CN 106886210 A CN106886210 A CN 106886210A
- Authority
- CN
- China
- Prior art keywords
- module
- port
- clk
- time
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
- G05B23/0221—Preprocessing measurements, e.g. data collection rate adjustment; Standardization of measurements; Time series or signal analysis, e.g. frequency analysis or wavelets; Trustworthiness of measurements; Indexes therefor; Measurements using easily measured parameters to estimate parameters difficult to measure; Virtual sensor creation; De-noising; Sensor fusion; Unconventional preprocessing inherently present in specific fault detection methods like PCA-based methods
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Disclose the priming system timing sequence testing device taken pictures based on sequence triggering.Taken pictures sampling module and the state change that compares control logic module parallel monitoring priming system time-ordered measurement port by port input filter module, port, if the current port state of time-ordered measurement port is different from last time port status, then latch the timers value of Timer module, by timers value and current port state write-in FIFO memory module, and the last time port status deposited in register module are updated with current port state；Compensation is filtered by the clock frequency of clock frequency division module adjustment time-ordered measurement port, by port input filter module, the certainty of measurement of priming system sequential time measurement device can be arbitrarily adjusted；By the timing bit wide for adjusting Timer module, it is possible to achieve timing length requirement expected from system.Priming system timing sequence testing device small volume of the invention, fast test, easily high precision, extension, can be directly integrated in airborne equipment.
Description
Technical field
Designed the present invention relates to guided missile and carrier space vehicle control system equipment, the fire more particularly to taken pictures based on sequence triggering
Work product timing sequence testing device.
Background technology
Background of related of the invention is illustrated below, but these explanation might not constitute it is of the invention existing
Technology.
Priming system is a kind of sensitive ignition energy of miniaturization, in conventional weapon ammunition, strategic missile, nuclear weapon and boat
Extensive use in the military engineerings such as empty aerospace system.Priming system guiding detonating controlling, typically by relay switch or other switch controls
Power on processed is simultaneously applied on priming system loop.Priming system sequential refers generally to missile armament, carrier rocket and is launching, flying
The control sequence of priming system ignited successively is needed in journey.
Priming system SECO possesses very important effect in guided missile and booster system, influences flight success or failure,
So, it is necessary to be carried out to priming system and its control circuit in testing and control before guided missile is penetrated with carrier rocket and flight course
Test,, fast and accurately to determine whether priming system path meets launch requirements, the latter is mainly used in flying quality point for the former
Analysis.
Priming system control sequential is typically special time order, pulsewidth (such as 100ms, 200ms) switching value, and its is main
Tested information be at the beginning of sequential between, end time and temporal width.General detection mode is by pre-processing circuit
Detect on-off model (generally square-wave signal), after temporal information detection is carried out to square-wave signal.Traditional detection mode is
First realize Signal Pretreatment on bullet (arrow), after send ground testing system equipment to be tested.The test mode on ground is：First pass through
Pre-processed results on ground number transmission control molding block scan (once gating sequential all the way) bullet, if signal, then select the signal
It is logical to deliver to frequency measurement module when ground is surveyed, so between completing at the beginning of sequential, the measurement of end time and width.
The main deficiency of conventional test methodologies is：(1) the realization of test function is depended on bullet (arrow), equipment is more and volume
Greatly, with the increase of priming system sequential way, system extension is complicated；(2) test degree of parallelism is not high, by scanning, chooses test,
Can only once survey all the way, testing efficiency is low, real-time is not high；Due to test system bullet (arrow), line long connection, constitute it is multiple
Miscellaneous, the frequency sampled by intermittent scanning is not high, and measuring accuracy is not high, about 50ms or so.
The content of the invention
It is an object of the invention to the priming system timing sequence testing device for proposing to be taken pictures based on sequence triggering, can be directly integrated
In airborne equipment, small volume, fast test, easily high precision, extension can effectively improve guided missile with carrier rocket priming system sequential
Test performance.
The priming system timing sequence testing device that the present invention is taken pictures based on sequence triggering, including：Port input filter module, port
Take pictures sampling module, compare control logic module, register module, Timer module, FIFO and write logic module, FIFO memory
Module, clock frequency division module and Read-write Catrol module；Wherein,
Read-write Catrol module receives the operational order of extraneous input；Clock frequency division module will be defeated according to outside operational order
Enter clock Clk_In and divide at least two clocks；At least two clock includes Scan_Clk and Sys_Clk, Scan_Clk
Output to port input filter module, Sys_Clk export to priming system timing sequence testing device except port input filter module it
Other outer modules；
Port input filter module will be exported to port after the temporal filtering of each time-ordered measurement port and taken pictures sampling module,
Port sampling module of taking pictures obtains the current port state of the time-ordered measurement port and sends to comparing control logic mould parallel
Block；
After comparing the current port state that control logic module receives the time-ordered measurement port, register module is inquired about
The last time port status of the time-ordered measurement port of middle deposit；If the current port state of the time-ordered measurement port and last time
Port status are different, generate latch signal, and the current port state of the latch signal and the time-ordered measurement port is sent out
Deliver to FIFO and write logic module；
FIFO is write after logic module receives the latch signal, latches the timers value of Timer module, will be described
Timers value and current port state write-in FIFO memory module, and working as with the priming system time-ordered measurement port
Front port state updates the last time port status deposited in register module.
Preferably, clock frequency division module is divided using counting；The clock phase phase of Clk_In, Scan_Clk and Sys_Clk
Together.
Preferably, port input filter module uses timing filter method；If the present port shape of the time-ordered measurement port
State is different from last time port status, and control module starts the filtering counter based on Scan_Clk：
The initial value for filtering counter is 0；When the count value for filtering counter is not up to filtering setting value, port input
Filtration module filters the port status change of the time-ordered measurement port；When the count value of filtering counter reaches filtering setting value
When, port input filter module exports the current port state of the time-ordered measurement port.
Preferably, Timer module with Sys_Clk be timer clock source；The timing bit wide M of Timer module meets such as
Lower relation：
In formula, L is timing length, and unit is h；TshortIt it is the time-count cycle of Sys_Clk, unit is μ s；Represent upward
Bracket function.
Preferably, at least two clock is further included：Syn_Clk_In, and the time-count cycle of Syn_Clk_In is big
The time-count cycle of Sys_Clk；
Timer module include two timers, one of them with Syn_Clk_In be timer clock source, for a high position
The thick timing of byte, another with Sys_Clk be timer clock source, for low byte essence timing；
The initial clocking value of Syn_Clk_In and Sys_Clk is 0；When the effective timing of Syn_Clk_In is along not timed out, by
Sys_Clk clocks carry out low level essence timing, and when the effective timing of Syn_Clk_In is along reaching, low byte essence clocking value clear 0 is high
The thick clocking value of bit byte adds 1.
Preferably, the timing bit wide M of Timer module meets following relation：
M=M1+M2
In formula, L is timing length, and unit is h；M1It is the timer bit wide of Syn_Clk_In, M2It is the timing of Sys_Clk
Device bit wide；TlongIt it is the cycle of Syn_Clk_In, unit is s；TshortIt it is the cycle of Sys_Clk, unit is μ s；Δ1It is Syn_
The timing margins of Clk_In, unit is s；Δ2It is the timing margins of Sys_Clk, unit is μ s；Expression rounds up function.
Preferably, FIFO writes logic module and includes：Bit wide converter unit and FIFO writing controllers；
After bit wide converter unit receives the latch signal, the timers value of Timer module is latched, according to FIFO
The storage bit wide of memory module is by the corresponding timers value in all time-ordered measurement ports and the current port state
Y byte is spliced into, and the y byte is sent to FIFO writing controllers；Wherein, y is positive integer, the bit wide of each byte
Storage bit wide with FIFO memory module is equal；The y byte that FIFO writing controllers will be received writes FIFO memory
Module, and the last time end deposited in register module is updated with the current port state of the priming system time-ordered measurement port
Mouth state.
Preferably, bit wide converter unit is further used for：When (N+M) is not the integral multiple of Q, a high position is carried out before a splice
0 is mended, makes the integral multiple that (N+M) is Q；Wherein, N is sequential way, and M is the timing bit wide of Timer module, and Q is FIFO memory
The storage bit wide of module.
Preferably, FIFO writing controllers include that a Moore types FIFO write states machine and (N+M) displacement bit buffering are posted
Storage.
According to the present invention based on the sequence priming system timing sequence testing device taken pictures of triggering, by port input filter module,
Port is taken pictures and sampling module and compares the state change of control logic module parallel monitoring priming system time-ordered measurement port, if sequential
The current port state of measurement port is identical with last time port status, then continue port monitoring；Otherwise, Timer module is latched
Timers value, by timers value and current port state write-in FIFO memory module, and with priming system time-ordered measurement end
The current port state of mouth updates the last time port status deposited in register module；Sequential is adjusted by clock frequency division module to survey
Measure the clock frequency of port, compensation is filtered by port input filter module, can arbitrarily adjust priming system sequential
The certainty of measurement of time measurement device；By the timing bit wide for adjusting Timer module, it is possible to achieve timing is long expected from system
Degree is required.Priming system timing sequence testing device small volume of the invention, fast test, easily high precision, extension, can be directly integrated in bullet
In upper equipment.
Brief description of the drawings
By the specific embodiment part of offer referring to the drawings, the features and advantages of the present invention will become more
It is readily appreciated that, in the accompanying drawings：
Fig. 1 is the structural representation of priming system timing sequence testing device in the preferred embodiment of the present invention；
Fig. 2 is the state transfer schematic diagram of FIFO writing controllers in the preferred embodiment of the present invention.
Specific embodiment
Illustrative embodiments of the invention are described in detail with reference to the accompanying drawings.Illustrative embodiments are retouched
State merely for the sake of demonstration purpose, and be definitely not to the present invention and its application or the limitation of usage.
As shown in figure 1, the priming system timing sequence testing device that the present invention is taken pictures based on sequence triggering, including：Port input filter
Ripple module, port take pictures sampling module, compare control logic module, register module, Timer module, FIFO and write logic mould
Block, FIFO memory module, clock frequency division module and Read-write Catrol module；Wherein,
Read-write Catrol module receives the operational order of extraneous input；Clock frequency division module will be defeated according to outside operational order
Enter clock Clk_In and divide at least two clocks；At least two clock includes that Scan_Clk and Sys_Clk, Scan_Clk are defeated
Go out to port input filter module, Sys_Clk is exported to other modules in addition to the input filter module of port；
Port input filter module will be exported to port after the temporal filtering of each time-ordered measurement port and taken pictures sampling module,
Port sampling module of taking pictures obtains the current port state of the time-ordered measurement port and sends to comparing control logic mould parallel
Block；
After comparing the current port state that control logic module receives the time-ordered measurement port, register module is inquired about
The last time port status of the time-ordered measurement port of middle deposit, the P_Data0 in such as Fig. 1；If the time-ordered measurement port
Current port state P_Data1 is different from last time port status, latch signal is generated, by the latch signal and the sequential
The current port state of measurement port is sent to FIFO writes logic module；
FIFO is write after logic module receives the latch signal, the timers value of Timer module is latched, in such as Fig. 1
T_Data, by the timers value and current port state write-in FIFO memory module, and use the priming system
The current port state of time-ordered measurement port updates the last time port status deposited in register module.
The present invention can be with the state change of parallel monitoring multiple priming system time-ordered measurement port, and sequential way can be according to institute
Register resources, clock sources and the combination logic resource aggregate demand that need to be consumed are selected.Surveyed to improve priming system sequential
Measurement stability and reliability that trial assembly is put, when sequential way is set, can be such that priming system timing sequence testing device leaves necessarily
Data surplus, for example leave at least 20% data surplus.
Clock frequency division module can be using counting frequency dividing mode.For example, using the counter that subtracts, by host computer by read-write
Control module rewrites the Counter Value, realizes the multi-channel frequency division to input clock Clk_In, is formed for priming system timing sequence test dress
Put same-phase, the clock of different frequency that internal each functional module is used.Time-ordered measurement port is adjusted by clock frequency division module
Clock frequency, can arbitrarily adjust the certainty of measurement of priming system timing sequence testing device.
Sys_Clk frequencies are higher, and certainty of measurement is higher, but excessive frequency can not only increase the resource consumption of device,
The stability of digital independent can also be influenceed.Therefore, in the case where the requirement of system testing precision and data reading speed is met, Ke Yijin
The low reliable crystal oscillator of amount selection frequency：1. in terms of measuring accuracy：If the Sys_Clk clock cycle is T1, timing sequence test is such as required
Precision is not less than 0.5ms, then (i.e. " Timer module " elapsed time clock cycle T 1, adds " timer mould the Test data generation time
In block " the time lock cycle (containing the multilevel iudge time before locking) (n × T1), add and write the FIFO times (m × T1)) should be less than
0.5ms, i.e. T1+n × T1+m × T1=(1+n+m) × T1 are less than 0.5ms, and n takes 2, m and takes 20 in this example, therefore T1 is less than 0.5/
23ms, i.e. frequency are higher than 46kHz；2. in terms of data access speed：Such as require fire-working article test Data writing time (this example
In, one byte of write-in enters FIFO needs 2 T1 cycles) system of being slightly above is when reading data (the reading data fifo)
Between, system take and deposit time of test data for 4us, then 2 × T1 is less than 4us, then T1 is less than 2us.1., 2. synthesis, and leaves one
Determine surplus, the active crystal oscillators of 1MHz can be selected, be i.e. T1 is 1us.
The cycle of Scan_Clk is smaller, and the test resolving power of priming system timing sequence testing device is higher, but the cycle is smaller, dress
The resource consumption put is higher, and the stability of digital independent can also be reduced.Scan_ should be determined according to timing sequence test resolving power requirement
The cycle of Clk.For example, if it is desired to timing sequence test resolving power be not less than 10us, then the Scan_Clk cycles should be less than 10us.
The Clk_In cycles should be not more than min { Sys_Clk cycles, Scan_Clk cycles, other clock cycle }, it is considered to reduce
The requirement such as type selecting and device maturity is unified in logical resource consumption, component, and the Clk_In cycles can set Clk_In, Scan_
Clk is identical with the clock cycle of Sys_Clk, for example, be both configured to 1us, i.e., from 1MHz active crystal oscillator as FPGA
The external clock input of device.
In certain embodiments, port input filter module uses timing filter method.If front end is worked as in time-ordered measurement port
Mouth state is different from last time port status, and control module starts the filtering counter based on Scan_Clk：Filter the first of counter
Initial value is 0；When the count value for filtering counter is not up to filtering setting value, port input filter module filters the sequential and surveys
Measure the port status change of port；When the count value for filtering counter reaches filtering setting value, port input filter module is defeated
Go out the current port state of time-ordered measurement port.
For example, the timing bit wide of filtering counter is 8, initial value is 0, and timer clock is that (cycle is Scan_Clk
T1), it is capable of achieving [0, (28- 1) × T1] in the range of duration filtering, the selected filtering time length of this example is that (correspondence is counted 127us
It is worth for 127)).Under each sampling period of Scan_Clk, using XOR criterion, when discovery port status are (with " last time
(initial) port status " compare, similarly hereinafter) change when, start filtering counter, when Counter Value reaches 127, confirm port status
Change, and export the port status；If Counter Value is not up to 127, port status change disappears, then filter the change,
And maintain former output state.
Timer module can be timer clock source only with Sys_Clk.By adjusting the time-count cycle of Sys_Clk, can
Arbitrarily to adjust the accuracy of timekeeping of Timer module；By the timing bit wide for adjusting Sys_Clk, it is possible to achieve the expected meter of system
When length requirement.The timing bit wide M of Timer module meets following relation：
In formula, L is timing length, and unit is h；TshortIt it is the time-count cycle of Sys_Clk, unit is μ s；Represent upward
Bracket function.
In the present invention, at least two clock that clock frequency division module is formed may further include：Syn_Clk_In,
And time-count cycle of the time-count cycle of Syn_Clk_In more than Sys_Clk.Timer module includes two timers, one of them
Be timer clock source with Syn_Clk_In, for the thick timing of upper byte, another with Sys_Clk be timer clock source,
For low byte essence timing.The initial clocking value of Syn_Clk_In and Sys_Clk is 0；When the effective timing edges of Syn_Clk_In
It is not timed out, low level essence timing is carried out by Sys_Clk clocks, when the effective timing of Syn_Clk_In is along reaching, low byte essence meter
Duration clear 0, the thick clocking value of upper byte adds 1.The thick timing of upper byte is carried out with Syn_Clk_In, low level is carried out with Sys_Clk
Byte essence timing, by adjusting the time-count cycle of Syn_Clk_In and Sys_Clk, can arbitrarily adjust the timing of Timer module
Precision；By the timing bit wide for adjusting Syn_Clk_In and Sys_Clk, it is possible to achieve timing length requirement expected from system.It is excellent
Selection of land, the timing bit wide M of Timer module meets following relation：
M=M1+M2
In formula, L is timing length, and unit is h；M1It is the timer bit wide of Syn_Clk_In, M2It is the timing of Sys_Clk
Device bit wide；TlongIt it is the cycle of Syn_Clk_In, unit is s；TshortIt it is the cycle of Sys_Clk, unit is μ s；Δ1It is Syn_
The timing margins of Clk_In, unit is s；Δ2It is the timing margins of Sys_Clk, unit is μ s；Expression rounds up function.
In the preferred embodiment shown in Fig. 1, FIFO writes logic module to be included：Bit wide converter unit and FIFO write control
Device；After bit wide converter unit receives latch signal, the timers value of Timer module is latched, according to FIFO memory module
Storage bit wide Q the corresponding timers value in all time-ordered measurement ports and current port state are spliced into y byte, and will
The y byte is sent to FIFO writing controllers；Wherein, y is positive integer, bit wide and the FIFO memory module of each byte
Q is equal for storage bit wide；The y byte that FIFO writing controllers will be received writes FIFO memory module, and when using priming system
The current port state of sequence measurement port updates the last time port status deposited in register module.
For example, when N+M=72, storage bit wide are 8, by the corresponding timers value in all time-ordered measurement ports and currently
Every 8 of port status are spliced into 9 bytes for one group as a byte, are designated as successively to high-order each byte from low level
Byte0, Byte1 ..., Byte8), sent after the completion of splicing to FIFO writing controllers.
When (N+M) is not the integral multiple of Q, it is impossible to carry out data splicing according to above-mentioned.Based on this, bit wide converter unit can
To be further used for：When (N+M) is not the integral multiple of Q, high-order benefit 0 is carried out before a splice, make the integral multiple that (N+M) is Q；Its
In, N is sequential way, and M is the timing bit wide of Timer module.For example, when N+M=70, storage bit wide are 8, being mended in a high position
2 " 0 " are filled, 72 are spliced into, every 8, for one group used as a byte, can form 9 bytes, from low level to high-order each word
Section be designated as successively Byte0, Byte1 ..., Byte8), sent after the completion of splicing to FIFO writing controllers.
FIFO writing controllers can include a Moore types FIFO write states machine and (N+M) bit shift buffer stock
Device.Fig. 2 shows the state transfer schematic diagram of FIFO writing controllers in the preferred embodiment of the present invention, wherein, FIFO writing controllers
Including a Moore types FIFO write states machine and a 72 bit shift buffer registers.Moore type FIFO write state machines, are divided into
19 states, are described as follows：
ST0-electrification reset (Rst_In) original states afterwards；
When ready invalidating signals, show data invalid, put (wherein Wr_En half clock cycle outputs more late than Lock,
Similarly hereinafter)：
When ready signals are effective, put：
ST1 --- put following state (unlisted signal keeps laststate, similarly hereinafter)：
ST2 --- put following state：
ST3 --- put following state：
ST4 --- put following state：
ST5 --- put following state：
ST6 --- put following state：
ST7 --- put following state：
ST8 --- put following state：
ST9 --- put following state：
ST10 --- put following state：
ST11 --- put following state：
ST12 --- put following state：
ST13 --- put following state：
ST14 --- put following state：
ST15 --- put following state：
ST16 --- put following state：
ST17 --- put following state：
| Sequence number | Signal name | Signal condition | Remarks |
| 1) | Wr_En | It is invalid | FIFO write control signals |
| 2) | Scan_En | Effectively | Take pictures to sample and enable signal in port |
| 3) | next_state | ST0 | NextState |
ST_Other --- put following state：
When Lock signals are effective, the data of 72 bit shift buffer registers locking bit wide converter unit output lock number
Current port state data " P_Data1 " part in is sent out as last time port status simultaneously, for comparing control logic mould
Block is inquired about.When Shift_En is effective, shifted：Byte0→Byte1→Byte2→Byte3→Byte4→Byte5→
Byte6→Byte7→Byte8→Byte0。
If programming device resource is fully, can in the IP of priming system reality timing sequence testing device intrinsic call Universal FIFO or
By FIFO operation principle designed, designed FIFO memories, this scheme can improve the integrated level of design, but programming device is provided
Source requirement is higher, and design complexities are also higher.It is of course also possible to use extend out FIFO memory chip, design is simple, pair can compile
The requirement of journey device resource is low.
In the technology of priming system timing sequence testing device of the present invention, those skilled in the art can extend according to the actual requirements
Other logics, as shown in figure 1, the present invention does not elaborate to this.
Although with reference to illustrative embodiments, invention has been described, but it is to be understood that the present invention does not limit to
The specific embodiment that Yu Wenzhong is described in detail and shown, in the case of without departing from claims limited range, this
Art personnel can make various changes to the illustrative embodiments.
Claims (9)
1. the priming system timing sequence testing device taken pictures based on sequence triggering, it is characterised in that including：Port input filter module, end
Mouth take pictures sampling module, compare control logic module, register module, Timer module, FIFO write logic module, FIFO storage
Device module, clock frequency division module and Read-write Catrol module；Wherein,
Read-write Catrol module receives the operational order of extraneous input；When clock frequency division module will be input into according to outside operational order
Clock Clk_In divides at least two clocks；At least two clock includes that Scan_Clk and Sys_Clk, Scan_Clk are exported
To port input filter module, Sys_Clk is exported to priming system timing sequence testing device in addition to the input filter module of port
Other modules；
Port input filter module will be exported to port after the temporal filtering of each time-ordered measurement port and taken pictures sampling module, port
Sampling module of taking pictures obtains the current port state of the time-ordered measurement port and sends to comparing control logic module parallel；
After comparing the current port state that control logic module receives the time-ordered measurement port, posted in inquiry register module
The last time port status of the time-ordered measurement port deposited；If the current port state of the time-ordered measurement port and last time port
State is different, generates latch signal, by the current port state of the latch signal and the time-ordered measurement port send to
FIFO writes logic module；
FIFO is write after logic module receives the latch signal, the timers value of Timer module is latched, by the timing
Device numerical value and current port state write-in FIFO memory module, and work as front end with the priming system time-ordered measurement port
Mouth state updates the last time port status deposited in register module.
2. priming system timing sequence testing device as claimed in claim 1, it is characterised in that clock frequency division module is using counting point
Frequently；Clk_In, Scan_Clk are identical with the clock phase of Sys_Clk.
3. priming system timing sequence testing device as claimed in claim 1, it is characterised in that port input filter module uses timing
Filter method；If the current port state of the time-ordered measurement port is different from last time port status, control module startup is based on
The filtering counter of Scan_Clk：
The initial value for filtering counter is 0；When the count value for filtering counter is not up to filtering setting value, port input filter
Module filters the port status change of the time-ordered measurement port；When the count value for filtering counter reaches filtering setting value,
Port input filter module exports the current port state of the time-ordered measurement port.
4. priming system timing sequence testing device as claimed in claim 1, it is characterised in that Timer module is with Sys_Clk to count
When device clock source；The timing bit wide M of Timer module meets following relation：
In formula, L is timing length, and unit is h；TshortIt it is the time-count cycle of Sys_Clk, unit is μ s；Expression rounds up
Function.
5. priming system timing sequence testing device as claimed in claim 1, it is characterised in that at least two clock is further wrapped
Include：Syn_Clk_In, and Syn_Clk_In time-count cycle more than Sys_Clk time-count cycle；Timer module includes two
Timer, one of them is timer clock source with Syn_Clk_In, and for the thick timing of upper byte, another is with Sys_Clk
It is timer clock source, for low byte essence timing；
The initial clocking value of Syn_Clk_In and Sys_Clk is 0；When the effective timing of Syn_Clk_In is along not timed out, by Sys_Clk
Clock carries out low level essence timing, when the effective timing of Syn_Clk_In is along reaching, low byte essence clocking value clear 0, upper byte
Thick clocking value adds 1.
6. priming system timing sequence testing device as claimed in claim 5, it is characterised in that the timing bit wide M of Timer module expires
The following relation of foot：
M=M1+M2
In formula, L is timing length, and unit is h；M1It is the timer bit wide of Syn_Clk_In, M2It is the timer position of Sys_Clk
It is wide；TlongIt it is the cycle of Syn_Clk_In, unit is s；TshortIt it is the cycle of Sys_Clk, unit is μ s；Δ1It is Syn_Clk_
The timing margins of In, unit is s；Δ2It is the timing margins of Sys_Clk, unit is μ s；Expression rounds up function.
7. priming system timing sequence testing device as claimed in claim 1, it is characterised in that FIFO writes logic module to be included：Bit wide
Converter unit and FIFO writing controllers；
After bit wide converter unit receives the latch signal, the timers value of Timer module is latched, stored according to FIFO
The storage bit wide of device module splices the corresponding timers value in all time-ordered measurement ports and the current port state
Into y byte, and the y byte is sent to FIFO writing controllers；Wherein, y is positive integer, the bit wide of each byte with
The storage bit wide of FIFO memory module is equal；
The y byte write-in FIFO memory module that FIFO writing controllers will be received, and with the priming system time-ordered measurement
The current port state of port updates the last time port status deposited in register module.
8. priming system timing sequence testing device as claimed in claim 7, it is characterised in that bit wide converter unit is further used for：
When (N+M) is not the integral multiple of Q, high-order benefit 0 is carried out before a splice, make the integral multiple that (N+M) is Q；Wherein, when N is
Sequence way, M is the timing bit wide of Timer module, and Q is the storage bit wide of FIFO memory module.
9. priming system timing sequence testing device as claimed in claim 7, it is characterised in that FIFO writing controllers include
Moore types FIFO write states machine and (N+M) bit shift buffer register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710005475.3A CN106886210B (en) | 2017-01-04 | 2017-01-04 | The priming system timing sequence testing device taken pictures is triggered based on sequence |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710005475.3A CN106886210B (en) | 2017-01-04 | 2017-01-04 | The priming system timing sequence testing device taken pictures is triggered based on sequence |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106886210A true CN106886210A (en) | 2017-06-23 |
| CN106886210B CN106886210B (en) | 2019-03-08 |
Family
ID=59176327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710005475.3A Expired - Fee Related CN106886210B (en) | 2017-01-04 | 2017-01-04 | The priming system timing sequence testing device taken pictures is triggered based on sequence |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106886210B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109377588A (en) * | 2018-10-29 | 2019-02-22 | 百度在线网络技术（北京）有限公司 | Test macro, method and the vehicle of Vehicular system timing |
| CN112444168A (en) * | 2019-09-05 | 2021-03-05 | 南京理工大学 | Accurate timer for preventing electric tube explosion caused by wiring error |
| CN114546030A (en) * | 2022-02-15 | 2022-05-27 | 海光信息技术股份有限公司 | Chip clock design method, chip, device and related equipment |
| CN116112627A (en) * | 2023-04-07 | 2023-05-12 | 合肥六角形半导体有限公司 | Method and circuit for video frame rate self-adaptive transformation |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656056A (en) * | 2008-08-20 | 2010-02-24 | 三星电子株式会社 | Timing controller and display apparatus having the same |
| CN101666597A (en) * | 2009-09-18 | 2010-03-10 | 重庆大学 | Detecting device of control time sequence of non-contact initiating explosive device and method thereof |
| US7962869B2 (en) * | 2002-08-09 | 2011-06-14 | Synopsys, Inc. | Method and system for debug and test using replicated logic |
| CN102854411A (en) * | 2011-06-27 | 2013-01-02 | 爱德万测试株式会社 | Test apparatus and test method |
| CN103051323A (en) * | 2012-09-14 | 2013-04-17 | 中国航天科技集团公司第四研究院第四十一研究所 | Conditioning conversion circuit for airborne time sequence and initiating explosive device test |
| CN203587694U (en) * | 2013-11-15 | 2014-05-07 | 湖北三江航天红峰控制有限公司 | Test circuit for resistance and time sequence of initiating explosive device |
-
2017
- 2017-01-04 CN CN201710005475.3A patent/CN106886210B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7962869B2 (en) * | 2002-08-09 | 2011-06-14 | Synopsys, Inc. | Method and system for debug and test using replicated logic |
| CN101656056A (en) * | 2008-08-20 | 2010-02-24 | 三星电子株式会社 | Timing controller and display apparatus having the same |
| CN101666597A (en) * | 2009-09-18 | 2010-03-10 | 重庆大学 | Detecting device of control time sequence of non-contact initiating explosive device and method thereof |
| CN102854411A (en) * | 2011-06-27 | 2013-01-02 | 爱德万测试株式会社 | Test apparatus and test method |
| CN103051323A (en) * | 2012-09-14 | 2013-04-17 | 中国航天科技集团公司第四研究院第四十一研究所 | Conditioning conversion circuit for airborne time sequence and initiating explosive device test |
| CN203587694U (en) * | 2013-11-15 | 2014-05-07 | 湖北三江航天红峰控制有限公司 | Test circuit for resistance and time sequence of initiating explosive device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109377588A (en) * | 2018-10-29 | 2019-02-22 | 百度在线网络技术（北京）有限公司 | Test macro, method and the vehicle of Vehicular system timing |
| CN112444168A (en) * | 2019-09-05 | 2021-03-05 | 南京理工大学 | Accurate timer for preventing electric tube explosion caused by wiring error |
| CN112444168B (en) * | 2019-09-05 | 2024-02-13 | 南京理工大学 | Accurate timer for preventing wiring error electric shock and tube explosion |
| CN114546030A (en) * | 2022-02-15 | 2022-05-27 | 海光信息技术股份有限公司 | Chip clock design method, chip, device and related equipment |
| CN116112627A (en) * | 2023-04-07 | 2023-05-12 | 合肥六角形半导体有限公司 | Method and circuit for video frame rate self-adaptive transformation |
| CN116112627B (en) * | 2023-04-07 | 2023-06-20 | 合肥六角形半导体有限公司 | Method and circuit for video frame rate self-adaptive transformation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106886210B (en) | 2019-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106886210A (en) | Based on the priming system timing sequence testing device that sequence triggering is taken pictures | |
| CN102254062A (en) | Method for testing time series data of standard unit | |
| Basile et al. | Identification of timed input/output relationships for industrial automation systems using timed interpreted petri nets | |
| CN108279591B (en) | Simulation platform digital quantity universal output method | |
| SU1429121A1 (en) | Device for generating tests | |
| CN203192417U (en) | Reading-speed measuring circuit based on automatic and periodic reading operation | |
| SU1513450A1 (en) | Signature analyzer | |
| SU748882A2 (en) | Frequency multiplier | |
| SU620983A1 (en) | Article dimension checking arrangement | |
| SU530462A1 (en) | Frequency multiplier | |
| SU1403012A1 (en) | Time signal-correcting master quartz clock | |
| RU1837294C (en) | Device for testing shift register | |
| SU1591014A1 (en) | Microprogram control device | |
| CN116991055A (en) | High-precision GPS synchronous holding module | |
| SU1485250A1 (en) | Program check unit | |
| SU822141A1 (en) | Self-checking electronic time-piece | |
| Juhás et al. | Modelling Time in Signal Nets | |
| SU750711A2 (en) | Frequency multiplier | |
| SU496557A1 (en) | Control device | |
| SU826289A1 (en) | Device for determining parameters of transient process | |
| SU1315935A1 (en) | Automatic control system | |
| SU1037251A1 (en) | Operation sequence control device | |
| SU1354162A1 (en) | Device for checking frequency-time parameters | |
| SU610122A1 (en) | Apparatus for determining electronic circuitry reliability | |
| SU838603A1 (en) | Device for measuring frequency ratio |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190308 Termination date: 20210104 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |