CN106876482A - MESFET devices based on vertical-channel and preparation method thereof - Google Patents
MESFET devices based on vertical-channel and preparation method thereof Download PDFInfo
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- CN106876482A CN106876482A CN201710086828.7A CN201710086828A CN106876482A CN 106876482 A CN106876482 A CN 106876482A CN 201710086828 A CN201710086828 A CN 201710086828A CN 106876482 A CN106876482 A CN 106876482A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 130
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- 238000009413 insulation Methods 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 5
- 239000002061 nanopillar Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 239000010953 base metal Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002070 nanowire Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 235000007164 Oryza sativa Nutrition 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
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- 230000015556 catabolic process Effects 0.000 description 1
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- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
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- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8122—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
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Abstract
The invention discloses a kind of MESFET (metal-semiconductor field effect transistor) device based on vertical-channel, it includes MES structures, source electrode and drain electrode, the MES structures include grid and at least semiconductor raceway groove, the axis of the semiconductor channel is basically perpendicular to a selected plane, the grid is set around semiconductor channel, the source electrode is electrically connected through semiconductor channel with drain electrode, the source electrode and drain electrode are set along semiconductor channel axially spaced-apart, and the grid is distributed between source, drain electrode.The invention also discloses the preparation method of the MESFET devices.MESFET devices of the invention have that grid-control ability is good, working frequency is high, and manufacture craft difficulty is low, the advantages of high yield rate.
Description
Technical field
The present invention relates to a kind of semiconductor devices, more particularly to a kind of MESFET devices based on vertical-channel
(Vertical Channel Heterostructure Metal-Insulator-Semiconductor Field-effect
Transistor, VC-MESFET) and preparation method thereof.
Background technology
With the development of microelectric technique, cmos device and integrated circuit have stepped into the so-called rear mole epoch, that is,
The development of integrated circuit has progressively deviateed the curve of " Moore's Law ".Particularly when the grid of device are long and channel length increasingly
" short-channel effect ", " DIBL effects " (the Drain Induced Barrier brought during short, gate dielectric layer more and more thinner
Lowering, the potential barrier reduction that drain terminal is introduced) and the direct tunnelling of source and drain etc. so that device dimensions shrink is more and more difficult.And
And shortened because grid are long, grid-control ability declines, and makes the subthreshold amplitude of oscillation of device and switching current than declining, and brings power consumption increase etc.
A series of problems.In order to solve problem above, researcher proposes Si base Fin-FET, Si bases vertical channel device, based on receiving
The solutions such as the vertical devices of rice noodles.But these solutions still suffer from some defects.For example, Fin-FET still will be by
Photoetching technique is long to obtain smaller grid.And for example, device based on Si nano wires etc. must carry out local doping, which increase work
Skill difficulty.For another example, the vertical channel device of Si can in advance form the structure of multilayer difference doping type and etch to form vertical again
Channel structure, but, this undoubtedly more increases the complexity of technique, and Si material systems by its material character institute
Limit, it is also not satisfactory in the performance of the aspects such as high pressure resistant and high temperature resistant, radioresistance.
The content of the invention
It is a primary object of the present invention to provide a kind of MESFET (Metal-Insulator- with vertical-channel array
Semiconductor Field-effect Transistor, metal-semiconductor field effect transistor) device and its preparation side
Method, to overcome the deficiencies in the prior art.
For achieving the above object, present invention employs following technical scheme：
The embodiment of the invention provides a kind of MESFET devices based on vertical-channel, including MES structures, source electrode and leakage
Pole, the MES structures include grid and at least semiconductor raceway groove, and the axis of the semiconductor channel is basically perpendicular to a choosing
Face is allocated, the grid is set around the semiconductor channel, the source electrode is electrically connected through the semiconductor channel with the drain electrode
Connect, the source electrode and drain electrode are set along the semiconductor channel axially spaced-apart, and the grid is distributed between source electrode and drain electrode.
In some preferred embodiments, the MESFET devices include what is formed by a plurality of described semiconductor channels
Channel array.
Further, the grid forms Schottky contacts with the semiconductor channel.
Further, the source electrode and drain electrode forms Ohmic contact with the semiconductor channel.
In some preferred embodiments, at least one of the source electrode, drain electrode and grid are parallel to described selected flat
Face.
The embodiment of the present invention additionally provides a kind of preparation method of the MESFET devices based on vertical-channel, and it includes：
In forming at least semiconductor raceway groove on substrate principal plane, the axis of the semiconductor channel is basically perpendicular to described
Substrate principal plane；
Source electrode, grid and drain electrode are made, and the source electrode is electrically connected through the semiconductor channel with drain electrode, wherein described
Source electrode and drain electrode are set along the semiconductor channel axially spaced-apart, and the grid is distributed between source electrode and drain electrode.
In some preferred embodiments, described preparation method may also include：Formed by plural number on substrate principal plane
The channel array that individual described semiconductor channel is formed, makes the source electrode, grid and drain electrode afterwards.
Further, described preparation method also includes：Make to form Xiao Te between the grid and the semiconductor channel
Base is contacted.
Further, described preparation method also includes：The source electrode and drain electrode is set to form Europe with the semiconductor channel
Nurse is contacted.
Than prior art, the present invention at least has the following advantages that：
(1) grid of MESFET devices of the invention can realize that full angle is surrounded to raceway groove, therefore can carry to greatest extent
Grid-control ability high.
(2) grid length of MESFET devices of the invention determines that its thickness limit can by the gate metal thickness for depositing
To reach monoatomic layer thickness, i.e. the limit of photoetching can be broken through, therefore device operating frequencies can be greatly improved.
(4) MESFET devices of the invention make when, without consider as existing planar structure device grid, leak
Pole, the lead crossover problem of source electrode, can greatly simplify technology difficulty, improve yield rate.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments described in invention, for those of ordinary skill in the art, on the premise of not paying creative work,
Other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is that a kind of stereochemical structure of MESFET devices based on vertical-channel in an exemplary embodiments of the invention is illustrated
Figure.
Fig. 2 is a kind of front view of the MESFET devices based on vertical-channel in an exemplary embodiments of the invention.
Fig. 3 is a kind of top view of the MESFET devices based on vertical-channel in an exemplary embodiments of the invention.
Fig. 4 is a kind of left view of the MESFET devices based on vertical-channel in an exemplary embodiments of the invention.
Fig. 5 is a kind of front view of the MESFET devices based on vertical-channel in another exemplary embodiments of the invention.
Fig. 6 is a kind of top view of the MESFET devices based on vertical-channel in another exemplary embodiments of the invention.
Fig. 7 is a kind of left view of the MESFET devices based on vertical-channel in another exemplary embodiments of the invention.
Specific embodiment
A kind of MESFET devices (VC-MESFET) based on vertical-channel that the one side of the embodiment of the present invention is provided,
Including MES structures, source electrode and drain electrode, the MES structures include grid and at least semiconductor raceway groove, the semiconductor channel
Axis be basically perpendicular to a selected plane, the grid is set around the semiconductor channel, and the source electrode is partly led through described
Bulk channel is electrically connected with the drain electrode, and the source electrode and drain electrode are set along the semiconductor channel axially spaced-apart, the grid point
It is distributed between source electrode and drain electrode.
Foregoing " being basically perpendicular to " refer to the semiconductor channel axis it is in 90 ° with the selected plane or close to
90 ° of angle, i.e., the mode that described semiconductor channel can stand relative to the selected plane standing or inclination is set.
Wherein, because foregoing source electrode and drain electrode are set along semiconductor channel axially spaced-apart, and grid is located between source, drain electrode,
That is, source, leakage, grid are non-coplanar, so the problems such as need not considering the lead crossover of grid, drain electrode, source electrode when making, can
To greatly simplify technology difficulty.
Wherein, because foregoing grid is set around semiconductor channel.That is, foregoing grid can be realized entirely to semiconductor channel
Angle is surrounded, and so can to greatest extent improve grid-control ability.
Further, aforesaid semiconductor raceway groove can be column, and its radial section can be circle, regular hexagon, three
One kind in angular or other closed polygons.That is, the semiconductor channel can be with cylindrical, prism-shaped etc..
Further, the length and diameter of aforesaid semiconductor raceway groove can be according to being actually needed and relative set.
For example, aforesaid semiconductor raceway groove is nano-pillar, i.e. its diameter can be nano level.
For example, the length of aforesaid semiconductor raceway groove can reach nanoscale, when it is less than qualified value, will make
The MESFET devices have more best performance, for example, produce the performances such as ballistic transport.
Further, the length (that is, the thickness on the semiconductor channel axial direction) of foregoing grid can be by grid
The deposit thickness of metal is controlled, thus can with minimum, or even the limit that photoetching can be broken through, it might even be possible to reach single electron
Thickness degree, thus device operating frequencies can be greatly improved, until device operating frequencies are extended into terahertz wave band.
Likewise, for the source electrode and drain electrode, its length (that is, the thickness on the semiconductor channel axial direction
Degree) can also be controlled by the deposit thickness to source metal, leakage metal.
Further, foregoing grid forms Schottky contacts with semiconductor channel.
Further, foregoing source electrode and drain electrode forms Ohmic contact with semiconductor channel, so that source, drain electrode can be by half
Conductor channel forms electrical connection.
In some preferred embodiments, the distance between foregoing grid and source electrode less than between grid and drain electrode away from
From to obtain larger breakdown voltage.
In some embodiments, the source electrode and drain electrode can be respectively arranged at semiconductor channel two ends.Also, institute
The position for stating source electrode and drain electrode can exchange.
In some preferred embodiments, at least one of the source electrode, drain electrode and grid are parallel to described selected flat
Face.
Further, foregoing source electrode, drain electrode and grid so can further simplify source, leakage each parallel to the selected plane
And the manufacture craft of grid, reduce cost of manufacture.
Further, between foregoing grid and source electrode and foregoing grid and drain electrode between overlapping area (also it is believed that
Grid with source electrode and/or drain in the overlapping area of the orthographic projection in the selected plane) should be as far as possible small, to reduce very as far as possible
To grid source, gate-drain parasitic capacitances are completely eliminated.
In some more specific case study on implementation, the source electrode includes source contact ring, and the source contact ring surround
The semiconductor channel is set.Further, the source contact ring can also be electrically connected through connecting line with source lead disk.
In some more specific case study on implementation, the drain electrode includes drain contact ring, and the drain contact ring surround
The semiconductor channel is set.Further, the drain contact ring can also be electrically connected through connecting line with drain lead disk.
In some more specific case study on implementation, the grid includes gate contact ring, and the gate contact ring surround
The semiconductor channel is set.Further, the gate contact ring can also be electrically connected through connecting line with grid lead disk.
Further, at least one of foregoing source contact ring, drain contact ring and gate contact ring and described half
Conductor channel is coaxially disposed.
In some preferred embodiments, the gate contact ring in the semiconductor channel is coaxially disposed with semiconductor.
Further, at least one of foregoing source contact ring, drain contact ring and gate contact ring are parallel to institute
State selected plane.
In some embodiments, at least one of the source electrode and drain electrode between grid also retain or do not retain every
From insulating medium layer.Preferably, any one of the source electrode and drain electrode between grid without isolated insulation dielectric layer.Enter one
Step, the material of foregoing isolated insulation dielectric layer can be selected from the material that the industries such as silica, silicon nitride, aluminum oxide are commonly used.
In some preferred embodiments, the grid can also have field plate structure.
In some more specific case study on implementation, the MESFET devices may also include substrate, and the selected plane is
The substrate principal plane, and the semiconductor channel is formed on the substrate principal plane.
Further, the substrate that the substrate can be commonly used selected from industry, such as Sapphire Substrate, GaN substrate, SiC linings
Bottom etc., and not limited to this.
In some preferred embodiments, the MESFET devices may also include and be formed by a plurality of semiconductor channels
Channel array (also referred to as raceway groove cluster), can so improve device current.Obvious, by controlling the semiconductor channel battle array
Quantity of row etc., can also realize the accuracy controlling to device current.
Further, the semiconductor channel array can be using the known lattice structure of industry.
The MESFET devices based on vertical-channel can be made up of commonly seeing process for fabricating semiconductor device.
It is summarized, compared with existing plane HEET, MESFET device of the present invention based on vertical-channel has following excellent
Point：First, the gate electrode length of device is decided by the thickness of metal, it is not necessary to defined by photoetching process, therefore, it can break through
Photoetching resolution is limited, and obtains minimum grid long.There is extremely important meaning for improving device frequency characteristic.Second, due to grid
360 ° of encirclement raceway grooves of electrode, it is possible to grid-control ability is greatly improved, so as to obtain very high transconductance and reduce off-state current.
The other side of the embodiment of the present invention is additionally provided and a kind of makes the foregoing MESFET devices based on vertical-channel
Method, it can include：
In forming at least semiconductor raceway groove on substrate principal plane, the axis of the semiconductor channel is basically perpendicular to described
Substrate principal plane；
Source electrode, grid and drain electrode are made, and the source electrode is electrically connected through the semiconductor channel with drain electrode, wherein described
Source electrode and drain electrode are set along the semiconductor channel axially spaced-apart, and the grid is distributed between source electrode and drain electrode.
Further, in the preparation method, can be by physics and/or change known to the industries such as MOCVD, PECVD
Mode is equal to growth or deposition on substrate principal plane and forms the semiconductor channel.
Further, in the preparation method, can make to form foregoing by modes such as metal sputtering, atom laminations
Source electrode, drain electrode, grid etc..And the material of these electrodes can also be selected from metal or the nonmetallic materials that industry is commonly used, particularly
Metal material, such as Au, Ni, Ti etc..
Further, in the preparation method, it is also possible to by physically and/or chemically depositional mode shape known to industry
Into foregoing isolated insulation dielectric layer etc..
Further, described preparation method may also include：Partly led by a plurality of described in being formed on substrate principal plane
The channel array that bulk channel is formed, makes the source electrode, grid and drain electrode afterwards.
Further, described preparation method also includes：Make to form Xiao Te between the grid and the semiconductor channel
Base is contacted.
Further, described preparation method also includes：The source electrode and drain electrode is set to form Europe with the semiconductor channel
Nurse is contacted.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, detailed retouching is carried out to the technical scheme in the embodiment of the present invention
State, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based on the present invention
In embodiment, the every other implementation that those of ordinary skill in the art are obtained on the premise of creative work is not made
Example, belongs to the scope of protection of the invention.
It is a kind of MESFET (VC- based on vertical-channel in an exemplary embodiments of the invention to refer to shown in Fig. 1
MESFET) device, it is including substrate, MES structures, source electrode and drain electrode etc..
The MES structures include grid and semiconductor channel.
Wherein, the semiconductor channel can be made up of the semiconductor structure a of column.Semiconductor structure a is perpendicular to substrate
Principal plane is set.
Wherein, the grid is set around semiconductor channel, and between source, drain electrode.
Wherein, the source electrode and drain electrode can be respectively arranged at the upper/lower terminal of semiconductor channel, and be formed with semiconductor channel
Ohmic contact so that source, drain electrode can be formed by semiconductor channel and electrically connected.
The material of aforesaid semiconductor raceway groove can be the III~V such as GaN races semi-conducting material etc..
Foregoing grid, source electrode, the material of drain electrode can be selected from Suitable metal materials known to industry.
Further, the drain electrode can include that drain contact ring c1, drain contact ring c1 can be connected by draining
Line c3 is electrically connected with drain lead disk c2.
Further, the grid can include that gate contact ring e1, gate contact ring e1 can be connected by grid
Line e3 is electrically connected with grid lead disk e2.The gate contact ring g1 and semiconductor structure a cooperatively forms coaxial MES structures.
Further, the source electrode can include that source contact ring g1, source contact ring g1 can be connected by source electrode
Line g3 is electrically connected with source lead disk g2.
Further, isolated insulation can be also distributed between the source electrode and grid and/or between the drain electrode and grid
Dielectric layer.Further, the material of the dielectric layer can be Si3N4Deng, and not limited to this.
A kind of method for preparing the VC-MESFET devices in an exemplary embodiments of the invention can include following step
Suddenly：
(1) semiconductor channel is formed on the selected substrate.
(2) drain electrode is formed, including around the drain contact ring c1 of semiconductor channel.Wherein, for some semiconductors, it is necessary to
First drain region is doped, Ohmic contact is then formed, so as to form drain electrode.And for some semiconductors, such as GaN, Ke Yizhi
Connect and form Ohmic contact with GaN using Ti Base Metals storehouse (such as Ti/Al/Ni/Au) alloying, so as to form drain electrode.
(3) the isolated insulation dielectric layer between deposition grid, leakage.
(4) grid is formed, including around the gate contact ring e1 of semiconductor channel.Shape between the grid and semiconductor channel
Into Schottky contacts.
(5) the isolated insulation dielectric layer between deposition grid, source.
(6) source electrode is formed, including around the source contact ring g1 of raceway groove.Wherein, for some semiconductors, it is necessary to first to source
Area is doped, and then forms Ohmic contact, so as to form source electrode.And for some semiconductors, such as GaN, can directly utilize
Ti Base Metals storehouse (such as Ti/Al/Ni/Au) alloying forms Ohmic contact with GaN, so as to form source electrode.
(7) grid of the removal outside lead wire tray and the isolated insulation dielectric layer between drain electrode, grid and source electrode.
(8) etching forms source electrode, grid, the contact hole of drain lead disk.
(9) source electrode, grid, drain lead are made.
Further, foregoing drain bond wires c3, gate connection line e3, source connection lines g3 are all not parallel.
Fig. 2~Fig. 4 is referred to again, and a kind of MESFET based on vertical-channel in an exemplary embodiments of the invention can be wrapped
Include the coaxial MES structures of substrate 2, column, source electrode 3 and drain electrode 5.Wherein, the coaxial MES structures of the column are main by semiconductor channel
Contact loop section with grid is cooperatively formed, and wherein semiconductor channel is formed by semiconductor structure 1.The coaxial MES structures of the column
It is vertically installed in substrate principal plane.Source electrode and drain electrode are located at the coaxial MES structures two ends of the column respectively, are formed with semiconductor channel
Ohmic contact, source electrode and drain metal are parallel with substrate principal plane.Grid is located between source, drain electrode.Gate metal and substrate master
Plane is parallel.
In the MESFET devices of the exemplary embodiments, material, diameter, length, shape of semiconductor structure etc. can be according to
Depending on being actually needed, for example, semiconductor structure can be GaAs nano wires, diameter can be 100nm, and semiconductor structure
In also carried out N-shaped doping with the GaAs of source electrode, the corresponding drain region of drain electrode and source region, and the radial section of semiconductor structure can be with
It is the shapes such as circle.The length of postscript, wherein semiconductor channel, the distance between Ye Jiyuan, drain electrode can also be according to actual need
Depending on wanting, for example, can be 50nm.Wherein, the grid length of the MESFET devices, source, drain electrode distance, grid, source electrode distance etc.
Depending on can be according to being actually needed, for example, grid length can be 5nm, source, drain electrode distance can be 30nm, grid, source electrode away from
From that can be 15nm, drain and may be located at the top side of the MESFET devices, source electrode may be located at the bottom side of the MESFET devices.And
Source, the thickness of drain electrode give rationally design according to the total output current requirement size for crossing device.
In another exemplary embodiments of the invention, a kind of MESFET (VC-MESFET) device based on vertical-channel
There can be the structure shown in Fig. 5~Fig. 7, in Fig. 5~Fig. 7, the lexical or textual analysis of each reference is the same as those described above.
Further, the VC-MESFET devices are including substrate, MES structures, source electrode and drain electrode etc..
The MES structures include the channel array that grid and some semiconductor channels are formed.
Wherein, each semiconductor channel can be made up of the semiconductor structure a of a column.These semiconductor structures a hangs down
It is straight to be set in substrate principal plane.
Wherein, the grid is set around semiconductor channel, and between source, drain electrode.
The source electrode and drain electrode can be respectively arranged at the upper/lower terminal of semiconductor channel, and form ohm with semiconductor channel
Contact so that source, drain electrode can be formed by semiconductor channel and electrically connected.
Aforesaid semiconductor structure a can be the GaN grown along c-axis, depending on its diameter can be according to being actually needed, for example may be used
Think 0~2 μm (not being 0).
The length of aforesaid semiconductor raceway groove, depending on the distance between Ye Jiyuan, drain electrode can be according to being actually needed, for example may be used
Think 100nm.
Aforementioned trenches array can be dot matrix form, for example, can be distributed as 3*3 square lattices.
The radial section of foregoing grid and semiconductor structure can be the shapes such as circle.
In the MESFET devices of the exemplary embodiments, the grid length of device, source, drain electrode distance, grid, source electrode distance etc.
Also depending on can be according to being actually needed, for example, grid length can be 10nm, source, drain electrode distance can be 60nm, grid, source
, from that can be 30nm, positioned at the MESFET devices bottom side, source electrode be positioned at the MESFET devices top side for drain electrode for pole span.Source, drain electrode
Thickness gives rationally design according to the total output current requirement size for crossing device.
The present invention is not limited to foregoing embodiment.In fact, many utilization the technology of the present invention features can also be had not
The change form of same type design.For example, in foregoing case study on implementation, between grid and drain electrode and source electrode and grid it
Between also can be set alumina medium layer etc..
It should be noted that herein, term " including ", "comprising" or its any other variant be intended to non-row
His property is included, so that process, method, article or equipment including a series of key elements not only include those key elements, and
And also include other key elements being not expressly set out, or also include for this process, method, article or equipment institute are intrinsic
Key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that including institute
Also there is other identical element in process, method, article or the equipment of stating key element.
It should be appreciated that the above is only specific embodiment of the invention, for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of MESFET devices based on vertical-channel, including MES structures, source electrode and drain electrode, the MES structures include grid
And at least semiconductor raceway groove, it is characterised in that：The axis of the semiconductor channel is basically perpendicular to a selected plane, described
Grid is set around the semiconductor channel, and the source electrode is electrically connected through the semiconductor channel with the drain electrode, the source electrode
Set along the semiconductor channel axially spaced-apart with drain electrode, the grid is distributed between source electrode and drain electrode.
2. MESFET devices based on vertical-channel according to claim 1, it is characterised in that：The MESFET devices bag
Include the channel array formed by a plurality of described semiconductor channels.
3. MESFET devices based on vertical-channel according to claim 1, it is characterised in that：The semiconductor channel is
Column；Preferably, the radial cross-sectional shape of the semiconductor channel includes polygon or circle；Preferably, the semiconductor ditch
Road is nano-pillar.
4. MESFET devices based on vertical-channel according to claim 1, it is characterised in that：The grid and described half
Conductor channel forms Schottky contacts；And/or, the source electrode and drain electrode form Ohmic contact with the semiconductor channel；It is preferred that
, the distance between the grid and source electrode are less than the distance between the grid and drain electrode；Preferably, the source electrode and drain electrode
It is respectively provided with the semiconductor channel two ends；Preferably, at least one of the source electrode, drain electrode and grid are parallel to described
Selected plane；Preferably, the source electrode, drain electrode and grid are each parallel to the selected plane；Preferably, the source electrode includes source
Pole contacts ring, and the source contact ring is set around the semiconductor channel；Preferably, the source contact ring through connecting line with
Source lead disk is electrically connected；Preferably, the drain electrode includes drain contact ring, and the drain contact ring is around the semiconductor ditch
Road is set；Preferably, the drain contact ring is electrically connected through connecting line with drain lead disk；Preferably, the grid includes grid
Pole contacts ring, and the gate contact ring is set around the semiconductor channel；Preferably, the gate contact ring through connecting line with
Grid lead disk is electrically connected；Preferably, at least one of the source contact ring, drain contact ring and gate contact ring and institute
Semiconductor channel is stated to be coaxially disposed；Preferably, at least one of the source contact ring, drain contact ring and gate contact ring
Parallel to the selected plane.
5. MESFET devices based on vertical-channel according to claim 1, it is characterised in that：In the source electrode and drain electrode
At least one also retain between grid or do not retain isolated insulation dielectric layer；Preferably, appointing in the source electrode and drain electrode
Without isolated insulation dielectric layer between one and grid；And/or, the grid has field plate structure；And/or, the MESFET
Device also include substrate, the selected plane be the substrate principal plane, and the semiconductor channel be formed at substrate master put down
On face.
6. a kind of preparation method of the MESFET devices based on vertical-channel, it is characterised in that including：
In at least semiconductor raceway groove is formed on substrate principal plane, the axis of the semiconductor channel is basically perpendicular to the substrate
Principal plane；Source electrode, grid and drain electrode are made, and the source electrode is electrically connected through the semiconductor channel with drain electrode, wherein described
Source electrode and drain electrode are set along the semiconductor channel axially spaced-apart, and the grid is distributed between source electrode and drain electrode.
7. preparation method according to claim 6, it is characterised in that including：In being formed on substrate principal plane by a plurality of institutes
The channel array that the semiconductor channel stated is formed, makes the source electrode, grid and drain electrode afterwards.
8. preparation method according to claim 6, it is characterised in that also include：Make the grid with the semiconductor channel
Between form Schottky contacts；And/or, the source electrode and drain electrode is formed Ohmic contact with the semiconductor channel.
9. MESFET devices based on vertical-channel according to claim 1, it is characterised in that：The semiconductor channel is
Column；Preferably, the radial cross-sectional shape of the semiconductor channel includes polygon or circle；Preferably, the semiconductor ditch
Road is nano-pillar.
10. preparation method according to claim 7, it is characterised in that：The distance between the grid and source electrode are less than institute
State the distance between grid and drain electrode；Preferably, the source electrode and drain electrode is respectively provided with the semiconductor channel two ends；It is preferred that
, at least one of the source electrode, drain electrode and grid are parallel to the selected plane；Preferably, the source electrode, drain electrode and grid
Pole is each parallel to the selected plane；Preferably, the source electrode includes source contact ring, and the source contact ring is around described half
Conductor channel is set；Preferably, the source contact ring is electrically connected through connecting line with source lead disk；Preferably, the drain electrode
Including drain contact ring, the drain contact ring is set around the semiconductor channel；Preferably, the drain contact ring is through even
Wiring is electrically connected with drain lead disk；Preferably, the grid includes gate contact ring, and the gate contact ring is around described half
Conductor channel is set；Preferably, the gate contact ring is electrically connected through connecting line with grid lead disk；Preferably, the source electrode
At least one of contact ring, drain contact ring and gate contact ring are coaxially disposed with the semiconductor channel；Preferably, it is described
At least one of source contact ring, drain contact ring and gate contact ring are parallel to the selected plane；And/or, the source
Also retain or do not retain isolated insulation dielectric layer between at least one of pole and drain electrode and grid；Preferably, the source electrode and
Any one of drain electrode is between grid without isolated insulation dielectric layer；And/or, the grid has field plate structure；And/or,
The MESFET devices also include substrate, and the selected plane is the substrate principal plane, and the semiconductor channel formed
In on substrate principal plane.
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| CN201710086828.7A CN106876482A (en) | 2017-02-17 | 2017-02-17 | MESFET devices based on vertical-channel and preparation method thereof |
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| CN201710086828.7A CN106876482A (en) | 2017-02-17 | 2017-02-17 | MESFET devices based on vertical-channel and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11233157B2 (en) | 2018-09-28 | 2022-01-25 | General Electric Company | Systems and methods for unipolar charge balanced semiconductor power devices |
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| CN1731587A (en) * | 2005-08-05 | 2006-02-08 | 西安电子科技大学 | Vertical type wide bandgap semiconductor device structure and making method |
| CN103633141A (en) * | 2012-08-24 | 2014-03-12 | 台湾积体电路制造股份有限公司 | System and method for a vertical tunneling field-effect transistor cell |
| US20150021664A1 (en) * | 2013-07-18 | 2015-01-22 | Sensor Electronic Technology, Inc. | Lateral/Vertical Semiconductor Device with Embedded Isolator |
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2017
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1731587A (en) * | 2005-08-05 | 2006-02-08 | 西安电子科技大学 | Vertical type wide bandgap semiconductor device structure and making method |
| CN103633141A (en) * | 2012-08-24 | 2014-03-12 | 台湾积体电路制造股份有限公司 | System and method for a vertical tunneling field-effect transistor cell |
| US20150021664A1 (en) * | 2013-07-18 | 2015-01-22 | Sensor Electronic Technology, Inc. | Lateral/Vertical Semiconductor Device with Embedded Isolator |
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| US11233157B2 (en) | 2018-09-28 | 2022-01-25 | General Electric Company | Systems and methods for unipolar charge balanced semiconductor power devices |
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Application publication date: 20170620 |