CN106876470A - A kind of trench gate metal oxide field-effect transistor and its manufacture method - Google Patents
A kind of trench gate metal oxide field-effect transistor and its manufacture method Download PDFInfo
- Publication number
- CN106876470A CN106876470A CN201710179875.6A CN201710179875A CN106876470A CN 106876470 A CN106876470 A CN 106876470A CN 201710179875 A CN201710179875 A CN 201710179875A CN 106876470 A CN106876470 A CN 106876470A
- Authority
- CN
- China
- Prior art keywords
- type
- layer
- doped region
- type doped
- lithography
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 23
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 23
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- 238000000407 epitaxy Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000001459 lithography Methods 0.000 claims description 50
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 31
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 27
- 239000000377 silicon dioxide Substances 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 16
- 238000002347 injection Methods 0.000 claims description 15
- 239000007924 injection Substances 0.000 claims description 15
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 14
- 238000007667 floating Methods 0.000 claims description 13
- 229910052759 nickel Inorganic materials 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 101100207343 Antirrhinum majus 1e20 gene Proteins 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000013461 design Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- -1 phosphonium ion Chemical class 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 238000007669 thermal treatment Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 230000005684 electric field Effects 0.000 abstract description 11
- 230000024241 parasitism Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000779 depleting effect Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of trench gate metal oxide field-effect transistor of the invention, including：Front, back metal electrode, N-type single crystalline substrate, N-type epitaxy layer, first p-type doped region, vertical trench is provided with the middle body of N-type epitaxy layer and the first p-type doped region, it is first medium layer between gate lateral wall in the trench and the first p-type doped region, it is second dielectric layer between gate bottom and epitaxial layer, on the first p-type doped region the first n-type doping area is provided near groove both sides, the second p-type doped region is additionally provided with away from groove both sides, the 3rd p-type doped region and the second n-type doping area being in contact with second dielectric layer lower section are additionally provided with inside epitaxial layer, make the 3rd p-type doped region and the second interlaced interval in n-type doping area, multiple PN junction units are formed in length direction and thickness direction.The present invention can reduce the parasitic capacitance between the grid of trench gate SiC MOSFET and drain electrode, reduce channel bottom electric-field intensity and suppress the unlatching of parasitism BJT.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of trench gate metal oxide field-effect transistor and its
Manufacture method.
Background technology
High voltage power device it is pressure-resistant proportional with device Withstand voltage layer thickness.And Withstand voltage layer thickness is critical with material
Electric field is inversely.Because carbofrax material critical electric field is approximately 10 times of silicon, therefore power is prepared using carbofrax material
During device, the resistance to pressure request of identical can be realized using relatively thin Withstand voltage layer, while also helping reduction device on-resistance.Remove
Outside this, carborundum (SiC) also have excellent physically and electrically characteristic, with broad stopband it is big, disruptive field intensity is high, electronics high satisfy
The advantages of with drift speed and extremely strong Radiation hardness and mechanical strength.Therefore, SiC turns into the high-power, high temperature of development, height
The preferred material of frequency power device, be widely used prospect.SiC MOS memories (MOSFET)
With conducting resistance it is low, switching loss is low the characteristics of, be more suitable for high-frequency work state.
But in trench gate SIC MOSFET, maximum field Intensity Transfer easily causes hot load to trench gate bottom corners
Trap capture is flowed at sub- injector grid oxide layer or oxidized bed boundary, the problems such as cause device threshold voltage drift, device is influenceed
Part is reliably and with long-term used.Meanwhile, due to the parasitic capacitance between grid and drain electrode in trench gate, postpone when causing device to turn off
Time is excessive, the situation of grid voltage easily vibration during unlatching.On the other hand, MOSFET element is in switching process, due to big electricity
Stream high voltage exists simultaneously, when the holoe carrier that ionization by collision is produced at big electric field in device flows out via the p-well in MOS areas,
Voltage drop is produced in p-well, when voltage drop increases to certain PN junction cut-in voltage, by source region N+ layers, p-well, N-type Withstand voltage layer group
Into parasitic BJT open, cause device second breakdown, fail.
The content of the invention
It is an object of the invention to propose a kind of trench gate metal oxide field-effect transistor and its manufacture method, reduce
Parasitic capacitance between the grid of trench gate SiC MOSFET and drain electrode, reduces channel bottom electric-field intensity and suppresses parasitism BJT
Unlatching.
On the one hand, the invention provides a kind of trench gate metal oxide field-effect transistor, including：Front metal electricity
Pole, back metal electrode, the N-type single crystalline substrate on the back metal electrode, the N formed in the N-type single crystalline substrate
Type epitaxial layer, the first p-type doped region formed in the N-type epitaxy layer, mixes in the N-type epitaxy layer and first p-type
The middle body in miscellaneous area is provided with vertical groove, and grid, the first p-type described in the depth ratio of the grid are provided with the trench
The junction depth of doped region is deeper, is first medium layer, the gate bottom between the gate lateral wall and the first p-type doped region
It is second dielectric layer between the epitaxial layer, the second dielectric layer thickness is more than the first medium thickness degree, described
The first n-type doping area is provided near the groove both sides on first p-type doped region, the 2nd P is additionally provided with away from the groove both sides
Type doped region, the first n-type doping area and the second p-type doped region are connected with the front metal electrode respectively, institute
The 3rd p-type doped region and the second n-type doping area for being additionally provided with inside epitaxial layer and being in contact with second dielectric layer lower section are stated, is made
The 3rd p-type doped region and the interlaced interval in the second n-type doping area, multiple is formed in length direction and thickness direction
PN junction unit.
Further, impurity dose of the impurity dose of the 3rd p-type doped region more than the second n-type doping area.
Further, the N-type single crystalline substrate and the N-type epitaxy layer are silicon materials or carbofrax material.
Further, the grid is in a thickness direction the repeat unit of multiple H shapes so that the grid is in length
The grid of left and right two of symmetrical separation is partly rendered as on direction.
Further, the second p-type doped region is located at the first n-type doping area bottom, and front metal electricity
The contact hole of pole directly contacts the second p-type doped region surface, the second p-type doped region and the front metal electrode
The depth of contact surface is equal to or more than the depth in the first n-type doping area；And make the second p-type doped region with described
The distance of one dielectric layer is less than the first n-type doping sector width；The doping concentration of the second p-type doped region is more than described the
The concentration of one p-type doped region.
Further, the impurity dose Q of the 3rd p-type doped regionpWith the impurity dose Q in the second n-type doping arean
Following relation should be met：
Wherein, VBIt is the device pressure voltage of demand, K is the pressure-resistant design department set in view of end use efficiency when designing device
Number, the span of K is 1.3~1.5；WpIt is the width of the 3rd p-type doped region.
Further, the second dielectric layer thickness is at least more than 2 times of the first medium thickness degree.
Further, the grid width W of each separation2With the groove width W, following relation should be met：
W≥2*W2+0.5μm
Further, the front metal electrode is nickel, aluminium more metal layers；The back metal electrode be nickel, titanium,
Nickel, silver or titanium, nickel, the more metal layers of silver.
On the other hand, present invention also offers a kind of method of manufacture groove gate metal oxide field-effect transistor, institute
State transistor and include 7 layers of lithography layer, alignment mark lithography layer, N+ injections lithography layer, p-type injection light are respectively according to production order
Carve layer, etching groove lithography layer, p-type floating implanted layer, N-type floating implanted layer, P+ injections lithography layer, gate lithography layer, contact
Hole etches lithography layer, front metal lithography layer, and methods described includes：
Alignment mark is etched using alignment mark lithography layer on epitaxial layer, is used for follow-up photoetching contraposition；
The micron silica of chemical vapor deposition 2, injecting lithography layer using N+ carries out N+ implanted layers injection opening etch, so
The multiple ion implantation doping of N+ implanted layers is carried out afterwards；
By etching silicon dioxide, and 0.3 micron silica is deposited again, lithography layer is injected using p-type, form injection
Window, and the multiple ion implanting of p-type doped region is carried out, form the first p-type doped region；
The silica that 0.5 micron of chemical vapor deposition, using etching groove lithography layer, etching silicon dioxide forms ditch
Groove etched window, using RIE lithographic techniques, it is 2.2 microns that depth is etched in silicon carbide epitaxial layers, and width is 1.7 microns
Groove；
Using p-type floating implanted layer, aluminium ion is carried out to channel bottom and is repeatedly injected；
Using N-type floating implanted layer, phosphonium ion is carried out to channel bottom and is repeatedly injected；
Injecting lithography layer using P+ carries out the multiple ion implanting of P+ implanted layers.In 1550 DEG C~1700 DEG C of temperature range
Inside carry out injecting the high-temperature annealing activation of ion.Form 0.3 micron of depth, first N-type of mean concentration 1e18~4e20cm-3
Doped region；1.5 microns of depth, the first p-type doped region of mean concentration 9e17~5e18cm-3；1.5 microns of depth, mean concentration
The 3rd p-type doped region of 8e15~1e16cm-3；1.5 microns of depth, second N-type of mean concentration 7.5e15~9.5e15cm-3
Doped region；
Deposit and etch by multiple oxide layer, form the second dielectric layer that channel bottom thickness is 200nm, trenched side-wall
Thickness is the first medium layer of 55nm.0.55 micron of deposition thickness, the n-type doping polysilicon of doping concentration 1e20~3e20cm-3
Grid, makes gate lithography layer etching form gate patterns layer；
Etching window is formed using contact hole etching lithography layer, by RIE etching silicon carbide epitaxial layers, forming depth is
0.3 front metal electrode contact hole, and 0.2~0.3 micron of isotropic etching is carried out to silicon dioxide layer；
Front deposits Ti/Al metal levels, and carries out rapid thermal treatment, forms Ohmic contact.Etched using gate lithography layer
Metal level, forms front metal layer pattern；
The back side deposit 40~80nm Ti 400~650nm Ni 900~1500nm Ag metal levels.
The beneficial effects of the invention are as follows：Grid is slot type structure in structure proposed by the present invention, and channel bottom has thickness
Dielectric layer, is the 3rd p-type doped region and the set on XY sections and thickness direction i.e. YZ sections in channel bottom length direction
Two n-type doping areas are spaced, due to depletion layer charge between the PN junction that the 3rd p-type doped region and the second n-type doping area are formed
It is shared, exhausting for the 3rd p-type doped region and the second n-type doping area is will further enhance, be conducive to making the body carbon of trench gate bottom
SiClx is rapidly depleting, reaches the effect of parasitic capacitance rapid decrease between grid and back metal electrode.
Some preferred embodiments of the invention also have following beneficial effect：
Impurity dose of the impurity dose of the 3rd p-type doped region more than the second n-type doping area so that under identical voltage, the
The depletion width of three p-type doped regions is less than the second doped region so that peak electric field is transferred to outside the 3rd p-type doped region and N-type
Prolong the PN junction bottom of layer formation, peak electric field advantageously reduces gate electric field away from gate dielectric layer, reduces hot carrier in jection,
Strengthen the reliability of gate dielectric layer.
Using separate grid, the area of medium layer capacitance between grid and back metal electrode can be reduced, be conducive to
Reduce reverse transfer capacitance between the two.But compared with the non-separate gate electrode of tradition, the gate electrode width after separation diminishes,
So that the equivalent resistance increase of gate electrode, is unfavorable for the quickly and uniformly switch of device.Therefore, compartment is used to gate electrode
Isolating construction, i.e., in the Z-axis direction formed H-shaped separate gate electrodes structure.So reaching both reduced between grid and electrode
Parasitic capacitance, gate electrode resistance will not again significantly increased.
Second p-type doped region 9b is located at the first n-type doping area 2b bottoms, and the contact hole of front metal 1b is directly contacted
Second p-type doped region 9b surfaces, with the second traditional p-type doped region and the structure phase of the first n-type doping area same level position
Than this structure is conducive to shortening the holoe carrier of ionization by collision generation in device via the first p-type doped region outflow front gold
The path length of category, that is, shorten the length that holoe carrier flows through dead resistance on path；The doping of the second p-type doped region simultaneously
Concentration is higher, and the resistivity of the semiconductor on path can be flowed through with holoe carrier, and holoe carrier flows through the parasitism electricity in path
The decline of resistance length and resistivity, will bring the decline of dead resistance, so as to reduce on the second p-type doped region on current path
Pressure drop, it is suppressed that the unlatching of the PN junction that the first n-type doping area and the first p-type doped region are formed, it is suppressed that the unlatching of parasitic BJT.
And the width W6 apart from W5 less than the first n-type doping area 2b of the second p-type doped region 9b and first medium floor 3b, can prevent highly concentrated
Second doped region 9b of degree has influence on the concentration of the first p-type doped region at first medium layer 3b surfaces, it is possible to prevente effectively from the
The influence of the impurity concentration of two p-type doped region 9b causes device threshold voltage waveform.
Brief description of the drawings
Fig. 1 is section of the trench gate metal oxide field-effect transistor of the offer of the embodiment of the present invention one on XY sections
Figure；
Fig. 2 is the tomograph of the trench gate metal oxide field-effect transistor that the embodiment of the present invention one is provided；
Fig. 3 is the tomograph of the first variant that the embodiment of the present invention one is provided；
Fig. 4 is the tomograph of second variant that the embodiment of the present invention one is provided；
Fig. 5 is section of the trench gate metal oxide field-effect transistor of the offer of the embodiment of the present invention two on XY sections
Figure；
Fig. 6 is the tomograph of the trench gate metal oxide field-effect transistor that the embodiment of the present invention two is provided；
Fig. 7 is threeth p-type doped region 5bs of the grid 11b of the embodiment of the present invention two with undoped spacer and the second n-type doping area
The top view of 12b；
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Embodiment 1
It is as shown in Figure 1 a kind of trench gate metal oxide field-effect transistor of the offer of the embodiment of the present invention 1, including just
Face metal electrode 1a, back metal electrode 8a, the overleaf N-type single crystalline substrate 7a on metal electrode 8a, in N-type single crystalline substrate 7a
The N-type epitaxy layer 6a of upper formation, the first p-type doped region 10a formed on N-type epitaxy layer 6a.In N-type epitaxy layer 6a and first
The middle body of p-type doped region 10a is provided with vertical groove, and grid 11a, the P of depth ratio the of grid 11a are provided with the trench
The junction depth of type doped region 10a is deeper, and it is W that both differ3-T2, it is first between grid 11a side walls and the first p-type doped region 10a
Dielectric layer 3a, is second dielectric layer 4a between grid 11a bottoms and epitaxial layer 6a.Near groove on the first p-type doped region 10a
Both sides are provided with the first n-type doping area 2a, and the second p-type doped region 9a, the first n-type doping area 2a and are additionally provided with away from groove both sides
Two p-type doped region 9a are connected with front metal electrode 1a respectively.Wherein, front metal electrode 1a be nickel, aluminium more metal layers,
Back metal electrode 8a is nickel, titanium, nickel, silver or titanium, nickel, the more metal layers of silver；First medium layer 3a and second dielectric layer 4a
It is gate silicon dioxide dielectric layer and material is identical, the thickness of first medium layer 3a is T1, the thickness of second dielectric layer 4a is
T2。T1Less than T2, and T2Thickness is at least T1More than 2 times of thickness.N-type epitaxy layer 6a and N-type single crystalline substrate 7a can be silicon material
Material or carbofrax material.Grid 11a is the polysilicon gate of N-type impurity doping, is operationally contacted by aluminum metal and drawn.
The 3rd p-type doped region 5a and being in contact with below second dielectric layer 4a are additionally provided with inside N-type epitaxy layer 6a
Two n-type doping area 12a, the 3rd p-type doped region 5a and the second n-type doping area interlaced intervals of 12a, make in length direction i.e. XY
Section and thickness direction are that multiple PN junction units are formed on YZ sections.When device works, both current potential floatings, it is not necessary to electricity
Draw pole.In the present embodiment, the 3rd p-type doped region 5a is distributed in the both sides of the second n-type doping area 12a on XY sections, often
The width of individual 3rd p-type doped region 5a is Wp, the width of the second n-type doping area 12a is Wn, the 3rd p-type in left side is adulterated
Area 5a and the second n-type doping area 12a one PN junction of formation, and the 3rd p-type doped region 5a on right side and the second n-type doping area 12a
Form another PN junction.As shown in Fig. 2 being again provided with p-type doped region and the n-type doping area at interval, each N on YZ sections
The spacing distance of type doped region is Wp, each n-type doping area is Z along Z axis width2, due to spaced p-type doped region and N-type
Doped region, can equally form multiple PN junction units.
The operation principle of the present embodiment：Forward voltage is applied to grid 11a, front metal electrode 1a connects low potential, the back side
Metal electrode 8a connects high potential.When the voltage of grid 11a increases to the threshold value electricity that the first p-type doped region 10a forms electron channel
When pressure is (about between 2.2~3.3V), the first p-type doped region 10a is near the surface of grid 11a silica first medium layer 3a
Place forms electronic shell, and the passage of electronics is formed between the first n-type doping area 2a and N-type epitaxy layer 6a.Due to back metal electricity
The current potential of pole 8a be higher than front metal electrode 1a, electronics by front metal electrode 1a, via the first n-type doping area 2a → P
Type doped region 10a is close to the surface → N-type epitaxy layer 6a → N-type single crystalline substrate 7a of first medium layer 3a, by back metal electrode
8a flows out, and forms by the electric current of back metal electrode 8a to front metal electrode 1a.
The first medium layer 3a connection grid 11a and the first p-type doped region 10a of trenched side-wall, second Jie of channel bottom
Matter layer 4a connection grid 11a and p-type doped region 5.Because the parasitic capacitance between grid 11a and back metal electrode 8a is equal to two
Depletion capacitance sum in silica medium layer capacitance and body carborundum, i.e.,
Wherein, CoxIt is silica dioxide medium layer capacitance, CDIt is depletion-layer capacitance, S has for silica dioxide medium layer capacitance
Effect area, toxIt is silica dioxide medium thickness degree, AeffIt is device depletion-layer capacitance area, XdepleteIt is depletion width.
Therefore, using thick silica second dielectric layer 4a, t can be increasedox, so advantageously reduce silica Jie
Matter layer capacitance.Reach the purpose for reducing the parasitic capacitance between device grids 11a and back metal electrode 8a.
Trench gate bottom is provided with the 3rd p-type doped region 5a and the second n-type doping area 12a doped region separately.And it is full
Sufficient Xj>2*Wn, Xj>2*Wp,.Meanwhile, as shown in Fig. 2 each separate the 3rd p-type doped region 5a in X-direction width it is equal
It is Wp, the second n-type doping area 12a is W in the width in X-directionn, width is Z in Z-direction2.Second n-type doping area
The Effective Doping concentration of 12a is set to Cn, then the impurity effective dose Q in each n-type doping arean=Cn*Wn*Z2*Xj；3rd p-type
The Effective Doping concentration of doped region 5a is set to Cp, the 3rd p-type doped region 5a in Z-direction with width as Z2+WpAs basic
Unit repeats, its effective impurity effective dose Qp=Cp*(2Wp*Wp+Wp*Wn+2Wp*Z2)*Xj；Meanwhile, the doping of the 3rd p-type
The impurity dose Q in areapWith the impurity dose Q in the second n-type doping areanFollowing relation should be met：
Wherein, VBIt is the device pressure voltage of demand, K is the pressure-resistant design department set in view of end use efficiency when designing device
Number, the span of K is 1.3~1.5；WpIt is the width of the 3rd p-type doped region.
The PN of both sides is formd due to the 3rd p-type doped region 5a on XY sections and YZ sections and the second n-type doping area 12a
Knot, and the PN junction for being formed to the second n-type doping area 12a with mutually strengthening the effect for exhausting, with back metal electrode 8a
Voltage difference with front metal electrode 1a gradually increases, and the 3rd p-type doped region 5a and the second n-type doping area 12a can be rapidly depleting.
Parasitic capacitance between grid 11a and back metal electrode 8a is equal to the equivalent electric capacity of second dielectric layer 4a and depletion layer equivalent electric
The series connection of appearance, it is rapidly depleting due to the 3rd p-type doped region 5a and the second n-type doping area 12a so that depletion width Xdeplete
Increase sharply, that is, cause that depletion layer equivalent capacity is reduced rapidly, reach posting between grid 11a and back metal electrode 8a
The effect that raw electric capacity can be reduced quickly.Meanwhile, the 3rd p-type doped region 5a Effective Dopings dosage according to formula (2) principle, more than
The Effective Doping dosage of two n-type doping area 12a, under identical voltage, the potential extension in the 3rd p-type doped region 5a is less than second
N-type doping area 12a, compared with channel bottom does not use p-type and N-type undoped spacer region, structure of the present invention can make peak electric field
By trench corner, the PN junction bottom that the 3rd p-type doped region 5a and N-type epitaxy layer 6a is formed is transferred to.The transfer of peak electric field,
The electric-field intensity at grid first medium layer 3a is advantageously reduced, hot carrier in jection to grid first medium layer 3a is reduced,
Be conducive to improving the operation reliably and with long-term of device.
It is as shown in Figure 3, Figure 4 other two kinds of variants of embodiment one, the front metal electrode of each variant
1, back metal electrode 8, N-type single crystalline substrate 7, N-type epitaxy layer 6, second dielectric layer 4, first medium layer 3, the first n-type doping area
2, the second p-type doped region 9, the first p-type doped region 10, grid 11 is identical with embodiment one.Also on XY sections
Three p-type doped region 5a are distributed in the both sides of the second n-type doping area 12a, the 3rd p-type doped region 5a in left side is mixed with the second N-type
Miscellaneous area 12a forms a PN junction, and the 3rd p-type doped region 5a on right side and the second n-type doping area 12a form another PN junction.
Distinctive points are the interval mode that p-type doped region and n-type doping area use on YZ sections, still can form multiple PN junction lists
Unit reaches the object of the invention.
Embodiment 2
It is as shown in Figure 5 a kind of trench gate metal oxide field-effect transistor of the offer of the embodiment of the present invention 2, including just
Face metal electrode 1b, back metal electrode 8b, the overleaf N-type single crystalline substrate 7b on metal electrode 8b, in N-type single crystalline substrate 7b
The N-type epitaxy layer 6b of upper formation, the first p-type doped region 10b formed on N-type epitaxy layer 6b.In N-type epitaxy layer 6b and first
The middle body of p-type doped region 10b is provided with vertical groove, and grid 11b, the P of depth ratio the of grid 11b are provided with the trench
The junction depth of type doped region 10b is deeper, and it is W that both differ3-T2, it is first between grid 11b side walls and the first p-type doped region 10b
Dielectric layer 3b, is second dielectric layer 4b between grid 11b bottoms and epitaxial layer 6b.As shown in Figure 6 and Figure 7, in N-type epitaxy layer 6b
Inside is additionally provided with the 3rd p-type doped region 5b and the second n-type doping area 12b being in contact with second dielectric layer 4b lower sections, the 3rd p-type
Doped region 5b and the second n-type doping area interlaced intervals of 12b, make to form multiple PN junction units on XY sections and YZ sections.
As shown in Figure 6 and Figure 7, it is multiple H-shaped on XZ sections that grid 11b is in thickness direction as different from Example 1
The repeat unit of shape so that grid 11b is the grid of left and right two that symmetrical separation is partly rendered as on XY sections in length direction.
And the grid width W of each separation2With groove width W, following relation should be met：
W≥2*W2+ 0.5 μm of formula (3)
By the way that using separate grid 11b, medium layer capacitance between grid 11b and back metal electrode 8b can be reduced
Area S.From formula (1), the mesh for reducing the parasitic capacitance between device grids 11b and back metal electrode 8b can be reached
's.But the grid width after separating diminishes so that the equivalent resistance increase of grid, it is unfavorable for quickly and uniformly opening for device
Close.Therefore, the separated grid structure of H-shaped is formed in z-direction using the isolating construction of compartment to grid.So reach
Both the parasitic capacitance between grid and electrode had been reduced, and will not have significantly increased resistance.
And the difference with embodiment one is also resided in, the second p-type doped region 9b is located at the first n-type doping area 2b bottoms, and
The contact hole of front metal 1b directly contacts the second p-type doped region 9b surfaces, the second p-type doped region 9b and front metal electrode
The depth of 1b contact surfaces is equal to or more than the depth W of the first n-type doping area 2b4(figure 6 illustrates both depth identical feelings
Condition)；And make the second p-type doped region 9b and first medium layer 3b apart from W5Less than the width W of the first n-type doping area 2b6；The
Concentration of the doping concentration of two p-type doped region 9b more than the first p-type doped region 10b.Can be reduced by this setup
Pressure drop on two p-type doped region 9b on current path, it is suppressed that what the first n-type doping area 2b and the first p-type doped region 10b was formed
The unlatching of PN junction, it is suppressed that the unlatching of parasitic BJT, while avoiding influence of the second p-type doped region to device threshold voltage.
Structure for embodiment two also proposed a kind of manufacture method, and this structure includes 7 layers of lithography layer, suitable according to making
Sequence is respectively
1) alignment mark lithography layer
2) N+ injections lithography layer
3) p-type injection lithography layer
4) etching groove lithography layer
5) p-type floating implanted layer
6) N-type floating implanted layer
7) P+ injections lithography layer
8) gate lithography layer
9) contact hole etching lithography layer
10) front metal lithography layer
Order specific implementation according to lithography layer is as follows：In N-type silicon carbide substrates, extension concentration is 8e15cm-3, thick
Spend the 4H silicon carbide epitaxial layers for 14 microns.
1) alignment mark is etched using alignment mark lithography layer on epitaxial layer, is used for follow-up photoetching contraposition.
2) micron silica of chemical vapor deposition 2, injecting lithography layer using N+ carries out N+ implanted layers injection opening etch,
Then the multiple ion implantation doping of N+ implanted layers is carried out.
3) by etching silicon dioxide, and 0.3 micron silica is deposited again, lithography layer is injected using p-type, form note
Enter window, and carry out the multiple ion implanting of p-type doped region, form the first p-type doped region；.
4) silica of 0.5 micron of chemical vapor deposition, using etching groove lithography layer, etching silicon dioxide is formed
Etching groove window, using RIE lithographic techniques, it is 2.2 microns that depth is etched in silicon carbide epitaxial layers, and width is 1.7 micro-
The groove of rice.
5) p-type floating implanted layer is used, aluminium ion is carried out to channel bottom and is repeatedly injected.
6) N-type floating implanted layer is used, phosphonium ion is carried out to channel bottom and is repeatedly injected.
7) injecting lithography layer using P+ carries out the multiple ion implanting of P+ implanted layers.In 1550 DEG C~1700 DEG C of temperature model
Carry out injecting the high-temperature annealing activation of ion in enclosing.Form 0.3 micron of depth, a N of mean concentration 1e18~4e20cm-3
Type doped region；1.5 microns of depth, the first p-type doped region of mean concentration 9e17~5e18cm-3；1.5 microns of depth, it is average dense
Spend the 3rd p-type doped region of 8e15~1e16cm-3；1.5 microns of depth, the 2nd N of mean concentration 7.5e15~9.5e15cm-3
Type doped region.
8) deposit and etch by multiple oxide layer, form the second dielectric layer that channel bottom thickness is 200nm, channel side
Wall thickness is the first medium layer of 55nm.0.55 micron of deposition thickness, the n-type doping polycrystalline of doping concentration 1e20~3e20cm-3
Grid, makes gate lithography layer etching form gate patterns layer.
9) etching window is formed using contact hole etching lithography layer, by RIE etching silicon carbide epitaxial layers, forming depth is
0.3 front metal electrode contact hole, and 0.2~0.3 micron of isotropic etching is carried out to silicon dioxide layer.
10) front deposit Ti/Al metal levels, and rapid thermal treatment is carried out, form Ohmic contact.Carved using gate lithography layer
Erosion metal level, forms front metal layer pattern.
11) back side deposit 40~80nm Ti 400~650nm Ni 900~1500nm Ag metal levels.
Above content is to combine specific/preferred embodiment further description made for the present invention, it is impossible to recognized
Fixed specific implementation of the invention is confined to these explanations.For general technical staff of the technical field of the invention,
Without departing from the inventive concept of the premise, its implementation method that can also have been described to these makes some replacements or modification,
And these are substituted or variant should all be considered as belonging to protection scope of the present invention.
Claims (10)
1. a kind of trench gate metal oxide field-effect transistor, including：
Front metal electrode,
Back metal electrode,
N-type single crystalline substrate on the back metal electrode,
The N-type epitaxy layer formed in the N-type single crystalline substrate,
The the first p-type doped region formed in the N-type epitaxy layer,
Vertical groove is provided with the middle body of the N-type epitaxy layer and the first p-type doped region, is set in the trench
There is grid, the junction depth of the first p-type doped region is deeper described in the depth ratio of the grid, the gate lateral wall and first p-type
It is first medium layer between doped region, is second dielectric layer, the second medium between the gate bottom and the epitaxial layer
Thickness degree is more than the first medium thickness degree,
The first n-type doping area is provided near the groove both sides on the first p-type doped region, away from the groove both sides also
Be provided with the second p-type doped region, the first n-type doping area and the second p-type doped region respectively with the front metal electrode
It is connected,
It is additionally provided with inside the epitaxial layer and is mixed with the 3rd p-type doped region and the second N-type that are in contact below the second dielectric layer
Miscellaneous area, makes the 3rd p-type doped region and the interlaced interval in the second n-type doping area, in length direction and thickness direction
Form multiple PN junction units.
2. trench gate metal oxide field-effect transistor as claimed in claim 1, it is characterised in that the 3rd p-type is mixed
Impurity dose of the impurity dose in miscellaneous area more than the second n-type doping area.
3. trench gate metal oxide field-effect transistor as claimed in claim 1, it is characterised in that the N-type monocrystalline lining
Bottom and the N-type epitaxy layer are silicon materials or carbofrax material.
4. trench gate metal oxide field-effect transistor as claimed in claim 1, it is characterised in that the grid is in thickness
It is the repeat unit of multiple H shapes on direction so that the grid is partly rendered as the left and right of symmetrical separation in the longitudinal direction
Two grids.
5. trench gate metal oxide field-effect transistor as claimed in claim 1, it is characterised in that second p-type is mixed
Miscellaneous area is located at the first n-type doping area bottom, and the contact hole of the front metal electrode directly contacts second p-type
Doped region surface, the second p-type doped region is equal to or more than a N with the depth of the front metal electrode contact surface
The depth of type doped region；And the second p-type doped region is mixed less than first N-type with the distance of first medium layer
Miscellaneous sector width；Concentration of the doping concentration of the second p-type doped region more than the first p-type doped region.
6. trench gate metal oxide field-effect transistor as claimed in claim 2, it is characterised in that the 3rd p-type is mixed
The impurity dose Q in miscellaneous areapWith the impurity dose Q in the second n-type doping areanFollowing relation should be met：
Wherein, VBIt is the device pressure voltage of demand, K is the pressure-resistant design ratio set in view of end use efficiency when designing device, K
Span be 1.3~1.5；WpIt is the width of the 3rd p-type doped region.
7. trench gate metal oxide field-effect transistor as claimed in claim 1, it is characterised in that the second dielectric layer
Thickness is at least more than 2 times of the first medium thickness degree.
8. trench gate metal oxide field-effect transistor as claimed in claim 4, it is characterised in that it is described each separate
Grid width W2With the groove width W, following relation should be met：
W≥2*W2+0.5μm
9. trench gate metal oxide field-effect transistor as claimed in claim 1, it is characterised in that the front metal electricity
Extremely nickel, aluminium more metal layers；The back metal electrode is nickel, titanium, nickel, silver or titanium, nickel, the more metal layers of silver.
10. a kind of method of manufacture groove gate metal oxide field-effect transistor, the transistor includes 7 layers of lithography layer, presses
Alignment mark lithography layer, N+ injections lithography layer, p-type injection lithography layer, etching groove lithography layer, p-type are respectively according to production order
Floating implanted layer, N-type floating implanted layer, P+ injections lithography layer, gate lithography layer, contact hole etching lithography layer, front metal light
Layer is carved, methods described includes：
Alignment mark is etched using alignment mark lithography layer on epitaxial layer, is used for follow-up photoetching contraposition；
The micron silica of chemical vapor deposition 2, injecting lithography layer using N+ carries out N+ implanted layers injection opening etch, Ran Houjin
The multiple ion implantation doping of row N+ implanted layers；
By etching silicon dioxide, and 0.3 micron silica is deposited again, lithography layer is injected using p-type, form injection window
Mouth, and the multiple ion implanting of p-type doped region is carried out, form the first p-type doped region；
The silica that 0.5 micron of chemical vapor deposition, using etching groove lithography layer, etching silicon dioxide forms groove and carves
Fenetre mouthful, using RIE lithographic techniques, etches depth for 2.2 microns in silicon carbide epitaxial layers, and width is 1.7 microns of ditch
Groove；
Using p-type floating implanted layer, aluminium ion is carried out to channel bottom and is repeatedly injected；
Using N-type floating implanted layer, phosphonium ion is carried out to channel bottom and is repeatedly injected；
Injecting lithography layer using P+ carries out the multiple ion implanting of P+ implanted layers.Enter within the temperature range of 1550 DEG C~1700 DEG C
The high-temperature annealing activation of row injection ion.Form 0.3 micron of depth, first n-type doping of mean concentration 1e18~4e20cm-3
Area；1.5 microns of depth, the first p-type doped region of mean concentration 9e17~5e18cm-3；1.5 microns of depth, mean concentration 8e15
The 3rd p-type doped region of~1e16cm-3；1.5 microns of depth, second n-type doping of mean concentration 7.5e15~9.5e15cm-3
Area；
Deposit and etch by multiple oxide layer, form the second dielectric layer that channel bottom thickness is 200nm, trenched side-wall thickness
It is the first medium layer of 55nm.0.55 micron of deposition thickness, the n-type doping polysilicon gate of doping concentration 1e20~3e20cm-3
Pole, makes gate lithography layer etching form gate patterns layer；
Etching window is formed using contact hole etching lithography layer, by RIE etching silicon carbide epitaxial layers, it is 0.3 just to form depth
Face metal electrode contact hole, and 0.2~0.3 micron of isotropic etching is carried out to silicon dioxide layer；
Front deposits Ti/Al metal levels, and carries out rapid thermal treatment, forms Ohmic contact.Use gate lithography layer etching metal
Layer, forms front metal layer pattern；
The back side deposit 40~80nm Ti 400~650nm Ni 900~1500nm Ag metal levels.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710179875.6A CN106876470A (en) | 2017-03-23 | 2017-03-23 | A kind of trench gate metal oxide field-effect transistor and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710179875.6A CN106876470A (en) | 2017-03-23 | 2017-03-23 | A kind of trench gate metal oxide field-effect transistor and its manufacture method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106876470A true CN106876470A (en) | 2017-06-20 |
Family
ID=59172994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710179875.6A Pending CN106876470A (en) | 2017-03-23 | 2017-03-23 | A kind of trench gate metal oxide field-effect transistor and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106876470A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729196A (en) * | 2019-10-28 | 2020-01-24 | 深圳市锐骏半导体股份有限公司 | Method for reducing on-resistance of groove type metal oxide semiconductor |
| CN113540209A (en) * | 2021-06-04 | 2021-10-22 | 复旦大学 | Radiation reinforcement SiC device structure based on distributed capacitance |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540770A (en) * | 2003-04-23 | 2004-10-27 | 株式会社东芝 | Semiconductor device and its mfg. method |
| US20050161732A1 (en) * | 2004-01-23 | 2005-07-28 | Makoto Mizukami | Semiconductor device |
| US20100006929A1 (en) * | 2008-07-08 | 2010-01-14 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US20100264488A1 (en) * | 2009-04-15 | 2010-10-21 | Force Mos Technology Co. Ltd. | Low Qgd trench MOSFET integrated with schottky rectifier |
| US20130001679A1 (en) * | 2011-06-30 | 2013-01-03 | Rohm Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN104247026A (en) * | 2012-04-19 | 2014-12-24 | 株式会社电装 | Silicon carbide semiconductor device and method for manufacturing same |
| CN105917470A (en) * | 2014-01-15 | 2016-08-31 | 罗伯特·博世有限公司 | Sic trench transistor and method for producing same |
| CN206672940U (en) * | 2017-03-23 | 2017-11-24 | 深圳基本半导体有限公司 | A kind of trench gate metal oxide field-effect transistor |
-
2017
- 2017-03-23 CN CN201710179875.6A patent/CN106876470A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540770A (en) * | 2003-04-23 | 2004-10-27 | 株式会社东芝 | Semiconductor device and its mfg. method |
| US20050161732A1 (en) * | 2004-01-23 | 2005-07-28 | Makoto Mizukami | Semiconductor device |
| US20100006929A1 (en) * | 2008-07-08 | 2010-01-14 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US20100264488A1 (en) * | 2009-04-15 | 2010-10-21 | Force Mos Technology Co. Ltd. | Low Qgd trench MOSFET integrated with schottky rectifier |
| US20130001679A1 (en) * | 2011-06-30 | 2013-01-03 | Rohm Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN104247026A (en) * | 2012-04-19 | 2014-12-24 | 株式会社电装 | Silicon carbide semiconductor device and method for manufacturing same |
| CN105917470A (en) * | 2014-01-15 | 2016-08-31 | 罗伯特·博世有限公司 | Sic trench transistor and method for producing same |
| CN206672940U (en) * | 2017-03-23 | 2017-11-24 | 深圳基本半导体有限公司 | A kind of trench gate metal oxide field-effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729196A (en) * | 2019-10-28 | 2020-01-24 | 深圳市锐骏半导体股份有限公司 | Method for reducing on-resistance of groove type metal oxide semiconductor |
| CN113540209A (en) * | 2021-06-04 | 2021-10-22 | 复旦大学 | Radiation reinforcement SiC device structure based on distributed capacitance |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107275407B (en) | Silicon carbide VDMOS device and manufacturing method thereof | |
| CN105932042B (en) | A kind of pair of division trench gate charge storage type IGBT and its manufacturing method | |
| CN102792448B (en) | Semiconductor device | |
| CN107256864B (en) | A kind of silicon carbide TrenchMOS device and preparation method thereof | |
| CN108735817A (en) | SiC semiconductor device with the offset in channel bottom | |
| CN105742346B (en) | Double division trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN107275406B (en) | A kind of silicon carbide TrenchMOS device and preparation method thereof | |
| CN105679816B (en) | A kind of trench gate charge storage type IGBT and its manufacturing method | |
| CN105870179B (en) | A kind of trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN109065621B (en) | Insulated gate bipolar transistor and preparation method thereof | |
| CN105914230A (en) | Ultra-low power consumption semiconductor power device and preparation method thereof | |
| CN109119463A (en) | A kind of lateral trench type MOSFET element and preparation method thereof | |
| CN104617149B (en) | Isolated form NLDMOS device and its manufacturing method | |
| CN110504310A (en) | A kind of RET IGBT and preparation method thereof with automatic biasing PMOS | |
| CN105993076B (en) | A kind of bi-directional MOS type device and its manufacturing method | |
| CN106997899A (en) | A kind of IGBT device and preparation method thereof | |
| CN109686781A (en) | A kind of superjunction devices production method of multiple extension | |
| CN105789291B (en) | A kind of double division trench gate charge storage type IGBT and its manufacturing method | |
| CN114823911A (en) | Groove silicon carbide MOSFET integrated with high-speed freewheeling diode and preparation method | |
| CN110518058A (en) | A kind of lateral trench type insulated gate bipolar transistor and preparation method thereof | |
| CN107425068A (en) | A kind of carborundum TrenchMOS devices and preparation method thereof | |
| CN107305909A (en) | A kind of inverse conductivity type IGBT back structure and preparation method thereof | |
| CN106876470A (en) | A kind of trench gate metal oxide field-effect transistor and its manufacture method | |
| CN110504313B (en) | Transverse groove type insulated gate bipolar transistor and preparation method thereof | |
| CN209626223U (en) | A kind of low-power consumption shielding grid-type semiconductor power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170620 |