CN106875974B - OTP memory device and method for accessing OTP memory - Google Patents
OTP memory device and method for accessing OTP memory Download PDFInfo
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- CN106875974B CN106875974B CN201710156206.7A CN201710156206A CN106875974B CN 106875974 B CN106875974 B CN 106875974B CN 201710156206 A CN201710156206 A CN 201710156206A CN 106875974 B CN106875974 B CN 106875974B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/26—Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability
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Abstract
The invention discloses an OTP (one time programmable) storage device and a method for accessing an OTP memory, which are used for realizing the operation of the OTP memory and generating interface time sequences corresponding to different instructions according to configurable instructions for accessing the OTP memory. Meanwhile, in the programming operation of the OTP memory, a brand new, efficient and highly reliable programming method is provided, and aiming at the redundancy processing of OTP programming addresses and adopting a method of allowing up to 16 times of pulse programming to the same address in the programming operation, the problem that programming errors are easy to occur when the OTP memory is accessed is solved to a great extent, the reliability of the OTP memory is greatly improved, and the utilization of the OTP memory is realized to the greatest extent.
Description
Technical Field
The present invention relates to the field of one-time programmable (OTP, one Time Programable) memories, and more particularly to a method and apparatus for accessing an OTP memory.
Background
With the continuous development of the electronic information society, the data storage demand has been increasing explosively. Compared with MASK and Flash memories, OTP memories have the advantages of both MASK and Flash memories, and have certain flexibility and low cost. And thus also plays an irreplaceable role in the embedded system or the chip as storage of information that cannot be changed after one-time programming or storage of encryption chip key information. OTP memory is well suited for one-time programmable storage of application specific data, in a System On a Chip (SOC) System, it is necessary to store a lot of specific one-time information, such as Chip serial number, interface closure information, and key information about Chip security, etc., which is not allowed to be changed by a customer after programming in the whole System test Chip, and which is not erased, i.e. is not modifiable after one-time programming. The MASK is adopted to make a photoetching plate, so that the flexibility is poor, and the cost of Flash memory is high. Therefore, OTP memory is used for storing specific information, so that hardware and research and development cost are reduced to the greatest extent.
When programming, reading and other accessing the OTP memory, a hardware controller is needed, the specific operation of accessing the OTP memory is judged whether to be a specific time sequence of converting a valid instruction into the OTP memory through analyzing the instruction, and the operations of reading, programming, resetting, sleeping and waking up are completed according to the interface time sequence of the OTP memory. FIG. 2 is a block diagram of accessing an OTP memory, including various instructions for accessing the OTP memory, where the hardware controller is required to generate corresponding timing sequences according to different access instructions to complete the access to the OTP memory.
Because of the low cost of storing some specific information, OTP memories are becoming more and more widely used in the memory field. The hardware circuit provides different time sequence circuits to drive the OTP memory according to different instructions, so that the OTP memory device is accessed. Because of the self factors, the OTP memory device is easy to make mistakes in the process of reading and programming, and how to reduce the error rate in the process of programming and reading the OTP, improve the reliability of the OTP memory and become a technical difficulty in the field of OTP memories. Secondly, with the increasingly wide application of the security chip, after the OTP memory realizes the programming of the key information, the user does not want to read the key information, so that special processing is needed when the OTP key information is read, and how to do special processing is needed to ensure that the key information stored in the OTP is not compromised, and ensuring that the chip security technology is also a scheme lacking in the current OTP memory access technology. Furthermore, adding fault tolerant hardware circuit units inside the OTP memory chip greatly increases the OTP memory chip area and has poor portability. Both of these disadvantages greatly increase development time and cost of accessing the OTP memory.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method and a device for accessing an OTP memory, which can flexibly configure different instructions to access the OTP memory and generate an interface time sequence of accessing the OTP memory corresponding to the instructions so as to complete programming, reading, resetting, waking and sleeping operations of the OTP memory. The method of the invention improves the yield of the OTP memory to a great extent, solves the problem of easy error of OTP in the programming process, and greatly improves the reliability of the OTP memory device. And the key information of the important information stored in the OTP is correspondingly scrambled during reading, so that the security of the data is protected.
In order to solve the above technical problems, the present invention provides a method for accessing an OTP memory, comprising the following steps:
step 1: defining a series of instructions for operating the OTP memory;
step 2: powering up to read all area information of the OTP memory, wherein the area information comprises OTP memory mode information, OTP memory interface closing information, OTP memory system area closing information, OTP memory user area closing information and key area information;
step 3: analyzing the defined instruction for operating the OTP memory, and driving the timing sequence for accessing the OTP memory according to the analyzed instruction;
step 4: entering a machine working mode, sending an OTP memory programming key instruction, analyzing the programming key instruction, generating an OTP memory interface time sequence corresponding to the instruction by an OTP time sequence generator, programming key data into the OTP memory, reading key information, and scrambling the read key information;
step 5: entering a normal working mode, sending an OTP memory programming information instruction, programming a chip serial number, generating a programming OTP memory time sequence by an OTP time sequence generator, and programming the chip serial number to a corresponding area in the OTP memory;
step 6: and sending an OTP memory programming information instruction, decoding the instruction through an instruction decoder, generating a programming OTP memory time sequence by an OTP time sequence generator, and transmitting the programming OTP memory time sequence to an OTP memory device to finish programming interface closed information and programming system area information.
Further, the defining a series of instructions to operate the OTP memory includes: different instructions for accessing the OTP memory are provided for the CPU or the machine mode configuration, and the series of instructions are used for operating the OTP memory to finish the operations of programming, reading, resetting, waking up and the like of the OTP memory. The series of instructions includes: an OTP memory sleep mode, an OTP memory wake mode, a reset OTP memory, OTP memory programming information, an OTP memory programming key, a read OTP memory and an OTP memory self-test mode;
the instructions for operating the OTP memory defined by the parsing include:
defining a specific instruction for accessing the OTP memory;
waiting for an access OTP memory instruction;
checking the OTP memory instruction; and
determining whether an instruction for accessing the OTP memory is a valid instruction, if so, transmitting the instruction to an OTP time sequence generator, and if not, terminating the access of the OTP memory;
the OTP timing generator is used for generating specific timing sequence for generating the parsed instruction for effectively accessing the OTP memory;
the OTP memory programming key instruction or the OTP memory programming information instruction adopts a method which adopts redundancy processing of OTP memory programming addresses and adopts programming operation implementation of the same address in programming operation and can allow up to 16 times of pulse programming.
The redundancy processing for the allocation of the addresses of the OTP memory programming operation comprises the following steps:
when one-bit data programming operation is carried out on the OTP memory, mapping the bit data to 4-bit physical addresses of the OTP memory and programming the data in sequence, if the programming of the addresses is successful, the configured one-bit data is considered to be successful, otherwise, the bit data is considered to be not successfully programmed.
Each bit data programming operation in the pair of OTP memory 4-bit physical addresses includes:
configuring an address to be programmed, wherein the programming address is equal to the provided initial programming address;
applying 3 program pulse voltages at the initial program address location;
continuing to apply 1 programming pulse voltage on the basis of applying 3 programming pulse voltages;
a program verification operation;
judging whether the programmed data is 1 or not according to the data obtained by the programming verification operation, wherein the data programmed by the OTP memory is 1, the unprogrammed data is 0, if the programmed data is 1, the programming operation on the address is successful, the programming operation on the next address is continuously executed according to the method, and if the programmed data is 0, the next step is executed;
judging whether the programming pulse voltage is applied to the position for 16 times, if the programming pulse voltage is not applied to the designated OTP memory address position for 16 times, continuing to apply the pulse voltage, judging whether programming data is 1 or not when the pulse voltage is applied once, and judging whether the programming pulse voltage is programmed to 16 times or not; if the 16 times programming voltage is applied to the location or the data is "0", the programming fails.
The invention also provides an apparatus comprising an OTP memory and an access OTP memory, wherein the OTP memory comprises: the chip serial number area is used for storing the chip serial number; the interface sealing area is used for storing related interface sealing information; OTP memory mode of operation: the operation mode for storing the OTP memory comprises a machine working mode and a normal working mode; the system closed control area is used for storing control information of the closed system area; the user closed control area is used for storing control information of the user area; a system key area for storing a key information area; and a user area for storing information to be stored by the user.
The beneficial technical effects of the invention are as follows: a method and a device for accessing OTP memory are provided, and different operation instructions can be flexibly configured through two modes of a CPU or a machine, and the interface time sequence of the OTP memory for accessing the corresponding instructions is generated. And the specific information key information is subjected to strict encryption processing outside the OTP storage device, so that the security of the chip is effectively ensured. The method of adopting address fault tolerance processing and applying programming pulse voltage to the same programming address for multiple times ensures that data are correctly programmed to the corresponding area of the OTP memory, solves the problem that OTP is easy to make mistakes in the programming process, ensures the correctness of the data, greatly improves the yield of the OTP memory and greatly enhances the reliability of accessing the OTP memory device.
Drawings
FIG. 1 is an OTP memory region profile according to one embodiment of the invention.
FIG. 2 is an operational block diagram of accessing OTP memory according to one embodiment of the invention.
FIG. 3 is a block diagram of an OTP memory control circuit according to one embodiment of the invention.
FIG. 4 is a flowchart of OTP memory power-on read circuit operation in accordance with one embodiment of the present invention.
FIG. 5 is a method of resolving instructions by an OTP memory instruction decoder according to one embodiment of the invention.
FIG. 6 is a diagram of address allocation and redundancy handling for OTP memory programming, read operations, according to one embodiment of the invention.
FIG. 7 is a programming algorithm flow diagram of an OTP memory programming algorithm module circuit in accordance with one embodiment of the invention.
Detailed Description
The invention will be described in further detail with reference to the drawings and the detailed description. The method is mainly used for accessing the OTP memory and realizing different operations of the OTP memory, including programming, reading, resetting, waking up, sleeping and OTP self-test operations. When the OTP memory is programmed, the data can not be correctly stored in the OTP memory device due to easy programming errors, the invention provides redundancy processing for the programming address, meanwhile, the same programming address can be allowed to be applied with programming pulse voltage for up to 16 times, the programming data is strictly ensured to be correctly programmed into the OTP memory device, the programming key information is programmed into the OTP memory by adopting a machine working mode, and when the key information is read, the key information read from the OTP memory device is scrambled by adopting a scrambling circuit, so that the high safety of the key information is ensured, and the protection requirement of special information is met. Detailed description is as follows.
Referring to fig. 1, in the embodiment of the present invention, the area distribution of the OTP memory is: the chip serial number area is used for storing the chip serial number; the interface sealing area is used for storing related interface sealing information; OTP memory mode of operation: the operation mode for storing the OTP memory comprises a machine working mode and a normal working mode; the system closed control area is used for storing control information of the closed system area; the user closed control area is used for storing control information of the user area; a system key area for storing a key information area; and the user area is used for storing information to be stored by the user.
Referring to fig. 2, to access a block diagram of an OTP memory, implementing operations on the OTP memory includes: programming, reading, resetting, waking up, sleeping, OTP self-test operations are performed by the OTP controller circuit, as shown in fig. 2, the OTP memory instructions to be accessed include the following:
the OTP memory is in a sleep mode, namely the current OTP is in a non-working state, so that the instruction can be placed when the OTP memory is not used, the power consumption of the system is reduced, and the configuration of the instruction can be completed by a CPU (Central processing Unit) or a machine platform mode;
an OTP memory wake-up mode for waking up OTP from a sleep mode, when the OTP memory device needs to be operated, such as programming data into the OTP memory and reading data, the OTP memory needs to be switched from the sleep mode to the wake-up mode firstly, and the configuration of the instruction can be completed by a CPU or a machine platform mode;
resetting the OTP memory, wherein the OTP memory needs to be reset before the OTP memory is operated, and the OTP memory device needs to be reset by the reset operation when the OTP memory is switched between instructions, and the configuration of the instructions can be completed by a CPU (Central processing Unit) or a machine mode;
programming information of the OTP memory, wherein the instruction needs to be configured in the OTP programming operation, such as chip serial number, chip interface sealing information and system information programming, the OTP memory programming operation is completed by configuring an OTP_PROGRAMINFO instruction, and the configuration of the instruction can be completed by a CPU or a machine mode;
the OTP memory programming key only aims at the storage of programming key information in the OTP memory, and in order to ensure the strict security of the key information, the instruction must be configured by a machine mode;
reading the OTP memory, executing the reading operation of the information of each area of the OTP memory, wherein the configuration of the instruction can be completed by a CPU or a machine mode;
and an OTP memory self-test mode for executing self-test on the OTP memory device, wherein the configuration of the instruction can be completed by a CPU or a machine mode.
The device for accessing the OTP memory comprises a CPU or a machine completion instruction configuration, a power-on reading circuit, a bus control circuit, a multiplexer circuit, an OTP time sequence generator circuit, a programming algorithm module circuit, a scrambling circuit and an OTP memory device which are sequentially connected, wherein all modules are realized by adopting an all-digital logic circuit;
the CPU or machine mode configuration circuit: instructions for configuring access to the OTP memory;
the power-on read circuit: when the OTP memory is powered on, firstly reading information of each area of the OTP memory, wherein the information comprises OTP memory mode information, OTP memory interface sealing information, OTP memory system area sealing information, OTP memory user area sealing information and key area information;
the bus control circuit: the CPU or the machine is configured to be used for loading a series of instructions configured by the CPU or the machine and analyzing the defined instructions for operating the OTP memory; the instruction register circuit is used for storing a series of instructions configured by the CPU or the machine, and the instruction decoder circuit is used for translating the configured instructions into specific effective instructions and transmitting the specific effective instructions to the multiplexer.
The multiplexer: an instruction for selecting the power-on read circuit to read the information instruction and transmit to the OTP operation time sequence generation controller or the bus control circuit to transmit to the OTP operation time sequence generation controller;
the OTP timing generator circuit: specific time sequence circuits for generating different OTP memory access instructions, including reset, wake-up, programming, reading and sleep operations, generate corresponding OTP memory access time sequence circuits according to the instructions configured by a CPU or a machine for specific OTP memory operation, and transmit the OTP memory access time sequence circuits to an OTP memory device interface;
the programming algorithm module circuit: aiming at the programming operation of the OTP memory, the problem of easy error in programming the OTP memory is solved, the algorithm circuit realizes that when the OTP memory is programmed, redundancy processing is carried out on an address to be programmed of the OTP memory and processing of applying allowable 16 times of programming pulse voltage is adopted for each bit of data programming, and the module circuit is realized by an all-digital circuit and adopts state machine control to realize a programming algorithm.
The scrambling circuit: the key information is read from the OTP memory to be encrypted, namely the read key data is scrambled by a scrambling circuit, so that the key data seen by a user is not the data actually programmed into the OTP memory, thereby protecting the key information security.
Referring to fig. 3, a block diagram of an OTP memory control circuit according to an embodiment of the invention is shown. Accessing the OTP memory firstly needs to send an operation instruction to the OTP memory by adopting a CPU or a machine mode. Issuing instructions to the OTP memory includes: the normal working mode adopts a CPU to configure the instruction of the OTP memory to be operated and the machine test mode adopts an automatic test equipment machine to issue the operation instruction. The invention adopts two modes of CPU or machine to flexibly realize the access to the OTP memory. Transmitting an instruction configured for the CPU or the machine to the bus controller through a Multiplexer (MUX) circuit; referring to fig. 2, the instructions configured by the CPU or the machine include: an OTP memory sleep mode, an OTP memory wake mode, a reset OTP memory, OTP memory programming information, an OTP memory programming key, a read OTP memory, and an OTP memory self-test mode. The CPU or the machine station configures the instructions for operating the OTP memory to be transmitted to the bus control module circuit, the instructions are stored in the instruction register of the bus control circuit, the instruction decoder circuit of the bus control module analyzes the defined instructions for operating the OTP memory, and the effective instructions for specifically operating the OTP memory are transmitted to the OTP time sequence generator through the MUX circuit. When the power-on reading circuit is powered on, reading the distribution information of each area of the OTP memory, namely the OTP memory shown in FIG. 1; the power-on reading circuit transmits a reading operation command to the OTP time sequence generator through a MUX (multiplexer) circuit to generate a reading time sequence so as to realize reading of all areas of the OTP memory; after the instruction decoder circuit analyzes the OTP memory accessing instruction configured by the CPU or the machine, the OTP memory accessing instruction is generated to the OTP time sequence generator, the time sequence generator realizes the specific time sequence generation of the configured instruction, and the OTP memory accessing is completed according to the configured instruction time sequence. The programming algorithm module circuit shown in fig. 3, when programming the OTP memory for the OTP memory programming key instruction or the OTP memory programming information instruction, adopts the algorithm of the invention, and when programming the OTP memory, the algorithm circuit performs redundancy processing on the address to be programmed of the OTP memory and performs processing of applying a pulse voltage for programming each bit of data for 16 times, and the module circuit is realized by an all-digital circuit and realizes the programming algorithm by adopting state machine control. When the key information of the OTP memory is read, the key information is strictly kept secret according to the special requirement of the key information, the chip safety is ensured, and the scrambling circuit is adopted to scramble the data read from the OTP memory, so that the key data seen by a user is not the data actually programmed to the OTP memory, thereby protecting the key information safety.
A method of accessing OTP memory, comprising:
1) Defining a series of instructions to operate the OTP memory by adopting a CPU mode or a machine mode according to the specific operation of the OTP memory to be accessed; for programming key information, in order to ensure the strict security of the key information, the programming key instruction can only be configured in a machine mode. The configuration of the rest instructions can adopt a CPU mode (namely a normal working mode) or a machine mode. The configurable set of instructions for accessing the OTP memory includes: an OTP memory sleep mode, an OTP memory wake mode, a reset OTP memory, OTP memory programming information, an OTP memory programming key, a read OTP memory, and an OTP memory self-test mode.
2) The power-on reading of the OTP area information is completed by a power-on reading circuit shown in fig. 1, and an operation flow chart of the power-on reading circuit is shown in fig. 7, wherein the operation flow chart comprises OTP mode information, OTP interface closed information, OTP system area closed information, OTP user area closed information and key area information, the key area information is scrambled information, and the security of the key information is ensured.
Referring to fig. 3, first, an instruction for operating the OTP memory is defined by a CPU or a machine, and each area information of the OTP memory is read by a power-on reading circuit, and each area information of the OTP memory is referred to in fig. 1.
Referring to fig. 4, implementing a power-on read of an OTP memory includes: the method comprises the steps of chip power-on reset, power-on wake-up OTP memory, power-on reset OTP memory, OTP memory mode information reading, OTP memory interface information reading, OTP memory system area information reading, user area information reading, key area information reading, entering an OTP sleep mode, and ending all areas of the OTP memory after power-on reading.
3) Analyzing the defined instruction for operating the OTP memory, and driving the OTP access time sequence according to the analyzed instruction; the instruction decoder is used for transmitting specific instructions configured by the CPU or the machine to the instruction decoder circuit, and the instruction decoding comprises: defining a specific instruction for accessing the OTP, waiting for accessing the OTP instruction, checking the OTP instruction, judging whether the OTP instruction is a valid instruction or not, and if the OTP instruction is the valid instruction, transmitting the OTP instruction to an OTP time sequence generator, generating a time sequence corresponding to the instruction, and completing the access to the OTP memory; if the instruction is invalid, the following steps are not continued to be executed, and the OTP memory is terminated to be accessed. The so-called invalidation instruction includes: and when the key information is programmed, an OTP programming information instruction is sent, the programming key instruction is configured in a normal working mode, the OTP self-test mode instruction is configured in a CPU mode, and the self-test mode instruction can only aim at a machine mode.
Referring to fig. 5, which is a method for parsing an instruction by an OTP memory instruction decoder according to an embodiment of the invention, the parsing the defined instruction for operating the OTP memory includes:
defining a specific instruction for accessing the OTP memory;
waiting for an access OTP memory instruction;
checking the OTP memory instruction; and
determining whether the OTP memory accessing instruction is a valid instruction, if so, transmitting the OTP memory accessing instruction to an OTP time sequence generator, executing an OTP memory operation instruction, and if not, terminating the OTP memory accessing instruction.
4) Entering a machine working mode, sending an OTP memory programming key instruction, analyzing the programming key instruction, generating an OTP memory interface accessing time sequence corresponding to the instruction by an OTP time sequence generator, and programming key data into the OTP memory. Because the key information has specificity and needs to ensure the safety of the information, when the key information is programmed, a machine working mode is required to be adopted to complete the programming of the key information to the corresponding area of the OTP memory; and the key information is read, scrambling processing is carried out on the read key information, information leakage which is truly programmed to the OTP storage device is prevented, and the security of the key is strictly ensured.
5) Referring to fig. 1, an OTP memory map according to an embodiment of the invention is shown, and therefore, it is necessary to program information in an OTP-related area, at this time, an OTP programming information command is sent, a chip serial number is programmed, and an OTP timing generator generates a programming OTP memory timing to program the chip serial number to a corresponding area in the OTP memory.
6) In the normal working mode, an OTP memory programming information instruction is sent, the instruction is decoded through an instruction decoder, an OTP time sequence generator generates a programming OTP memory time sequence, and the programming OTP memory time sequence is sent to an OTP memory device to finish programming interface closed information and programming system area information.
In order to solve the problem of error easily when programming data of the OTP memory, the reliability of the OTP memory is increased, and the operation of an OTP memory programming key instruction or an OTP memory programming information instruction adopts the address redundancy processing and the data of the same address to allow the application of programming pulse voltage for up to 16 times.
Referring to FIG. 6, an address allocation and redundancy process diagram for OTP memory programming, read operations is shown, according to one embodiment of the present invention. Firstly, the programming operation performs fault tolerance processing on the address of the OTP memory, namely, each programming data corresponds to the physical address of the 4-bit OTP memory, each bit of the 4-bit physical address is programmed in sequence, when the programming of not less than 3-bit address is successful, the configured bit data can be considered to be successfully programmed, otherwise, the configured bit data is considered to be failed to be programmed. As shown in fig. 6, the address for accessing the OTP memory in the embodiment of the invention is formed of a 13-bit address including a system address, a logical bit address, and a physical address. The system address and the logical bit address are specific areas of the selected OTP memory. For a programming address, a one-bit logical address maps redundancy of a 4-bit physical address, and programs each bit of the 4-bit address at a time, wherein when not less than 3 bits of addresses are successfully programmed, the configured bit of data can be considered to be successfully programmed, otherwise, the configured bit of data is considered to be failed to be programmed.
Wherein each bit data programming operation of the pair of OTP memory 4-bit physical addresses includes, referring to fig. 7, including:
starting an OTP memory programming algorithm;
configuring an address to be programmed, wherein the programming address is equal to the provided initial programming address;
applying 3 programming pulse voltages at the provided initial programming address locations, and recording N (representing the number of recording programming pulses) equal to 0 times;
continuing to apply 1 programming pulse voltage on the basis of applying 3 programming pulse voltages;
a program verification operation;
the data obtained by the program verification operation determines whether the programmed data is 1 (OTP memory programming data is "1", unprogrammed data is "0"), and if the programmed data is "1", it means that the current programming operation for the address is successful, and the programming operation for the next address is continued according to the method. If the programming data is "0", executing the next step;
it is determined whether 16 times of programming pulse voltage is applied to the position, and the number of times of determination is counted by N. If the address position of the OTP memory is not reached to the applied programming voltage for 16 times, continuing to apply pulse voltage, and adding one to N at the moment; determining whether the programming data is 1 or not every time the pulse voltage is applied (i.e. every time N is increased by one), determining whether the programming pulse voltage is programmed to 16 times, and verifying that the programming data is successful in 16 times of programming pulse operation and the like, so that the address data is programmed successfully; if the 16 times programming voltage is applied to the location or the data is "0", the programming fails.
According to the programming method, under the normal working mode, programming storage operation of the OTP memory interface closed information and the system area information is completed, and the OTP memory is accessed.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention and not for limiting it, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that: the technical scheme of the invention can be modified or replaced by the same, and the modified technical scheme cannot deviate from the spirit and scope of the technical scheme of the invention.
Claims (10)
1. A method of accessing OTP memory, comprising:
step 1: defining a series of instructions for operating the OTP memory;
step 2: powering up to read all area information of the OTP memory, wherein the area information comprises OTP memory mode information, OTP memory interface closing information, OTP memory system area closing information, OTP memory user area closing information and key area information;
step 3: analyzing the defined instruction for operating the OTP memory, and driving the timing sequence for accessing the OTP memory according to the analyzed instruction;
step 4: entering a machine working mode, sending an OTP memory programming key instruction, analyzing the programming key instruction, generating an OTP memory interface time sequence corresponding to the instruction by an OTP time sequence generator, programming key data into the OTP memory, reading key information, and scrambling the read key information;
step 5: entering a normal working mode, sending an OTP memory programming information instruction, programming a chip serial number, generating a programming OTP memory time sequence by an OTP time sequence generator, and programming the chip serial number to a corresponding area in the OTP memory;
step 6: and sending an OTP memory programming information instruction, decoding the instruction through an instruction decoder, generating a programming OTP memory time sequence by an OTP time sequence generator, and transmitting the programming OTP memory time sequence to an OTP memory device to finish programming interface closed information and programming system area information.
2. The method of accessing OTP memory of claim 1 wherein the series of instructions comprises: an OTP memory sleep mode, an OTP memory wake mode, a reset OTP memory, OTP memory programming information, an OTP memory programming key, a read OTP memory, and an OTP memory self-test mode.
3. The method of accessing OTP memory of claim 1 wherein said parsing defined instructions for operating the OTP memory comprises:
defining a specific instruction for accessing the OTP memory;
waiting for an access OTP memory instruction;
checking the OTP memory instruction; and
it is determined whether the access OTP memory instruction is a valid instruction, and if so, it is transferred to an OTP timing generator.
4. A method of accessing OTP memory as recited in claim 3, wherein said determining whether the instruction to access the OTP memory is a valid instruction, and terminating the access of the OTP memory if the instruction is an invalid instruction.
5. The method of accessing OTP memory of claim 1 wherein the OTP timing generator is operative to generate a specific timing of resolved valid access OTP memory instructions.
6. The method of accessing an OTP memory of claim 1 wherein the OTP memory programming key instruction or the OTP memory programming information instruction employs a redundancy process for an OTP memory programming address and a method of performing N-time pulse programming for a programming operation of the same address in a programming operation, wherein N is 16 or less.
7. The method of accessing OTP memory of claim 6 wherein either step 4 or step 5 further comprises performing redundancy processing on allocation of addresses for OTP memory programming operations, the redundancy processing comprising:
when one-bit data programming operation is carried out on the OTP memory, mapping the bit data to 4-bit physical addresses of the OTP memory and programming the data in sequence, if the programming of the addresses is successful, the configured one-bit data is considered to be successful, otherwise, the bit data is considered to be not successfully programmed.
8. The method of accessing OTP memory of claim 7 wherein said programming each bit of data in the 4-bit physical address of the OTP memory comprises:
configuring an address to be programmed, wherein the programming address is equal to the provided initial programming address;
applying 3 program pulse voltages at the initial program address location;
continuing to apply 1 programming pulse voltage on the basis of applying 3 programming pulse voltages;
a program verification operation;
judging whether the programmed data is 1 or not according to the data obtained by the programming verification operation, wherein the data programmed by the OTP memory is 1, the unprogrammed data is 0, if the programmed data is 1, the programming operation on the address is successful, the programming operation on the next address is continuously executed according to the method, and if the programmed data is 0, the next step is executed;
judging whether the programming pulse voltage is applied to the position for 16 times, if the programming pulse voltage is not applied to the designated OTP memory address position for 16 times, continuing to apply the pulse voltage, judging whether programming data is 1 or not when the pulse voltage is applied once, and judging whether the programming pulse voltage is programmed to 16 times or not; if the 16 times programming voltage is applied to the location or the data is "0", the programming fails.
9. The method of accessing OTP memory of claim 1 wherein the OTP memory comprises: the chip serial number area is used for storing the chip serial number; the interface sealing area is used for storing related interface sealing information; OTP memory mode of operation: the operation mode for storing the OTP memory comprises a machine working mode and a normal working mode; the system closed control area is used for storing control information of the closed system area; the user closed control area is used for storing control information of the user area; a system key area for storing a key information area; and a user area for storing information to be stored by the user.
10. An apparatus implementing the method of accessing OTP memory of any of claims 1-9, comprising an OTP memory and an apparatus for accessing the OTP memory, wherein the OTP memory comprises: the chip serial number area is used for storing the chip serial number; the interface sealing area is used for storing related interface sealing information; OTP memory mode of operation: the operation mode for storing the OTP memory comprises a machine working mode and a normal working mode; the system closed control area is used for storing control information of the closed system area; the user closed control area is used for storing control information of the user area; a system key area for storing a key information area; and a user area for storing information to be stored by the user.
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| CN108170607B (en) * | 2018-01-03 | 2021-05-18 | 上海传英信息技术有限公司 | Control device and control method of OTP switch |
| CN109286546B (en) * | 2018-11-20 | 2023-08-29 | 深圳市卓越信息技术有限公司 | Multi-point access type intelligent interconnection equipment and interconnection communication method |
| CN110275845B (en) * | 2019-06-29 | 2021-11-19 | 江苏芯盛智能科技有限公司 | Memory control method and device and electronic equipment |
| CN112306559A (en) * | 2019-07-26 | 2021-02-02 | 珠海零边界集成电路有限公司 | Storage starting system and method |
| CN112286468B (en) * | 2020-12-28 | 2021-03-16 | 湖北芯擎科技有限公司 | Access control method and device of storage device and electronic equipment |
| CN113312224B (en) * | 2021-06-08 | 2022-09-13 | 合肥磐芯电子有限公司 | MCU for testing OTP type and testing method thereof |
| CN114489516B (en) * | 2022-02-08 | 2024-06-25 | 合肥芯颖科技有限公司 | Data storage device and method |
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